CN114850080A - Mass production test method, system and storage medium - Google Patents
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Abstract
The application discloses a mass production test method, a mass production test system and a storage medium, so that the high quality of test data, the low yield loss and the short test time can be considered in mass production test. The method comprises the following steps: acquiring actual measurement parameters of chips of the same type and different batches; respectively carrying out combined clamping control on failure rate and yield of each batch based on the measured parameters; carrying out component average test on the problem batches screened by the joint control; and outputting the test result of the current batch production according to the joint clamping control result and the average test result of the components.
Description
Technical Field
The present invention relates to the field of mass production testing technologies, and in particular, to a mass production testing method, system and storage medium.
Background
The last process in the chip production flow is a mass production test. The basic purpose of mass production testing is to eliminate chips that do not meet design specifications (also called outlier chips or failed products) in the chip production process, thereby improving the early reliability of the chips. With the improvement of product integration level, the semiconductor industry has raised higher requirements on the aspects of test data quality, yield loss, test time and the like of mass production test, but the existing mass production test scheme cannot give consideration to the three aspects of high test data quality, low yield loss and short test time.
Disclosure of Invention
In view of the above, the present invention provides a method, a system and a storage medium for mass production testing, so as to achieve the balance of high test data quality, low yield loss and short test time during mass production testing.
A method of mass production testing, comprising:
acquiring actual measurement parameters of chips of the same type and different batches;
respectively carrying out combined clamping control on failure rate and yield of each batch based on the measured parameters;
carrying out component average test on the problem batches screened by the joint control;
and outputting the test result of the current batch production according to the joint clamping control result and the average test result of the components.
Optionally, the performing component average test on the problem lot screened by the joint card control includes: and carrying out component average test on good products in the problem batches screened by the joint clamping control.
Optionally, the outputting the test result of the present batch production according to the joint clamping control result and the average test result of the components includes:
and marking the failed products screened by the combined clamping control and the failed products screened by the component average test as all the failed products determined by the mass production test, and obtaining the rest products.
Optionally, the performing, by the joint clamping control of the failure rate and the yield rate on each batch respectively includes:
respectively calculating the yield of each batch and the failure rate of each batch on the mth pre-specified test item; m is 1, 2, …, k is an integer greater than 0;
for each batch, when the yield of the batch does not exceed the preset lower yield limit and the failure rate of the batch on the mth pre-specified test item does not exceed the preset upper failure rate limit corresponding to the test item, judging the batch to be a normal batch; otherwise, the batch is determined to be a problem batch.
Optionally, in the execution process of the mass production testing method, the method further includes:
judging whether the preset updating time of the lower yield limit and the upper failure rate limit is reached, judging whether the number of chips tested at present from the last updating of the lower yield limit and the upper failure rate limit reaches a first preset number, and updating the lower yield limit and the upper failure rate limit when at least one of the preset updating time and the first preset number is reached.
Optionally, in the component average test, chips that do not exceed the upper specification limit and the lower specification limit are determined as good products, and the rest are failed products.
Optionally, in the execution process of the mass production testing method, the method further includes:
judging whether the preset updating time of the upper specification limit and the lower specification limit is reached, judging whether the number of chips tested at present from the last calculation of the upper specification limit and the lower specification limit reaches a second preset number, and updating the upper specification limit and the lower specification limit when at least one of the regular updating time and the second preset number is reached.
Optionally, the component averaging test includes: a dynamic component averaging test or a static component averaging test; the dynamic component averaging test has a higher frequency of updating the specification upper limit and the specification lower limit than the static component averaging test.
A mass production test system comprising:
the acquisition unit is used for acquiring the actual measurement parameters of chips of the same model and different batches;
the processing unit is used for respectively carrying out joint clamping control on failure rate and yield of each batch based on the measured parameters; carrying out component average test on the problem batches screened by the joint control; and outputting the test result of the current batch production according to the joint clamping control result and the average test result of the components.
A storage medium having stored thereon a program which, when executed by a processor, implements any of the mass production testing methods as disclosed above.
According to the technical scheme, the mass production test is carried out on the chips of each batch by adopting a method of combining the combined clamping control of failure rate and yield with the average test of the parts, the problem batch is screened out by the combined clamping control of failure rate and yield, the problem batch is not directly discarded as the failed product, and further fine screening is carried out by the average test of the parts so as to screen out the good product and the failed product in the problem batch. The scheme combining thickness screening and thickness screening is beneficial to saving the total testing time, can ensure the quality and reliability of the chip, can not cause meaningless yield loss of the chip, and is suitable for being popularized to chips with relatively low added values, such as consumer electronic chips and the like.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a mass production testing method according to an embodiment of the present invention;
FIG. 2 is a flowchart of a joint control method for failure rate and yield rate of each batch according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for controlling the update of the lower limit of the yield and the upper limit of the failure rate according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating PAT test specification definition;
FIG. 5 is a flowchart of a PAT test specification update control method disclosed in the embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a mass production testing system according to an embodiment of the present invention.
Detailed Description
For reference and clarity, the terms, abbreviations or abbreviations used hereinafter are summarized as follows:
SBL: statistical Bin Limit, counting the classified failure control lines;
SYL: statistical Yield control line;
PAT: part Average Test;
PPM: part per milliont;
and (3) CP: chip Probing, Chip probe testing;
YMS: yield Management System, Yield Management System.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the embodiment of the invention discloses a mass production testing method, which includes:
step S01: and acquiring actual measurement parameters of chips of the same model and different batches.
Step S02: and respectively carrying out joint clamping control on the failure rate and the yield of each batch based on the measured parameters.
Step S03: and carrying out PAT test on the problem batches screened by the combined card control.
Step S04: and outputting the test result of the current mass production according to the joint card control result and the PAT test result.
Specifically, the requirements for the quality and reliability of the vehicle-mounted electronic chip are very strict in the industry, and the current chip manufacturers generally adopt the dynamic PAT technology to perform mass production tests on the vehicle-mounted electronic chip. The dynamic PAT technology dynamically adjusts the PAT upper and lower limit specifications for each batch of chips, and the chips exceeding the PAT upper and lower limit specifications in each batch are regarded as failure products, and the rest are good products. The dynamic PAT test has the advantages that the test data quality is high, the quality and the reliability of a chip can be guaranteed to a great extent, the upper limit specification and the lower limit specification of the PAT are required to be adjusted frequently, the complexity of a test program is increased, and the test time is increased, so that the test method is only used for chips with high added values such as vehicle-mounted electronic chips and the like at present, and the test method is not popularized to chips with relatively low added values such as consumer electronic chips (such as audio power amplifier chips) and the like. Because the PPM requirement of the consumer electronic chip is not high compared with that of a vehicle-mounted electronic chip, if the testing method is directly applied to the consumer electronic chip, more yield loss and testing time can be caused.
To this end, the embodiment of the present invention performs a mass production test on each batch of chips by using a scheme combining the combined card control of failure rate and yield with the PAT technology, first, a problem batch is screened out by the combined card control of failure rate and yield (i.e., a batch intercepted by the combined card control of failure rate and yield, also called an outlier batch), the problem batch is not directly discarded as a failed product, but is further finely screened out by the PAT technology to screen out good products and failed products in the problem batch, and finally, the mass production test result is output according to the combined card control result and the PAT test result (for example, the failed products screened out by the combined card control of failure rate and yield and the failed products screened out by the PAT test are determined as all the failed products determined by the mass production test, and the rest are good products), and the mass production test result is presented in a form such as arranging the chips of the same batch into a CP map, but not limited to) to a seal plant. The scheme combining thickness screening and thickness screening is beneficial to saving the total testing time, can ensure the quality and reliability of the chip, can not cause meaningless yield loss of the chip, and is suitable for being popularized to chips with relatively low added values, such as consumer electronic chips.
Optionally, referring to fig. 2, the performing joint stuck control of failure rate and yield rate on each batch respectively includes:
respectively calculating the yield of each batch and the failure rate of each batch on the mth pre-specified test item; m is 1, 2, …, k is an integer greater than 0;
for each batch, when the yield of the batch does not exceed the preset lower yield limit and the failure rate of the batch on the mth pre-specified test item does not exceed the preset upper failure rate limit corresponding to the test item, judging the batch to be a normal batch; otherwise, the batch is determined to be a problem batch.
The joint stuck control of the failure rate and the yield rate is, for example, the joint stuck control of SBL and SYL. The following example takes the joint stuck control of SBL and SYL as an example to illustrate the joint stuck control of failure rate and yield: both SBL and SYL are control lines that trigger a response once exceeded in a normal production environment. Performing SBL and SYL combined card control on each batch of chips (SYL card control is specifically used for judging whether the yield of the chips in the same batch exceeds a preset yield lower limit, which is also called an SYL control line; SBL card control is specifically used for judging whether the failure rate of a certain test item of the chips in the same batch exceeds a preset failure rate upper limit corresponding to the test item, and the failure rate upper limit corresponding to the test item is also called an SBL control line corresponding to the test item), specifically: firstly, judging whether each chip of each batch is good, then calculating the yield of each batch of chips, and the failure rate of each batch of chips on the m (m is 1, 2, …, k is an integer greater than 0) pre-specified test items, and when the yield of a certain batch of chips does not exceed the SYL control line and the failure rate on the m pre-specified test item does not exceed the SBL control line corresponding to the test item, regarding the batch of chips as a normal batch (i.e. a batch which is not outlier); whereas, the lot of chips is suspected of being a lot with potential quality problems (i.e., considered as a problem lot, i.e., considered as an outlier lot), the present embodiment does not directly discard the problem lot as the failed product, but rather retains the failed product for further testing, also more rigorous testing, specifically PAT testing.
Wherein, one chip has n (n is more than or equal to 1) parameters, and all items related to the quality and the reliability of the chip are selected from the n (n is more than or equal to 1) parameters as test items. The determining whether each chip of each batch is good, and then calculating the yield of each batch of chips specifically includes: acquiring actual measurement parameters of all test items of each chip of each batch, and judging that the chip is a good product if all test items of the chip reach the standard aiming at each chip; if at least one test item of the chip does not reach the standard, the chip is judged to be a failure product; and respectively calculating the ratio of the number of the good chips of the batch to the total number of the chips of the batch to obtain the failure rate of the batch.
In fig. 2, the test items with the failure rate upper limits are pre-specified from the m test items according to the actual needs of the seal test factory, for example, two test items "open circuit or not" and "short circuit or not" may be specified to set the failure rate upper limits respectively. For example, if the lower limit of yield is set to 97%, the upper limit of failure rate corresponding to "open circuit or not" is set to 1%, and the upper limit of failure rate corresponding to "short circuit or not" is set to 1%, during actual testing, 100 batches of chips are assumed, each batch is 200, if the yield of a certain batch is 97%, the open circuit percentage is 1%, and the short circuit percentage is 1%, 6 failed products and 194 good products can be screened out from the batch through the combined control of failure rate and yield, and the batch is regarded as a normal batch; assuming that the yield of another lot is 97%, the open circuit percentage is 1% and the short circuit percentage is 2%, 6 failed products and 194 good products can be screened from the lot, and the lot is regarded as a problem lot and enters the PAT test. It should be noted that, when the PAT test is performed, all chips in the problem lot may be subjected to the PAT test, or good products in the problem lot screened by the joint card control of failure rate and yield may be subjected to the PAT test, and the failed products do not need to be subjected to the PAT test.
The setting process of the yield lower limit and the failure rate upper limit of the mth test item specifically comprises the following steps: selecting a certain amount of sample data, for example, selecting actual measurement data of each wafer in 8 wafer lots (200 wafers); then eliminating abnormal data generated due to test failure, and determining statistical average value μ of batch yield of the rest sample data by normal distribution 1 Sum variance σ 1 And determining the statistical average value mu of the batch failure rate of the rest sample data on the mth test item through normal distribution 2 Sum variance σ 2m (ii) a Variance σ 1 (Q3-Q1)/1.35 (Q1 is 25% quantile, Q3 is 75% quantile), variance σ 2m (Q3-Q1)/1.35; finally, determining the lower limit of the yield as mu 1 –3σ 1 Determining the failure rate upper limit of the mth test item as mu 2 +3σ 2m 。
Optionally, the lower limit of the yield and the upper limit of the failure rate are determined again every preset time or after a preset number of chips are tested, and which condition is reached first. The update control method is specifically shown in fig. 3, and includes:
step S11: judging whether the predetermined update time (for example, half a year) of the yield lower limit and the failure rate upper limit is reached, if not, entering step S12; if yes, go to step S13;
step S12: judging whether the number of chips tested at present from the last time of updating the lower limit of the yield and the upper limit of the failure rate reaches a first preset number (for example 1000), if so, entering a step S13, and if not, returning to the step S11;
step S13: and calculating the lower yield limit and the upper failure rate limit again and updating.
It should be noted that fig. 3 and fig. 1 may be two independent threads. And the execution order of step S11 and step S12 can be interchanged, fig. 3 is only an example and is not limited.
The PAT test in the embodiment of the invention can be a dynamic PAT test or a static PAT test. The PAT test specification includes an Upper Specification Limit (USL) and a Lower Specification Limit (LSL), and any value that exceeds the LSL and USL limits is considered an outlier, as shown in FIG. 4. The static PAT test specification calculation method specifically comprises the following steps: all good products obtained from the previous batch production test are taken as samples, and then the mean value mu of the samples on each test item is determined through normal distribution 3 Sum variance σ 3 . Variance σ 3 (Q3-Q1)/1.35 (Q1 is 25% quantile, Q3 is 75% quantile), USL ═ μ was determined 3 +6σ 3 ，LSL＝μ 3 -6σ 3 . The calculation method of the static PAT test specification is the same as that of the dynamic PAT test specification.
PAT test Specification the two dashed lines in FIG. 4 represent the recalculated LSL and USL limits, and both dynamic PAT tests and static PAT tests require periodic (or based on the number of chips tested) recalculation of the PAT test specification to replace the previous LSL and USL limits, with the main difference being that the dynamic PAT test specification is calculated at a high frequency and the static PAT test specification is calculated at a relatively low frequency. The PAT test specification calculation method is specifically shown in fig. 5, and includes:
step S21: judging whether the preset updating time (for example, half a year) of the PAT test specification is reached, if not, entering the step S22; if yes, go to step S23;
step S22: judging whether the number of chips tested from the last time of updating the PAT test specification to the current time reaches a second preset number (for example, 200 chips), if so, entering step S23, otherwise, returning to step S21;
step S23: and calculating and updating the PAT test specification again.
It should be noted that fig. 5 and fig. 1 may be two independent threads. And the execution order of step S21 and step S22 can be interchanged, fig. 5 is only an example and is not limited.
The embodiment of the invention is suitable for processing and judging mass production test data, and is realized by means of a YMS tool. The YMS system which is mainstream in the industry such as PDF-exensio yield, JMP, Tango and the like can be realized. When static PAT test is selected for PAT test, the test data quality is high, the yield loss is low, the test time is short, and the test program has strong portability and is suitable for processing off-line processing. At the moment, the embodiment of the invention starts from uploading off-line data (the off-line data is the actual measurement data of chips with the same model and different batches to a remote server, and the actual measurement data is automatically downloaded from the remote server through network communication, is not the data on a production machine, and the advantage of obtaining the off-line data is that the off-line data is not subjected to an interruption test).
Corresponding to the above method embodiment, the embodiment of the present invention further discloses a mass production testing system, as shown in fig. 6, which includes a processor and a memory, wherein the following acquiring unit 1 and the template processing unit 2 are both stored in the memory as program units, and the processor executes the program units stored in the memory to implement corresponding functions;
the obtaining unit 1 is configured to obtain actual measurement parameters of chips of the same model and different batches.
The processing unit 2 is used for respectively carrying out joint clamping control on failure rate and yield of each batch based on the measured parameters; carrying out component average test on the problem batches screened by the joint control; and outputting the test result of the current batch production according to the joint clamping control result and the average test result of the components.
In addition, an embodiment of the present invention further provides a storage medium, on which a program is stored, and the program, when executed by a processor, implements any one of the mass production testing methods as disclosed above.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The mass production test system and the storage medium disclosed in the embodiments correspond to the method disclosed in the embodiments, so the description is simple, and the relevant points can be referred to the description of the method.
The terms "first," "second," and the like in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, identical element in a process, method, article, or apparatus that comprises the element.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for mass production testing, comprising:
acquiring actual measurement parameters of chips of the same type and different batches;
respectively carrying out combined clamping control on failure rate and yield of each batch based on the measured parameters;
carrying out component average test on the problem batches screened by the joint control;
and outputting the test result of the current batch production according to the joint clamping control result and the average test result of the components.
2. The mass production test method according to claim 1, wherein the performing the component average test on the problem lot screened by the joint card control comprises: and carrying out component average test on good products in the problem batches screened by the joint clamping control.
3. The mass production test method according to claim 1 or 2, wherein the outputting the mass production test result according to the joint clamping result and the component average test result comprises:
and marking the failed products screened by the combined clamping control and the failed products screened by the component average test as all the failed products determined by the mass production test, and obtaining the rest products.
4. The mass production testing method according to claim 1 or 2, wherein the joint control of the failure rate and the yield rate for each lot comprises:
respectively calculating the yield of each batch and the failure rate of each batch on the mth pre-specified test item; m is 1, 2, …, k is an integer greater than 0;
for each batch, when the yield of the batch does not exceed the preset lower yield limit and the failure rate of the batch on the mth pre-specified test item does not exceed the preset upper failure rate limit corresponding to the test item, judging the batch to be a normal batch; otherwise, the batch is determined to be a problem batch.
5. The mass production test method according to claim 4, further comprising, during execution of the mass production test method:
judging whether the preset updating time of the lower yield limit and the upper failure rate limit is reached, judging whether the number of chips tested at present from the last updating of the lower yield limit and the upper failure rate limit reaches a first preset number, and updating the lower yield limit and the upper failure rate limit when at least one of the preset updating time and the first preset number is reached.
6. The mass production test method according to claim 1, wherein the part average test determines chips that do not exceed the upper and lower specification limits as good chips, and the rest are defective chips.
7. The mass production test method according to claim 6, further comprising, during execution of the mass production test method:
judging whether the preset updating time of the upper specification limit and the lower specification limit is reached, judging whether the number of chips tested at present from the last calculation of the upper specification limit and the lower specification limit reaches a second preset number, and updating the upper specification limit and the lower specification limit when at least one of the regular updating time and the second preset number is reached.
8. The mass production test method according to claim 6, wherein the component averaging test includes: a dynamic component averaging test or a static component averaging test; the dynamic component averaging test has a higher frequency of updating the specification upper limit and the specification lower limit than the static component averaging test.
9. A mass production test system, comprising:
the acquisition unit is used for acquiring the actual measurement parameters of chips of the same model and different batches;
the processing unit is used for respectively carrying out joint clamping control on failure rate and yield of each batch based on the measured parameters; carrying out component average test on the problem batches screened by the joint control; and outputting the test result of the current batch production according to the joint clamping control result and the average test result of the components.
10. A storage medium having a program stored thereon, the program when executed by a processor implementing the mass production testing method according to any one of claims 1 to 7.
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