TWM599460U - Memory operating condition checking device - Google Patents

Abstract

A device for checking operating conditions of a memory includes several memory modules to be tested, a power management chip, several measurement units and a central processing unit. The central processing unit on the motherboard of this creation can provide more precise adjustments to the voltage measurement values returned by the measurement unit set at the input voltage (VDD, VDDQ, and VPP) supply terminals of each memory module under test. The correct supply voltage of the memory module under test , So that the central processing unit can play the highest efficiency, by using the three operating voltages of VDD, VDDQ and VPP to solve the problem of the deviation of the memory power supply voltage, so that the input to each memory model under test can be accurately adjusted during the mass production test The correct supply voltage of the group terminal to achieve consistent calibration.

Description

Memory operating condition checking device

This creation is related to a device for checking the operating conditions of the memory, especially a The three operating voltages of VDD, VDDQ and VPP solve the problem of memory power supply voltage deviation, which can more accurately adjust the correct supply voltage to each memory module under test, so that the central processing unit can exert the highest efficiency, especially During the mass production test, the correct supply voltage input to each memory module under test can be accurately adjusted to achieve a consistent calibration.

Such as a dynamic random access memory (dynamic random access memory, DRAM) is a semiconductor device in which the memory die can be mounted on a motherboard and receive a power supply from a central processing unit (CPU), which can transmit the externally supplied power to a power source The power management circuit (PMC) manages the power supplied to the components of the memory system. Power can be supplied to different components at different voltages and with different current needs. Among them, the power supply terminals VDD and VDDQ on the motherboard are usually the same value (1.2 V), and in general use, VDDQ and VDD are combined into one power supply.

However, due to the influence from program changes, end load voltage, etc., the power supply The voltage may deviate from the value set by the pulse width modulation (PWM) unit in the power management circuit.

In view of the fact that the electric power output from the host side reaches to the memory side to receive This section of the path will produce an unavoidable voltage deviation, so that the value that actually reaches the memory terminal cannot be changed. It is known that the prior art does not measure this. Even if the PWM itself generates a feedback voltage, it can only know the set value just output, but the value when the memory is received at the end has been affected. The time has been deviated by the load voltage at the end, so the power consumption of each memory itself cannot be accurately known.

Therefore, for the conventional skills, the output from the power management circuit to the memory input The voltage value of the terminal is measured to compensate for the lack of power supply voltage deviation. Therefore, the general user is unable to accurately adjust the correct voltage value input to each memory terminal during actual use to achieve a consistent calibration. need.

The main purpose of this creation is to overcome the above-mentioned problems encountered by learning skills and Provide a more accurate adjustment to provide the correct supply voltage for each memory module under test, so that the central processing unit can exert the highest efficiency, and solve the problem of memory power supply voltage deviation with three operating voltages of VDD, VDDQ and VPP, thereby During the mass production test, the correct supply voltage input to each memory module under test can be accurately adjusted to achieve a consistent calibration memory operating condition checking device.

Another purpose of this creation is to provide a reference that can accurately monitor operations Voltage (VREF) and other parameters, by quickly changing the operating conditions, can quickly change the basic input and output system (Basic Input and Output System, BIOS) frequency and delay time (CAS latency, CL) settings, so as to effectively perform under various conditions The operating ability test of the memory operating condition checking device.

In order to achieve the above purpose, this creation is a memory operating condition checking device, which is Including: several memory modules under test (device under test, DUT), which are installed on a motherboard, Each memory module under test includes a first input voltage (VDD) supply terminal, a second input voltage (VDDQ) supply terminal, and a third input voltage (VPP) supply terminal; a power management chip (power management) integrated circuit, PMIC), which is connected to each memory module under test, and provides a number of original supply voltages to the first to third input voltage supply terminals of each memory module under test, each of the original supply voltages Including VDD, VDDQ, and VPP; several measurement units, each measurement unit includes a first measurement element coupled to the first input voltage supply terminal, a first measurement element coupled to the second input voltage supply terminal Two measuring elements and a third measuring element coupled to the third input voltage supply terminal for measuring the input voltage and current of the first to third input voltage supply terminals of each memory module under test , To generate the corresponding current supply voltage; and a central processing unit (CPU), which is connected to each of the memory modules under test, the power management chip, and each of the measurement units, and has a built-in The storage component (register) can manage the power management chip through software to control the original supply voltage provided to each memory module under test, and according to the current supply voltage fed back by each measurement unit and each original supply The voltage comparison result generates a corresponding compensation voltage. The central processing unit manages the power management chip through the storage element for the memory module under test related to the compensation voltage to provide the compensation voltage to the corresponding test The memory module performs compensation, so that the correct supply voltage input to each end of the memory module under test can be accurately adjusted.

In the above-mentioned embodiment of this creation, each of the measurement units is a digital multimeter (digital multimeter). multimeter, DMM).

In the above-mentioned embodiment of this creation, the first to third measuring elements are respectively applied with an electric The resistance measurement corresponds to the input voltage and current of the first to third input voltage supply terminals coupled to it, and generates the corresponding current supply voltage according to the change of the intermediate bias voltage of the resistance value.

In the foregoing embodiment of the present creation, the resistance value is 8-12 milliohms (mΩ).

Please refer to "Picture 1", which is a block diagram of this creation. as the picture shows: This creation is a memory operating condition checking device, which includes several memory modules under test (device under test, DUT)1, a power management integrated circuit (PMIC)2, and several measurement units3 And a central processing unit (central processing unit, CPU) 4 constituted.

The several memory modules 1 under test mentioned above are installed on a motherboard, each The memory module 1 under test includes a first input voltage (VDD) supply terminal 11, a second input voltage (VDDQ) supply terminal 12, and a third input voltage (VPP) supply terminal 13.

The power management chip 2 is connected to each of the memory modules 1 under test, which provides a The original supply voltage is supplied to the first to third input voltage supply terminals 11-13 of each of the memory modules 1 under test, and the original supply voltage includes VDD, VDDQ, and VPP.

Each measurement unit 3 includes a device coupled to the first input voltage supply terminal 11 A first measuring element 31, a second measuring element 32 coupled to the second input voltage supply terminal 12, and a third measuring element 33 coupled to the third input voltage supply terminal 13, with To measure the input voltage and current of each of the first to third input voltage supply terminals 11-13 of the memory module 1 to be tested to generate the corresponding current supply voltage.

The central processing unit 4 is connected to each of the memory module 1 and the power tube The management chip 2 is connected to the measurement unit 3, which has a built-in storage element (register) 41, which can be accessed through The power management chip 2 controls the original supply voltage provided to each memory module 1 to be tested in a software way, and generates a comparison result based on the current supply voltage fed back by the measurement unit 3 and the original supply voltage Corresponding to the compensation voltage, the central processing unit 4 manages the power management chip 2 through the storage element 41 for the memory module 1 to be tested related to the compensation voltage and provides the compensation voltage to the corresponding memory module to be tested. Group 1 performs compensation, so that the correct supply voltage input to each end of the memory module under test can be adjusted accurately. If so, a brand-new memory operating condition checking device is constructed by the above disclosed device.

When used, this creation is designed to more accurately measure the consumption of each memory module 1 under test. The power is to separate the operating voltages VDD and VDDQ, which are usually combined on traditional motherboards, according to the three separate first to third input voltage supply terminals 11 of VDD, VDDQ, and VPP of each memory module 1 under test. ~13 to measure its input voltage and current. In a preferred embodiment, the authoring system is provided with several measurement units 3, such as a digital multimeter (DMM). Each of the measurement units 3 is correspondingly coupled to the first to the third input voltage supply terminals 11-13 of the memory module 1 under test from the first to the third input voltage supply terminals 11-13 on the motherboard. The three measuring components 31 to 33 measure the input voltage and current supplied to the first to third input voltage supply terminals 11 to 13 of the memory module 1 under test at the end to generate the corresponding current supply voltage. In this embodiment, although a digital multimeter is used as the measurement unit 3, it is described. However, the 3 types of measurement units mentioned above are only examples of current mainstream components for current measurement, and other components with the same or similar functions that are not specified should also be considered as covered by this creation.

The above-mentioned measuring unit 3 is based on the first to third measuring elements 31 to 33 respectively Apply a resistance value of 8-12 milliohms (mΩ) to measure the input voltage and current of the first to third input voltage supply terminals 11-13 that are coupled to each other, and generate the corresponding current according to the change in the intermediate bias voltage of the resistance value Supply voltage, each of the measurement units 3 sends the measured current supply voltage back to the central processing unit 4. The central processing unit 4 supplies the power management chip 2 to each memory module under test according to the previous setting 1 original supply voltage (for example: 1.2 V), compare the current supply voltage (for example: 1.19 V) of each memory module 1 under test returned from each measurement unit 3, and know the supply voltage from the After the voltage deviation value (ΔV=1.2-1.19=0.01) between the output terminal of the power management chip 2 and the input terminal of the memory module 1 under test, a corresponding compensation voltage (for example: 0.01) is generated. V). The central processing unit 4 then controls the power management chip 2 through the storage element 41 to compensate the memory module 1 to be tested related to the compensation voltage, and adjust it according to the voltage required to increase or decrease. The traditional method does not have this technology. The motherboard of the present invention can more accurately adjust the correct supply voltage provided to each memory module 1 under test through the feedback of the above-mentioned measured values, so that the central processing unit 4 can perform the highest Efficiency, using these three operating voltages VDD, VDDQ and VPP to solve the problem of memory power supply voltage deviation, so that during mass production testing, the correct supply voltage input to each memory module under test can be accurately adjusted , In order to achieve consistent correction.

In this way, this creation can accurately monitor the reference voltage (VREF) in operation and other Parameters, by quickly changing operating conditions, can quickly change the basic input and output system (Basic Input and Output System, BIOS) frequency and delay time (CAS latency, CL) settings, so as to effectively perform operational capability tests under various conditions.

In summary, this creation is a memory operating condition checking device that can effectively change Taking advantage of various shortcomings, the central processing unit on the motherboard can adjust the voltage measurement value returned by the measurement unit on the input voltage (VDD, VDDQ, and VPP) supply terminals of each memory module under test, which can be more accurately adjusted Provide the correct supply voltage for each memory module to be tested, so that the central processing unit can exert the highest efficiency. With the three operating voltages of VDD, VDDQ and VPP, the problem of memory power supply voltage deviation can be solved, so that it can be tested in mass production , Can accurately adjust the correct supply voltage input to the end of each memory module under test to achieve consistent calibration, so that the creation of this creation can be more advanced, more practical, and more in line with the needs of users. It has met the requirements for a new patent application, and Yan has filed a patent application in accordance with the law.

However, the above are only the preferred embodiments of this creation, and should not be limited to this The scope of implementation of this creation is determined; therefore, everything made in accordance with the scope of the patent application for this creation and the content of the new specification The simple equivalent changes and modifications should still fall within the scope of this creation patent.

1: Memory module to be tested １１: The first input voltage supply terminal 12: The second input voltage supply terminal 13: The third input voltage supply terminal 2: Power management chip 3: Measuring unit 31: The first measuring component 32: The second measuring element 33: The third measuring element 4: Central Processing Unit 41: Storage element

Figure 1 is a block diagram of this creation.

1: Memory module to be tested

11: The first input voltage supply terminal

12: The second input voltage supply terminal

13: The third input voltage supply terminal

2: Power management chip

3: Measuring unit

31: The first measuring component

32: The second measuring element

33: The third measuring element

4: Central processing unit

41: storage components

Claims (4)

A device for checking operating conditions of memory, including: Several memory modules under test (device under test, DUT) are installed on a motherboard. Each memory module under test includes a first input voltage (VDD) supply terminal and a second input voltage ( VDDQ) supply terminal, and a third input voltage (VPP) supply terminal; A power management integrated circuit (PMIC) is connected to each of the memory modules to be tested, and provides a number of original supply voltages to the first to third input voltage supplies of the memory modules to be tested Terminal, each of the original supply voltages includes VDD, VDDQ and VPP; A plurality of measurement units, each measurement unit includes a first measurement element coupled to the first input voltage supply terminal, a second measurement element coupled to the second input voltage supply terminal, and a coupling A third measurement element connected to the third input voltage supply terminal for measuring the input voltage and current of the first to third input voltage supply terminals of each memory module under test to generate the corresponding current supply Voltage; and A central processing unit (CPU) is connected to each of the memory modules to be tested, the power management chip, and each of the measurement units. It has a built-in storage component (register) that can be accessed through software Way to manage the power management chip to control the original supply voltage provided to each memory module under test, and generate the corresponding compensation voltage according to the current supply voltage fed back by the measurement unit and the comparison result of each of the original supply voltages For the memory module under test related to the compensation voltage, the central processing unit manages the power management chip through the storage element to control the supply of the compensation voltage to the corresponding memory module under test for compensation, so as to accurately Adjust the correct supply voltage input to each end of the memory module under test. According to the memory operating condition inspection device described in item 1 of the scope of patent application, each of the measurement units is a digital multimeter (DMM). According to the device for checking the operating conditions of the memory as described in the scope of patent application, wherein the first to third measuring elements respectively apply a resistance value to measure the input voltage corresponding to the coupled first to third input voltage supply terminals And the current, according to the change of the intermediate bias voltage of the resistance value to generate the corresponding current supply voltage. According to the memory operating condition inspection device described in item 3 of the scope of patent application, the resistance value is 8-12 milliohms (mΩ).

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