TWI298922B - Predictive, adaptive power supply for an integrated circuit under test - Google Patents

Description

1298922 (1) IX. Description of the invention [Technical field to which the invention pertains] The use of a crystal card 1C for each of the pins 12 is a source of the device 14 and, in general, the invention relates to testing an integrated circuit, and in particular to reducing the integrated body A device that causes source noise of a logic state transition in its circuit test. [Prior Art]

The integrated circuit (1C) tester can simultaneously test a set of ICs in a granular form on a semiconductor wafer. 1 is a block diagram depicting a typical 1C tester 10 connected to a set of identical test devices (DUTs) 14 that can be formed on a semiconductor wafer via a probe 12, the tester 10 utilizing a spring pin 1 5 or other devices connect different input and output terminals to a set of contacts 16 on the probe card 12. The probe card 12 includes a set of probes 1 8 for contacting the input/output (I/O) pads 19 on the surface of the DUT 14 and for connecting the contacts 16 to the conductive path 20 of the probes 18. The path through the probe card allows the tester 1 to transmit test signals to the DUT 14 and monitor the output signals produced by the DUT 14. Since the digital integrated circuit often includes a clock in response to the synchronous logic gate of the periodic main clock signal (CLOCK), the probe card 12 also provides a path 22 through which the tester 10 supplies a CLOCK signal to each DUT 14 . The test system also includes an electrical supply 24 for supplying power to the DUTs 14 when tested, and the probe card 12 is coupled to the power supply pads 24 of the respective DUTs via the probes 18. Each switching transistor in the DUT 14 has an inherent input capacitance, (2) 1298922. To turn the transistor on or off, the driver of the transistor must charge or discharge the input capacitance of the transistor. When the driver charges the input capacitance of the transistor, it will obtain a charging current from the power supply 24. Once the input capacitance of the transistor is fully charged, its driver only needs to supply a relatively small amount of leakage current required to maintain the input capacitance of the transistor, so that the transistor remains on or off. In DUTs that implement synchronous logic, most of the transistors' switches will immediately occur after the edge of each CLOCK signal pulse, so immediately after the CLOCK signal of each pulse, the power supply current is input to each DUT 14. There is a temporary increase in 1 1 , which provides the charging current required to change the state of the different transistor switches in the DUT, and then in the CLOCK signal cycle, after the transistors have changed state, the demand for current 1 1 is supplied. It will become a steady state level of &gt; static 且 and remain there until the next CLOCK signal cycle begins. Through this, the probe card 12 can be connected to the power supply 24 and the signal path 28 of each DUT 14 has the inherent impedance represented by the resistor R1 in FIG. Because there is a voltage drop between the output of the power supply 24 and the power input 26 of the DUT 14, the supply voltage input VB of the DUT 14 is somewhat less than the output voltage VA of the power supply 24, and although the VA can be better adjusted However, VB will vary with the magnitude of current 11. After each CLOCK signal cycle is initiated, a temporary increase in 11 required for the input capacitance of the charge switch transistor increases the voltage drop across R1, thus temporarily reducing VB. Since the tilt in the supply voltage VB occurring after the edge of the pulse wave of each CLOCK signal is a noise pattern which can adversely affect the performance of the DUTs 14 (3) 1298922, it is expected to limit its size and period. The noise can be limited by reducing the reactance of the paths 28 between the power supply 24 and the DUTs 14, for example by increasing the conductor size or by minimizing the length of the path 28. However, by virtue of this, we will have practical restrictions on reducing the number of reactances. We can also reduce the power supply noise by placing capacitor C1 on the probe card 12 near the power input 26 of each DUT 14. Figure 2 depicts the behavior of supply voltage VB and current II at power input 26 of IC 14 in response to a CLOCK signal pulse input to 1C 14 when capacitor C1 is not very large. It should be noted that after the edge of the CLOCK signal at time T1, the temporary rise above II in its static level IQ will result in a temporary increase in the voltage drop across R1, which will be sequentially in the supply voltage VC. Produces a temporary tilt below its static level VQ. Figure 3 depicts the behavior of VB and II when capacitor C1 is very large. Between the CLOCK signal pulses, when the DUT 14 is static, the capacitor C1 is charged to the static level of VB. After the rising edge (or falling edge) of the CLOCK signal at time T1, when the DUT 14 temporarily needs more current, the capacitor C1 supplies some of its stored charge to the DUT 14, thus reducing the amount of extra current, so The power supply 24 must be provided to match the increased demand. For example, it can be seen in Fig. 3 that the presence of capacitor C1 reduces the magnitude of the temporary voltage drop of R1 and thus reduces the magnitude of the tilt in the supply voltage VB input to DUT 14. For capacitors that limit variation in VB, the capacitor must be large enough to supply the required charge to DUT 14 and must be positioned close to DUT 14 such that the path impedance between C1 and DUT 14 is extremely low. (4) 1298922 Unfortunately, it is not always convenient or feasible to install large capacitors on the probe card 12 near the power input 26 of each DUT 14. Figure 4 is a simplified plan view of a typical probe card 12 with the 1C tester 1 located above the probe card and the wafer containing the DUTs 14 held under the probe card. Since the I/O terminals of the 1C tester 10 of FIG. 1 are distributed over a relatively large area compared to the surface area of the wafer under test, the probe card 12 provides a relatively large upper surface 25 for Keep the contact point of the tester access to 16. In addition, on the one hand, the probes 18 (not shown) on the lower surface of the probe card 12 of the DUTs 14 on the contact wafer are concentrated below the relatively small central region 27 of the probe card 12. The path impedance between the contacts on the upper surface 25 of the probe card 12 and the probes 18 below the region 27 is a function of the distance between the contacts 16 and their corresponding probes. In order to minimize the distance between the capacitor C1 and the DUTs, the capacitors should be mounted on the probe card 12 near (or above) the small central region 27. However, when the wafer contains a large number of ICs to be tested or 1C with a large number of densely packed terminals, there is not enough space to install a required number of capacitors C1 of sufficient size sufficiently close to the central region 27. SUMMARY OF THE INVENTION During testing of an integrated circuit device (DUT) in a test using synchronous logic, the DUT experiences a temporary power supply after each successive leading or trailing edge of the clock signal input to the DUT The need for increased current, when the transistor forming the logic device experiences a state transition in response to the edge of the clock signal, the DUT may require additional current to charge the input capacitance of the isoelectric (5) 1298922 crystal. The present invention limits the variation in the power supply voltage of the DUT power input caused by the transient increase in the power supply current after the pulse signal of each clock signal, so the present invention can reduce the power supply noise of the power input of the DUT. . According to the invention, the charging current pulse wave is supplied to the power input of the DUT after the edge of each clock signal, and during the test period, the current supplied by the main power supply is supplemented, and the charging is appropriately supplied by the auxiliary power supply. Current pulses reduce the need for the main power supply to increase its output current to match the increased demand of DUTs. Despite the increased current demand of the DUT, with the output current of the main power supply that remains substantially constant, the voltage drop across the path impedance between the main power supply and the DUT will remain substantially constant, so in the DUT The supply voltage at the power input will also remain substantially constant. After each clock signal edge, the amount of additional charge current required by the DUT will vary in response to the edge of the clock signal depending on the number and nature of state transitions experienced by its internal logic device. Since the 1C test requires 1C to perform a predetermined sequence of state changes, the 1C behavior during the test, including its demand for current during the edge of each clock signal, is predictable. Therefore, the magnitude of the current pulse wave supplied after the edge of each clock signal can be adjusted to suit the predicted amount of additional charging current required by the DUT after each pulse signal pulse, and for each clock signal edge followed by the DUT The prediction of the increase in the resulting current may be subject to similar tests, for example, by the measurement of the current caused by the same DUT under the same test conditions, or by analog DUT. -8 - (6) 1298922 Although the amount of charge current that can be induced by a particular form 1C can be predicted with relatively high accuracy at any test cycle, the actual amount of additional charge current caused by a given DUT of any such form is More or less will be higher or lower than the predicted amount. In particular, variations in the random process in the manufacture of ICs relative to the amount of charge current required during the state change of the transistors will cause all ICs to behave slightly differently. To compensate for these differences between DUTs, a feedback circuit can be configured to monitor the voltage at the power supply of the DUT and properly meter the predicted current pulse size to minimize variations in the voltage. Thus, the magnitude of the current pulse supplied to the power supply input of the DUT after each clock signal cycle is a function of the predicted magnitude of the additional current caused by the DUT of the form during the clock signal cycle, but the predicted pulse The wave size is measured by the feedback so that the prediction can be adapted to adjust for changes in the charging current requirements of each particular DUT being tested. The conclusions of this specification particularly point out and explicitly claim the subject matter of the present invention. However, those skilled in the art will be able to better understand the organization and method of operation of the present invention and the further embodiments of the present invention. The advantages and objectives. [Embodiment] &lt;System Architecture&gt; Fig. 5 depicts, in block diagram form, a through probe card 32 coupled to a set of identically tested 1C mounted S (-9 - (7) 1298922 DUTs on a semiconductor wafer in the form of a die. 34 integrated circuit (IC) tester 30. The probe card 32 includes a set of probes 37 for accessing the input/output terminal pads 39 on the surface of the DUTs 34; and also includes a signal path 46 that couples the tester 30 to the probes 3 7 to allow the 1C tester 30 transmits a clock signal (CLOCK) and other test signals to the DUTs 34, and passes the DUT output signals back to the tester to enable the tester to monitor the behavior of the DUTs. The probe card 32 also connects the main power supply to the power input 41 of each DUT 34 via a conductor that is routed through the probe card to the probe 37 and extends to the terminal 41. The power supply 36 produces a good The adjusted output voltage VA and continuously supplies current 12 to the DUT 34. For purposes of depiction, Figure 5 shows the inherent impedance of the path 43 through the probe card 32 between the main power supply 36 and each DUT as resistor R1. Due to the voltage drop across resistor R1, the supply voltage VB of each DUT 34 input is always slightly less than VA. According to the present invention, the first transistor switch SW1 mounted on the probe card 32 is coupled to an auxiliary power supply 38 to a set of capacitors C2 mounted in the probe card 32; the group is also mounted to the probe card 3 2 The second transistor switch SW2 connects the capacitors C2 to the power input terminals of the corresponding DUTs 34. The resistor R2 shown in Fig. 5 represents the inherent signal path impedance in the probe card 32 between the capacitor C1 and the power input terminal 41 of the DUT 34 when the switch SW2 is turned off. The 1C tester 30 provides an output control signal CN1 for SW 1, a control signal CNT2 for controlling the switch SW2, and CNT3 for controlling the output voltage VC of the auxiliary power supply 38. As described in more detail below, the auxiliary power supply 38, -10- (8) 1298922 switches SW1 and SW2, and capacitor C2 act as an auxiliary current source when any desired increase in the required supply current to the DUT is required' That is, the current pulse 13 is injected into the power input terminal 41 of each DUT under the control of the 1C tester 30. &lt;Power Supply Noise&gt; The DUTs 34 implement synchronization logic in which the switching transistor forming the logic gate is turned on and off in response to the pulse of the periodic main CLOCK signal provided by the tester 30, each switching transistor having The inherent input capacitance, and in order to turn the transistor on or off, its driver must charge or discharge the input capacitance of the transistor. When the driver in the DUTs 34 charges the input capacitance of the transistor, it will increase the power that must be supplied to each DUT. The amount of current 11 at input terminal 41. When the input capacitance of the transistor is full of charge, its driver only needs to supply a relatively small amount of leakage current required to maintain the input capacitance of the transistor, so that the transistor remains on or off. Therefore, after each pulse of the CLOCK signal, there is a temporary increase in the power supply current 11 input to each of the DUTs 34, and a charging current required to change the switching states of the different transistors is provided. Later in the CLOCK signal cycle, after the transistors have changed state, the power supply current demand will produce a ''static' steady state level and remain there until the start of the next CLOCK signal cycle. Since the amount of additional current II required by the DUT 34 at the beginning of each CLOCK signal cycle will vary depending on the number and nature of the transistors that are turned on or off during the cycle of the particular CLOCK signal, the charge current requirement can be -11 - (9) 1298922 changes between cycles. If tester 30 - keeps switches SW1 and SW2 open, then main power supply 36 will always provide all current inputs to each DUT 34 . In this example, the increase in the temporary characteristic in the supply current 11 will cause the inherent impedance of the signal path 43 between the main power supply 36 and the DUT 34 due to the increased switching action in each DUT 34 after the pulse of each CLOCK signal. A temporary increase in voltage drop across R1, which in turn will cause a temporary tilt in voltage VB at power input terminal 4 of the DUT, and Figure 2 represents the behavior of VB and II when SW2 is on. Since the tilt in the supply voltage VB occurring after the edge of the pulse of each CLOCK signal can adversely affect the noise form of the DUTs 34 performance, it is desirable to limit the magnitude of the voltage tilt. &lt;Predictive Current Compensation&gt; According to an embodiment of the present invention, the 1C tester 30 controls the states of the auxiliary power supply 38 and the switches SW1 and SW2 so that the capacitor C2 can supply additional charging at the beginning of each test cycle. Current 13 to DUT 34. The charging current 13 flowing only during the initial portion of each CLOCK signal cycle combines the current 12 of the main power supply to provide current input II to DUT 34. When the charging current 13 provides approximately the same amount of charge as the capacitance of the switching transistor in the DUT 34 after the CLOCK signal pulse, there is only a relatively small change in the main power supply 3 after the CLOCK signal pulse. 6 of the generated current 12, and thus there is only a small change in the supply voltage VB. -12- (10) 1298922 Therefore, before the edge of each CLOCK signal, the tester 30 supplies the data CNT3 to the auxiliary power supply 38 to indicate the magnitude of the desired auxiliary supply voltage VC and then turns off the switch SW1. Next, the power supply 38 charges all of the capacitors C2, and the amount of charge stored by the capacitor C2 is proportional to the size of the VC. When the capacitor C2 has time full charge, the tester 30 turns on the switch SW1; after that, after the start of the next CLOCK signal cycle, the tester 30 turns off all the switches SW2, so that the charge stored in the capacitor C2 can be regarded as flowing into the DUTs. Current 13 in 34; Next, when it is deemed that a transient charging current is required, tester 30 will turn on switch SW2 such that only main power supply 36 supplies current to DUTs 34 during the remainder of the CLOCK signal cycle. This process will be repeated to the tester 30 during each cycle of the CLOCK signal, and the size of the VC is adjusted via the control data CNT3 for each clock cycle to provide a certain magnitude of current pulse 1C to satisfy the particular clock signal. The demand for the charge current predicted during the cycle. Therefore, the magnitude of the 1C current pulse can vary between cycles. Figure 6 depicts the behavior of supply voltage VB and currents II, 12 and 13 during the initial portion of the CLOCK signal cycle. Current II shows a large temporary increase above its static level IQ1 at time T1 after the CLOCK pulse edge to charge the capacitance within DUT 34. Current 13 rises rapidly to substantially provide all of the additional charging current. The output current 12 of the main power supply 38 shows only a relatively small disturbance to its static 値IQ2, resulting in a small mismatch between the transient components of 13 and 12. Since the change in 12 is small, the change in VB is also small. Therefore, the present invention can substantially limit power supply noise due to the switching transients in -13-(11) 1298922 DU Ts 34. &lt;Programming Program Program&gt; As described above, the amount of additional charging current generated by each DUT 34 at the beginning of the CLOCK signal cycle depends on the number of transistors turned on or off during the CLOCK signal cycle, and is charged. The current will vary between cycles. To provide the appropriate voltage adjustment to the DUT terminal 41, the tester 30 must predict how much charge the DUT 34 will store after each CLOCK signal edge because the tester must adjust the size of the auxiliary power supply output VC such that the capacitor C2 is Store the appropriate amount of charge before the CLOCK signal cycles. Figure 7 depicts a test system established to allow the tester 30 to experimentally determine the VC level it should set during each test cycle. A well-known reference DUT 40 that is suitable for operation and similar to the ICs to be tested is connected to the tester 3 via probe 32 in a manner substantially similar to that of the DUTs 34, such that the tester 30 can perform the same test with reference to 1C40. Above, the probe card 32 also connects the power supply terminal of the reference IC 40 to the input terminal of the tester 3, so that the tester 30 can monitor the power supply voltage VB. The tester 30 then observes VB using only the minimum C of the VC to perform the first CLOCK cycle of the test. If VB falls below the lower expected limit during the CLOCK signal cycle, the tester 30 repeats the higher of the VC. The first CLOCK signal loop is tested and this process will repeat until the appropriate vc of the vc of the first CLOCK signal loop is established. Then 14-(12) 1298922, the tester repeatedly performs the first two CLOCK signal cycles of the test and monitors the VB during the second CLOCK signal cycle and adjusts the VC accordingly, using the same procedure to establish the test. The VC of the successive CL CK CK signal loop is appropriate, and the VC 可 can be used when testing the DUTs 34. Typically, before the ICs are manufactured, the designer will use a circuit simulator to simulate the ICs. When the circuit simulator performs the same test that the 1C tester will perform on its real counterparts on the analog ICs, the circuit simulator can Used in a similar manner to determine the VC値 sequence to be used during the test of the real 1C. &lt;Probe Card&gt; Figure 4 depicts a typical prior art probe card 12 that is connected to the power input of the DUTs of the voltage regulating capacitor C1 to limit the power supply to the 'this temple probe card The distance between the voltage regulating capacitor and the DUT must be minimized to minimize the impedance between the capacitors and the DUTs. Accordingly, the capacitors are preferably mounted in the probe card or near a small area 27 above the probes that access the DUTs. Since there is only a small space on the probe card close to the probe, the size and number of the adjustment capacitor C1 that can be deployed on the probe card 12 are limited, and the limitation on the capacitor installation space can be limited simultaneously. The number of DUTs tested. Figure 8 is a simplified plan view of the probe card 32 according to Figure 5 of the present invention. The contact points 45 accessed by the 1C tester 30 of Figure 7 are distributed over a relatively large portion of the upper surface 43 of the probe card 32. In the area, the probe 3 7 (not shown) contacting -15-(13)(13)1298922 DUT s 3 4 is concentric under the central area 47 of the probe card which is relatively small. Since the voltage VC charged to the capacitor C2 can be adjusted to accommodate the effective path impedance R2 between any of the switches SW2 and the DUT 34 terminal 41 (Fig. 5), the capacitor C2 can be spaced from the center region 47 above the DUT probe. The capacitor C1 is mounted on the probe card 32 at a greater distance; and since the capacitor C2 is charged to a higher voltage than the capacitor C1, the capacitor C2 can be smaller than the capacitor C1 because the probe card 32 of FIG. The capacitor C2 can be smaller and further away from the center of the probe card than the capacitor C1 of the conventional probe card 12 of FIG. 4, so that a large number of capacitors C2 can be mounted on the probe card 32. Therefore, the test system using the probe card 32 according to the present invention can simultaneously test more DUTs than the test system of the conventional probe card 12 of Fig. 4. &lt;Probe Card with Pattern Generator on Board&gt; Figure 9 depicts an alternative embodiment of the present invention comprising a probe card 50 substantially similar to probe card 32 of Figure 7, except that it is already in it Install one, power control 1C 〃 52. The power control IC 52 includes a pattern generator 54 that performs the tester 3 of FIG. 1C with respect to generating control signals and data CNT1, CNT2, and CNT3 for controlling the switches SW1 and SW2 and the auxiliary power supply 38. The pattern produces a function. The power control 1C 52 includes a conventional pattern generator 54 that is programmed by the programming information generated by the external computer provided by the conventional computer bus 56 before the test is started. The pattern generator 54 begins to generate it. The output data pattern is responsive to the START signal from the 1C tester 5 8 to enable the test start 16-(14) 1298922, and the CNT1, CNT2, CNT3 data pattern that produces its output in response to the same operation as the tester 58 Pulse system clock (SYSCLK). As shown in Figure 9, when the required capacitor C2 is small enough, the switches SW1 and SW2 and the capacitor C2 can be implemented within the power control IC 52, and the IC 52 should be mounted on the probe card as close as possible to the DUT. Needle. The patterning of the switch SW1 and SW2 and the capacitor C2 and the tester 30 can be reduced within the single IC 52 to reduce the cost and complexity of the probe card 32, as well as to reduce the required number of tester 30 output channels, and Desirably, capacitor C2 can be implemented external to power control IC 52 by means of discrete components. &lt;Charge Flow Modulation of Pulse Width Modulation&gt; FIG. 1 depicts an embodiment of the present invention which is substantially similar to the embodiment of FIG. However, in FIG. 10, the switch SW1 is omitted from the probe card 60, so that the VC output of the auxiliary power supply 38 is directly connected to the capacitor C2, and the output voltage VC is fixed and is not adjusted by the ic tester 30. Let C2 charge to the same 之前 before the pulse of each CLOCK signal. In this configuration, the 1C detector 30 will control the amount of charge of the capacitor C2 delivered to the DUTs 34 at the beginning of each CLOCK pulse via the control signal CNT2 via the pulse width modulation switch SW2, at the CLOCK signal pulse. The amount of time that tester 30 turns off S W2 after the wave front will determine the amount of capacitance C2 delivered to DUTs 34. Alternatively, when the tester 30 rapidly increases and then reduces the duty cycle of the CNT2 signal, as depicted by 17-(15) 1298922 in Figure n, it can more closely approximate the 13 depicted in Figure 6. Current flow shape. &lt;Analog-Modulated Charge Flow&gt; Figure 12 depicts an embodiment of the present invention which is substantially similar to the embodiment of Figure 1. However, in Fig. 12, the transistor switch SW2 is replaced by the transistor Q2 operating in its active region when the DUTs 34 system is subjected to a state change and an additional current 13 is required. In this configuration, the CNT2 output of the 1C tester 30 is applied as a data sequence input to an analog-to-digital (A/D) converter 63 mounted on the probe card 61, which represents the cycle of each CLOCK signal. The demand for charging current 13 is predicted during this period. The A/D converter 63 is input to the base of the transistor Q2 in response to the CNT2 data sequence by generating an analog signal CNT4 that varies during the cycle of each CLOCK signal, as depicted in FIG. The analog signal CNT4 controls each transistor Q2 to allow the amount of current 13 flowing out of capacitor C2 to substantially match the predicted transient component of current II required by DUT 34. The A/D converter 63 can be implemented within the 1C tester 30 instead of being mounted on the probe card 61. &lt;Charge Prediction Using Reference DUT&gt; Figure 14 depicts an embodiment of the present invention in which a reference DUT 60 of similar DUTs 34 is tested in a similar manner except that the tester 30 tests the reference DUT 60 by applying it to Refer to the DUT60's CLOCK and other input signals ahead of the other slightly ahead of other DUTs. The main power supply is -18-(16) 1298922. The unit 62 supplies all the DUTs 34 and the auxiliary power supply 64 supplies the reference DUT 60. The capacitor C4 mounted on the probe card 66 near the reference DUT 60 adjusts the voltage VREF in a conventional manner. At its power input 68, it is allowed to stay within its allowed operating range, capacitor C5 is coupled to VREF to a set of amplifiers A1, and capacitor C6 is coupled to the output of each amplifier A1 to the power input 70 of each DUT 34. Due to the requirement of the transient charging current of the reference DUT, the supply voltage VREF at the input 68 of the reference DUT 60 will fall below its static level after the start of each CLOCK signal cycle by good adjustment. The amount of voltage tilt in VREF is proportional to the amount of transient charging current generated by the reference DUT. Since the reference DUT is similar to the DUTs 34 and the test is slightly ahead of the DUTs 34, the tilt in VREF predicts the amount of transient charging current for each DUT 34 after a short time. Amplifier A1, which operates through capacitors C5 and C6, amplifies the AC component of VREF to produce an output current 13 that increases the current output 12 of mains supply 62, and provides current input II to each DUT 34. The amount of time that the tester 30 leads the DUT 60 test is set to be equal to the delay between the change in the reference voltage VREF and the corresponding change in the current 13. With the (negative) gain of each amplifier A1 suitably adjusted by an externally generated signal (GAIN), current 13 will substantially match the transient charging current required by DUTs 34. &lt;Charge prediction in a non-test environment) In addition to being effective in reducing power supply noise when testing integrated circuits, -19-(17) 1298922, embodiments of the present invention may also pass through a series of integrated circuits therein. The measurable state is used in applications to reduce power supply noise. Figure 15 depicts an example of the present invention in which the integrated circuit 80 passes the state of the predictable series in response to the edge of the externally generated CLOCK signal supplied as an input thereto, and the IC 80 accepts power from the main power supply, the auxiliary power supply. The supplier 84 charges the capacitor C2 via the OFF SW1 when the switch SW1 is closed, and the capacitor C2 takes its charge as an additional current input to the IC 80 when the switch SW2 is closed. The charge predictor circuit 80 allows the auxiliary power supply 8 4 to be turned on in response to the CLOCK signal by the request signal CNT1 to close the switch SW1 and the request control signal CNT2 while the IC 80 is in a portion of each of the CLOCK letters that are not changing states. During the state change charging capacitor C2, the charge prediction circuit 86 may request the control signal CNT2 to close the switch SW2 without requiring the control signal CNT1 to turn on the switch SW1 during a portion of each CLOCK signal cycle in which the IC 80 is not changing state, by the capacitor C2 circulates current to the power input of IC80 to provide its desired transient current. The charge predictor circuit 86 also provides a control data CNT2 auxiliary power supply 84 to adjust its output voltage VC to a level determined by the charging device C2 to an amount of power expected by the IC 80 during the next state change. The charge predictor 86 is suitably implemented by a conventional pattern generator or any other device that produces an output data sequence CNT1, CNT2 CNT3 suitable for the transient current requirements of the IC 80 for its intended state sequence. The switches SW1 and SW2 can be implemented outside the IC 80 as depicted in Fig. 15, or can be implemented in the internal 80 of the IC80. / No. This is not the power and the current capacity and medium -20- ( 18) 1298922 &lt;Charge Averaging Method&gt; Figure 16 depicts a simplified form of the present invention suitable for use in applications where IC 80 is charged within a fairly limited predictable range at the beginning of each CLOCK signal cycle. . As shown in FIG. 16, the inverter 90 inverts the CLOCK signal to provide a CNT1 control input to a switch that couples the auxiliary power supply to the capacitor C2. The CLOCK signal directly supplies the CNT2 control signal to a capacitor C2 for general borrowing. The switch SW2 of the IC80 input driven by the main power supply 82. As shown in Fig. 17, the CLOCK signal CLOCK signal drives the CNT2 signal boost switch SW2 during the first half of the cycle, and drives the CNT1 signal high in the second half of each CLOCK signal cycle to close the switch SW1. The output voltage VC of the auxiliary power supply 84 is set to a constant level to charge the capacitor C2 to the level before the start of each CLOCK signal cycle. The level of VC is set to appropriately determine the range in which the power supply voltage VB swings when the charging current being generated by the IC 80 is started at the start of each CLOCK signal cycle, for example, when we want to make the static of VB in the middle of its range. We can adjust VC so that capacitor C2 should be in the middle of the range of charging current expected to be generated by IC80. On the other hand, if we want to prevent VB from falling below its static level, we prefer VB to rise to its static state. Above, we can adjust so that capacitor C2 can supply a large amount of charging current that is expected to be generated by 1C 80. Although capacitor C2 can predict the SW1 connection power in the flow diagram during each CLOCK signal cycle during each closed period, the same additional input level is available, the pole | VC of the most supply - 21 - (19) 1298922 is extremely small The charging current and the large charging current are supplied during other CLOCK signal cycles, but in many applications, the system depicted in Figure 16 can keep the VB swing within an acceptable range when VC is properly adjusted. It should be noted that the systems of Figures 5, 9, 14 and 15 can be programmed in a similar manner by setting the control data CNT3 for each CLOCK signal cycle to be the same. &lt;Adaptability Current Compensation&gt; Figure 18 depicts another representative embodiment of the present invention. As shown in FIG. 18, the power supply 36 supplies power through the probe card 50 to the power input terminal 1 806 on the semiconductor device (DUT) 34 under test, through the power line 1812 on the probe card 50. The representation of the intrinsic impedance is depicted as R1 in Figure 18, and as shown in Figure 18, the 1C tester 58 provides clock and other signals to the DUT 34 via the probe card, on the representative DUT 34. The clock input terminal is depicted as terminal 1808. The 1C tester 58 also receives signals from the DUT 34 via the probe card 50, and displays an input/output (I/O) sub-1810 on the DUT 34 in FIG. However, the DUT 34 may have additional I/O terminals 1810 or may have outputs dedicated only to the input or other terminals dedicated only to the output, or terminals dedicated only to the input or output and other functions being input and output terminals. combination. Significantly, the probe card 50 can be coupled to a DUT as shown in Figure 18 or to a plurality of DUTs as shown in Figure 14. As shown in FIG. 18, the current sensing device 1804 (eg, a current sensing coupler or current converter) can sense the current of the -22-(20) 1298922 flow through the bypass capacitor c1. The amplifier 1 8 02, which is preferably an inverting amplifier (for example, the amplifier has a negative one), can provide current through the capacitor C7 into the transmission 1812, and the auxiliary power supply 38 supplies power to the amplifier 1802. Of course, it can be supplied by other devices. Power to amplifier 18 02, comprising a power supply from source supply 36, IC tester 5 8, located on probe card 50, or in addition to the power supply 3 6, 1C tester 5 8, or probe The power supply provided outside the card. In operation, as described above, the power terminal 180 6 typically produces a small current (assuming the DUT 34 primarily contains a field effect transistor), and in only a few cases, the power terminal 108 generates a large amount of current. As noted above, the most common occurrences arise when at least one of the transistors in the DUT 34 is in a state that typically occurs with respect to the relationship of the rising or falling edges of the clock at the clock terminal 108. When the DUT 34 is not changing state, the amount of current generated at the power terminal 1 8 06 will only pass through the bypass capacitor C1 and typically be small and mainly static DC (DC) flow or no current flow, The small to zero current sensed by the current sensing device 108 is generated and thus the current to the inverting amplifier 108 is as small as zero. However, when the DUT 34 is changing state, as described above, the power sub-186 will temporarily generate a large amount of current, which will generate a temporary large amount and change the flow current, current through the path capacitor C1 as described above. It is sensed by the current sensing device 10804 and inverted and amplified by the inverting amplification 1802, and finally lifted into the power line 1 8 1 2 through the isolation capacitor C7. As mentioned above, the additional current is reduced by the amplifier 1 8 0 2 provided in the benefit line of the sub-construction of the sub-construction of the white end of the current supply -23- (21) 1298922 rate line 18 12 A change in the voltage at power terminal 1 806. Figure 19 depicts a variation of the representative embodiment shown in Figure 18. As shown, Figure 19 is generally similar to Figure 18 and also includes an electrical influenza component 1 804 and an inverting amplifier 1 802 constructed to provide current to the power line 1812 on the probe card 50. However, in Fig. 19, the electrical influenza measuring component 108 will sense the current flowing through the power line 1 8 1 2 instead of the current flowing through the bypass capacitor C 1 . The operation of the embodiment of Figure 19 is similar to the operation of Figure 18. When the DUT 34 is not changing state, a typical small, primary static DC (DC) generated by the power terminal 1 806 via line 1 804 is sensed by the current sensing device 108, and thus, the inverting amplifier 1 8 02 provides little or no charging current. However, when the DUT 34 is changing state, the current sensing device 1 800 will sense a large current change generated by the power terminal 1 8 0 6 at the power terminal 1 800, and the inverting amplifier 1 802 will The sensed current is amplified and inverted to provide additional charging current through the isolation capacitor C7 to within the power line 1 8 1 2 . As mentioned above, this additional charging current will reduce the variation in the voltage at the power terminal 186. &lt;Interconnect System&gt; In the above-described probe card for providing a signal path in any of the embodiments between the integrated circuit tester, the power supply and the DUTs, the present invention can be combined with many Other designs of interconnect systems are implemented, for example, Figure 20A depicts a relatively simple probe card that includes a substrate -24 (22) (22) 1298922 2 0 02 with terminal 2004 for connection to a 1C tester (not shown in Fig. 20A) and having the probe element 2008 for electrical connection to the DUT (not shown in Fig. 20A). As shown, terminal 2004 is electrically coupled to probe card component 2008 by interconnecting component 2006. For example, the substrate can be a single or multi-layer printed circuit board or ceramic or other material. Obviously, the material composition of the substrate is not critical to the invention. The probe element 2008 can be any type of probe that can be electrically coupled to the DUT, including but not limited to needle probes, COBRA type probes, bumps, posts, rods, spring contacts, and the like. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; US Patent No. 62680 1 5 B1, and U.S. Patent Application Serial No. 09/3,648, assigned to PCT Publication No. WO 01/0 9952, filed on Jun. For reference here. Such spring contacts can be considered as described in U.S. Patent No. 6,150,186, the disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in the the the the the the the the the the Optionally, the probes may be pads or terminals for contacting the riser elements on the DUT, such as spring contacts formed on the DUT. An unrestricted example of interconnect path 2006 includes a combination of vias and/or vias with conductive traces on the surface of substrate 2002 or within substrate 2〇〇2. Figure 20B depicts another unrestricted example of a probe card that can be used in the present invention. As shown, the representative probe card shown in Fig. 20B includes a substrate 2018, an interposer 2012, and a probe head 2032. Terminal 2022 is in contact with a -25-(23) 1298922 1C tester (not shown in Figure 20B), and probe element 2034, which may be similar to probe element 2008 described above, is in contact with the DUT (not shown in Figure 20B) . The interconnect path 2020, the resilient connection element 2016, the interconnect path 2014, the resilient connection element 2010, and the interconnect path 203 6 provide a conductive path from the terminal 2022 to the probe element 2034. The substrate 2018, the interposer 2012, and the probe head 2032 can be made of the same material as described above in relation to 20 02. Indeed, the material composition of substrate 2018, interposer 2012, and probe tip 2032 is not essential to the invention, but any composition can be used. Interconnect paths 2020, 2014, 2 03 6 may be similar to interconnect path 2006 as described above. The elastic connecting members 2016 and 2010 are preferably elongate elastic members, and an unrestricted example of such elements is depicted in U.S. Patent No. 5,472,621; U.S. Patent Application Serial No. 08, filed on Feb. /8 02054, which corresponds to PCT Publication No. WO 97/44676; U.S. Patent No. 626 80 1 5B1; and U.S. Patent No. PCT Publication No. WO 0 1/09952, filed on July 30, 1999 In the application No. 09/364,855, all of which are incorporated herein by reference. A more detailed description of a plurality of representative probe cards, such as those shown in Figure 20B, is found in U.S. Patent No. 5,976,626, the disclosure of which is incorporated herein by reference. Many variations of the representative design shown in FIG. 20B are possible, for example, as just one example, the interconnect path 2014 can be replaced with a hole and one or more fixed in the hole and extending to the hole. The outer elastic members 2016 and/or 2010 contact the substrate 2018 and the probe card 2032. However, it should be understood that the architecture or design of the &apos;interconnect system is not essential to the present invention, but any architecture or design may be used. As shown in the embodiments described herein, the circuitry for reducing variations in the voltage at the power terminals on the DUT is preferably disposed on the probe card. If multiple substrate probe cards are used, Such a representative probe, such as shown in Figure 20B, may be located on any of the substrates or may be distributed among two or more of the substrates. Thus, for example, the circuit can be located on one of the probe head 2032, the interposer 2012, or the substrate 2018 depicted in FIG. 20B, or the circuit can be located in the probe head, the interposer, and/or the substrate. Above or more combinations. It should be understood that the circuit may be integrally formed of interconnected discrete circuit components, may be integrally formed on an integrated circuit, or may be comprised of a portion of discrete circuit components and a portion of the components formed on the integrated circuit. &lt;Predictive/adaptive circuit compensation&gt; As described above, a predictive system for controlling a change in the supply voltage at the power input terminal of the DUT can predict the amount of charging current that the DUT will require during each clock signal cycle, and Then, according to the prediction, the magnitude of the supplemental current pulse applied to the power input terminal of the DUT is determined during the clock signal cycle; on the other hand, the adaptive system can monitor the power signal applied to the terminal of the DUT and utilize feedback To adjust the size of the supplemental current pulse, while maintaining the voltage of the power signal is constant. Figure 21 depicts an embodiment of the invention in which the amount of additional charge current required at the power input terminal 26 of the DUT 34 is determined by a combination of prediction and adaptation. The auxiliary power supply 38 supplies power VC to current -27-(25) 1298922 pulse generator 2102, when it is necessary to increase the normal supply current from the main power supply 36, the current pulse generator 2102 will supply current pulse 13 to the power input terminal 26 of the DUT. At the beginning of each test cycle, the 1C tester 58 will supply the signal CNT5 to the current pulse generator 2102 to indicate the predicted magnitude of the current pulse, and during each test cycle the '1C tester 58 will request the control signal CNT6. A current pulse generator 2102 is instructed when a current pulse is generated. The 1C tester 58 is programmed to test a particular form of DUT 34, and the predictions made with respect to the magnitude and time period of the current pulse 13 required during each test cycle can be generated as described above for the DUT of the form. Current measurement or simulation of DUT behavior. However, due to process variations in the manufacture of DUTs and other factors, the amount of additional charging current that each DUT of the form will require during each test cycle can vary from the predicted charging current. For any given DUT, the ratio of the actual charging current produced to the predicted charging current tends to be fairly uniform on a cyclic basis, such as a DUT that consistently produces a predicted charge during each test cycle. The current is more than 5% of the charging current, while the other DUT at the same time consistently produces a charging current that is 5% less than the predicted charging current during each test cycle. The feedback controller 2104 compensates for such changes in the charging current requirement and the prediction 借 by supplying an adaptive gain (or A adaptation 〃) signal G to the current pulse generator 2 1 02, which appropriately increases or decreases the current pulse Wave 13 is sized to adapt the current pulse to the requirements of the particular DUT 3 4 currently in the test. Therefore, the prediction signal CNT5 indicates the predicted magnitude of the charging current required by the form -28-(26)(26)1298922 DUT being tested, and the gain (adaptation 信号) signal size indicates the specific condition of the DUT being tested. Prediction error. Prior to testing the DUT 34, the 1C tester 58 performs a pre-test procedure similar to the test to be performed, where it transmits the test and CLOCK signal pulses to the DUT 34, causing the DUT 34 to behave substantially the same as its behavior during the test. During the pre-test procedure, the feedback control circuit 2 10 04 monitors the voltage VB at the power input terminal 26 of the DUT and adjusts the magnitude of the gain signal G, so that it occurs in VB when the size of 13 is too large or too small. The change is minimized. The pre-test procedure causes the feedback controller 2 10 04 to adjust the magnitude of the gain signal G to accommodate the charging current demand of the particular DUT 3 4 to be tested, after which the feedback controller 2 1 04 continues during the test. The VB is monitored and the gain signal is adjusted, but the adjustments made are small. Therefore, although the magnitude of the charge current 13 supplied during each test cycle is primarily a function of the predicted charge current demand of the DUT, the gain control feedback provided by the controller 2 104 will eventually adjust the current pulse magnitude to The tendency to adapt to any consistency in the actual charging current demand of the DUT varies with the predicted demand. Those skilled in the art will appreciate that the feedback controller 2 10 04 of Figure 21 can be any of a number of designs that produce an output gain control signal G that minimizes variations in VB. Those skilled in the art will also appreciate that the current pulse generator can be any of a number of designs capable of generating a current pulse 13, wherein the timing of 13 is controlled by the input signal CNT6, and wherein 13 The size is the current pulse wave size of the -29 - (27) 1298922 and the adaptive gain signal G size represented by the control signal CNT5. FIG. 22 depicts the feedback of the AC component of the non-limiting VB of the controller 2 1 04 to generate the gain control signal G. The container C10 passes through the AC component of the VB to an integrator 2 106. The capacitor R5 is connected in parallel by an operational amplifier A1 and has a resistor R4 &gt; connected in series to its input; Fig. 23 depicts the current pulse wave of Fig. 21 Example. In this example, the data of the predicted magnitude of the pulse 13 of the control signal CNT 5 is digital to analog. The predicted data of the analog current test cycle is an analog signal P of a proportional magnitude. When the 1C tester 58 is to indicate when the current pulse 13 will be generated, the switch 2 1 : the signal P to the input of the variable gain amplifier 2112 of the auxiliary power supply 38 of Fig. 21. The gain control signal output of 21 2 104 will control the amplifier: the amplifier 2112 will generate a pulse 13 proportional to the product of P and G, and the capacitor C7 will transmit power to the signal path of the DUT 34 through the 13 signal pulse 3 card 50. Figure 24 depicts a non-limiting example of current pulse generation in Figure 21. In this example, the time length of the 1C CNT5 control signal of FIG. 21 is proportional to the predicted maximum pulse wave 13 of the current pulse wave 13 generated during the lower-loop period, and the CNT5 is required after the pulse generator 13 of each of the 13 signals is generated. The signal is closed by a function of coupling through the resistor. A fixed example is formed by integrating DC (DC) power 2106, which is formed by the integrator C8 and the resistor. The non-restricted output of the L device 2106 represents the required current converter (DAC). For example, the CNT6 signal is obtained in the prediction data, and the CNT is closed to apply the gain of the feedback controller Π 1 2 of the energy supply diagram of the VC output, and the amplification is small. The output current 1 of the probe of Figure 2: another tester of the device 2106 5 8 requires -CLOCK signal to follow the small, the current pulse 1C tester 58 will assist the power supply to send -30- (28) 1298922 out signal VC to capacitor C 8 switch 2 1 1 6 , 1C tester 58 continues to request the CNT5 signal for a period of time, the amount of time will increase with the predicted size of the next 13 signal pulse, so Figure 2 The auxiliary power supply 38 charges the capacitor C 8 to a voltage proportional to the predicted magnitude of the next 13 signal pulses. Thereafter, when the 1C tester 58 requests the CNT6 signal to indicate that the next 13 signal pulse will be generated, the switch 21 17 connects the capacitor C8 to a gain control signal output G having the feedback controller 2104 of FIG. The gain of the amplifier 2118 is input. The coupling capacitor C9 transfers the generated 13 signal to the probe power of the 21st picture to the probe card conductor 2114 of the DUT 35, and after the capacitor C8 has been substantially discharged in a timely manner, the control signal CNT6 turns on the switch 21 17 . Since the magnitude of the 13-current pulse wave rises rapidly and then tilts when C8 is discharged, the behavior of the time variation of the 13-pulse wave tends to be similar to the time-varying charging current requirement of the DUT. Figure 25 depicts yet another non-limiting example of the current pulse generator 2106 of Figure 21, wherein the data transmitted by the CNT5 signal represents the predicted magnitude of the 13 signal pulse, and the gain control signal G acts as the data transmitted by the converted CNT5. To reference the reference voltage of DAC2 120 of signal P, the voltage scale of gain control signal G will define the range of DAC output signal P such that P is proportional to the product of G and CNT5. The switch 2122 temporarily transmits a P signal to the amplifier 2124 in response to the pulse of the control signal CNT6, thereby causing the amplifier 2125 to transmit 13 signal pulses to the power conductor 2 1 1 4 via the coupling capacitor C5, the 13 signal pulse size Will be proportional to the product of G and P size. -31 - (29) 1298922 Figure 26 depicts an still undefined example of a predictive/adaptive system in accordance with the present invention in which auxiliary power supply 38 supplies power to variable gain amplifier 2126 and whenever 1C is tested When the 58 predicts that additional charging current will be required at the power input terminal 26 of the DUT 3 4, it will supply the control signal pulse CNT6 to the amplifier 2126. Capacitor C11 delivers a 13 signal pulse to power signal path 2114 in probe card 50 that is coupled to power supply 36 to DUT power input terminal 26, and feedback control circuit 2104 monitors voltage VB present at terminal 26 and adjusts amplifier 2 The gain of 126 is to minimize the variation in VB. At the beginning of each CLOCK cycle, the 1C tester 58 supplies a control signal CNT5 as an input to the auxiliary power supply 38 for setting its output voltage VC based on the size of the data transmitted by the CNT5 control signal. Thus, the size of 13 is a function of the product of the gain control signal G and the auxiliary power supply voltage VC. Thus, Figures 21 to 26 depict additional charging currents provided after the edges of the CLOCK signal in accordance with the present invention. To the power input terminal 26 of the DUT to accommodate the difference in the predictive/adaptive control system of the voltage applied to the power signal VB of the DUT 34 due to the increase in the temporary current required for the initial switching of the edge of the CLOCK signal Representative examples. The control system is 'v predictive 〃, which predicts the amount of additional current that the DUT will require during each cycle of the test; the control system is also 'adaptive 〃, which uses feedback to determine the resulting response to the prediction. The magnitude of the current pulse is adapted to the observed change in the amount of current actually generated by the individual DUTs to be tested. -32- (30) 1298922 Although the invention is depicted herein as reducing noise in a system employing only a single primary power supply, it will be understood that the invention may be employed in which more than one primary power supply is provided Provide power in the environment of DUTs. Although the present invention is depicted as operating in conjunction with DUTs having a single power input, it will be appreciated that the apparatus can be adapted to operate in conjunction with DUTs having multiple power inputs. Although the present invention is described as providing an additional charging current after the leading edge of the CLOCK signal pulse, it may also provide an additional charging current after the trailing edge of the CLOCK signal pulse for use in the trailing edge switch of the CLOCK signal. DUTs. Although the present invention has been described for use in conjunction with a different form of a 1C tester that uses a probe card to access ICs terminals formed on a semiconductor wafer, those skilled in the art will appreciate that the present invention may employ a combination. 1C tester using other forms of interface equipment to provide DUT terminals that are connected to ICs that are still at the wafer level, or DUT terminals of ICs that can be separated from the wafers they form; and their availability or not It will be incorporated into the DUT terminals of the packaged ICs at the time of its testing. These interface devices include, but are not limited to, load plates, burn-in boards, and final test boards. The invention in its broadest form is not intended to be limited to any particular form of 1C tester, any particular form of tester to DUT interconnect system, or any particular form of IC DUT application. It will also be understood by those skilled in the art that although the invention described above is incorporated in a test coupled to an integrated circuit, it can also be used when testing any type of electronic device, such as Includes a combination of flip-flops, boards and the like, or whenever -33- (31) 1298922 is expected to accurately adjust the voltage at the power input terminals of the device during testing. Having thus described the preferred embodiments of the present invention, it will be understood by those skilled in the art that many modifications may be made to the embodiments without departing from the invention. Therefore, the scope of the appendices of the appendix is intended to cover all such modifications as being included in the true scope and spirit of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram depicting a typical prior art test system including an integrated circuit tester connected to a set of integrated circuit devices (DUTs) through a probe card; And FIG. 3 are timing diagrams depicting signal behavior within the prior art of FIG. 1; FIG. 4 is a simplified plan view of a conventional probe card of FIG. 1; • FIG. 5 is a block diagram depicting A test system according to a first embodiment of the present invention, wherein a system for reducing noise in a power supply input of a group of DUTs is implemented; FIG. 6 is a timing chart depicting signal line 2 in the test system of FIG. For example, 'Figure 7 is a block diagram depicting the operation of the test system of Figure 5 during the calibration procedure; Figure 8 is a simplified plan view of the probe card of Figure 6; Figures 9 and 10 are block diagrams depicting The test system of the second and third-34-(32) 1298922 embodiments of the present invention is implemented; FIG. 1 is a timing diagram depicting the signal behavior in the test system of the first diagram; Depicting a test system embodying a fourth embodiment of the present invention; a timing diagram depicting signal behavior in the test system of FIG. 2, a block diagram of a first embodiment of the present invention; and a fifth block diagram depicting a sixth embodiment of the present invention; Figure 16 is a block diagram showing a seventh embodiment of the present invention; Figure 17 is a timing chart showing a signal behavior in the circuit of Figure 16 showing a eighth embodiment of the present invention; Figure 19 is a block diagram depicting a ninth embodiment of the present invention; Figure 2A depicts a representative probe card; Figure 2B depicts another representative probe card; Figure 4 is a block diagram depicting a tenth embodiment of the present invention; Figure 2 is a block diagram depicting a representative embodiment of the feedback control circuit of Figure 21; a block diagram of Figures 23 through 25 depicting the 21st A representative embodiment of the selection of the current pulse wave &quot; generator of the figure; and a block diagram of the drawing of the second embodiment of the present invention. [Main component comparison table] -35- (33) (33) 1298922 10, 30, 38: 1C Tester 12, 32, 50, 60, 61, 66: Probe card 14, 34, 35 · · Tested Devices (DUTs) 1 5 : Spring pins 1 6 : Contacts 1 8 , 3 7 : Probes 19, 39, 1810, 1 8 08 : Input / Output (I/O) pads 2 〇: Conductive paths 22, 43 : path impedance 24, 36, 62, 82: main power supply 26, 41, 68, 1806: power input terminals 28, 46: signal path 25: upper surface 2 7, 4 7 · center area 38, 84: auxiliary Power Supply 40: Reference DUT (Reference 1C) 45: Contact Point 5 2: Power Control IC 54: Pattern Generator 56: Computer Bus 63: Analog to Digital (A/D) Converter 80: Integrated Circuit 86: Charge Predictor Circuit 90: Inverter-36- (34) (34)

1298922 18 12 : Transmission line 1 804 : Current sensing devices 1802, 2112, 2118, 2124, 2125, 2126 : Amplifiers 2002, 2018 : Substrate 2 0 0 8 : Probes 2004, 2022: Terminals 2006, 2020: Interconnect path 2 0 1 2 : interposer 203 2 : probe head 2034 : probe element 2 0 1 0, 2 0 1 6 : elastic connection element 2014, 203 6 : interconnection path 2 102 : current pulse generator 2 104 : back Controller 2 1 1 4 : Power signal path 2116, 2117, 2110: Switch 2 120 : DAC (digital to analog converter) G : gain control signal CNT1 ~ CNT6 : control signal 2106 : integrator -37-

Claims (1)

1298922 (1) X. Patent Application No. 1 A method for testing a supply current to a semiconductor device by means of a bulk circuit during testing of a semiconductor device, the integrated circuit tester accessing the input/output (I/O) of the semiconductor device via an interface device a terminal, the interface device providing a signal path between the I/O terminals and the integrated circuit test, wherein the semiconductor device includes a power input terminal for receiving a current through a power conductor provided by the interface device And wherein the semiconductor device temporarily increases its demand for supply current after applying the edges of a set of edges of a clock signal of the input of the semiconductor device, the method comprising the steps of: (a) during the test Supplying a first current to the power input terminal 9 b ) generating a prediction signal indicative of a magnitude proportional to a predicted amount by which the semiconductor device can increase its power input after one of the edges of the clock signals Current demand at the terminal; c) generating an adaptive signal indicating that a response is present at the power input a magnitude determined by the voltage at the terminal; and d) supplying a current pulse to the power input terminal to supplement the first current after each edge of the edge of the clock signal, wherein the magnitude of the current pulse is a predictive signal And a function that adapts to the size represented by the signal. 2. The method of claim 1, wherein the integrated circuit tester performs step b. 3. The method of claim 1, wherein the magnitude of the current pulse is proportional to the predicted signal and the size represented by the adaptive signal - 38 - 1298922 The product of. 4. The method of claim 1, wherein the magnitude of the adaptation signal is a function of a voltage at a time varying portion of the time integral at the power input terminal. 5. The method of claim 4, wherein step c comprises the following additional steps: cl) filtering the voltage present at the power input terminal to produce a proportional amount of voltage present at the power input terminal a varying magnitude of the filtered voltage; and c2) integrating the filtered voltage to produce the adapted signal. 6. The method of claim 1, wherein the step d comprises the following subsidiary steps: dl) generating an analog signal in response to the predicted signal, the magnitude of the analog signal being proportional to the size represented by the predicted signal; And d2) temporarily applying the analog signal to an input of an amplifier after the edges of the clock signals, such that the amplifier generates a current pulse wave after the edge of each of the clock signals, wherein the magnitude of the current pulse wave is The magnitude of the analog signal and the magnitude of the magnitude represented by the adaptive signal. 7. The method of claim 1, wherein the step d comprises the following subsidiary steps: d1) generating an analog signal in response to the predicted signal and the appropriate signal, the analog signal having a size, the size And the d2) temporarily applying the analog signal to the edge of each of the clock signals -39-(3) 1298922 as an input of the amplifier, such that the amplifier A current pulse is then generated as a function of the magnitude of the current number. 8. The method of claim 1, wherein the capacitor voltage at the edge of each of the clock signals is a function of the magnitude of the signal in response to the prediction signal; and d2) The input of the amplifier at the edge of the isochronous signal causes the amplifier to generate a current pulse wave, wherein the magnitude of the current pulse pressure and the indication indicated by the adaptive signal are as attached to the first item of the patent application scope. Step: dl) by generating a voltage output signal, the voltage output signal is represented by the prediction signal d2) by adjusting a gain of the amplifier produced by step dl in response to the adaptation signal d3) at the edge of each of the clock signals The input of the amplifier is such that the amplifier is in each signal pulse wave, wherein the voltage of the current pulse wave and the size represented by the adaptation signal are: 1 〇. The size indicated by the number of the first application patent range Retrieving the grant to adjust the magnitude of the pulse wave at the edge of each of the clock signals is the analogy signal, wherein step d includes charging the capacitor to the capacitor voltage system after the prediction When the capacitor is connected to each one of the wave function of the magnitude of the clock signal edges of the capacitor-based electrical size. a method, wherein the step d includes a function of a magnitude corresponding to the prediction signal; generating an energy supply number of the output signal; and temporarily applying a signal pulse to generate a current pulse wave in response to the magnitude of the output signal Electrical function. The method wherein the adaptation signal is used to minimize variations in the voltage present at the input terminal of the power -40-(4)(4)1298922. 1 1 · A method for reducing variations in voltage supplied to a power input terminal of a semiconductor device under test, for use in a semiconductor test system including a probe card and a supplemental current source, the method comprising the steps of: providing through the probe card Power to the power input terminal of the semiconductor device in the test; providing an input signal to the supplemental current source, the input signal being responsive to a temporary change in current generated by the input terminal of the semiconductor device; and from the supplemental current source A supplemental current is provided to the input terminal in response to the input signal. The method of claim 11, further comprising changing a state of the semiconductor device that causes the temporary change in current generated by the input terminal of the semiconductor device. The method of claim 11, further comprising sensing a change in current generated by the input terminal of the semiconductor device. The method of claim 13, wherein the sensing of the change in the current generated by the input terminal comprises electrically connecting to the power input terminal via a bypass capacitor to sense a change in current. The method of claim 13, wherein the change in the current generated by the sensing input terminal comprises a transparent path that is electrically connected to the power input terminal of the probe card. The change in the sense current 〇1 6 · The method of claim 1, wherein the supplemental current -41 - (5) 1298922 corresponds to the amount of current generated by the input terminal. The method of claim 11, wherein the supplemental current source comprises an amplifier. The method of claim 11, wherein the supplemental current is supplied to the input terminal through a capacitor. The method of claim 11, wherein the supplemental current source is disposed on the probe card. The method of claim 11, wherein the probe card comprises a plurality of interconnected substrates. 2. The method of claim 20, wherein the plurality of interconnected substrates comprise a probe head. 2. The method of claim 21, wherein the supplemental current source is disposed above the probe head. 2 3. The method of claim 11, wherein the method further comprises configuring at least one advanced signal to a reference device. 24. The method of claim 23, wherein the input signal of the supplemental current source corresponds to the amount of current generated by the reference device to respond to the at least one advanced signal. 2. The method of claim 11, wherein the providing power further comprises providing power through the probe card to a power input terminal of each of the plurality of tested semiconductor devices; the providing an input signal to the supplemental current source Further comprising providing an input signal to each of the plurality of supplemental current sources, each of the input signals corresponding to a current generated by an input terminal of one of the semiconductor devices; and -42-(6)1298922 providing a supplemental current further comprising Each of the supplemental current sources provides supplemental current to the input terminals in response to the input signals. -43-