TW200302539A - Predictive, adaptive power supply for an integrated circuit under test - Google Patents

Abstract

A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

Description

200302539 (1) 发明. Description of the invention [Technical field to which the invention belongs] In general, the present invention relates to testing integrated circuits, and in particular, relates to power supply noise for reducing logic state transitions that would cause the integrated circuits to perform during the testing of integrated circuits installation. [Previous Technology] The integrated circuit (1C) tester can simultaneously test a group of ICs in the form of grains on a semiconductor wafer. Figure 1 is a block diagram depicting a typical 1C tester 1 〇, tester 1 〇, connected to a set of identical tests J c devices (DUTs) 14 through a probe card 12 connected to a semiconductor wafer. Use spring pins 15 or other devices to connect different input and output terminals to a group of contacts 16 on the probe card 12. The probe card 12 includes a set of probes 18 for contacting the input / output (I / O) pads 19 on the surface of each DUT 14 and provides a conductive path 20 connecting the contacts 16 to the probes 18 through The path of the probe card 12 allows the tester 10 to transmit a test signal to the DUT 14 and monitor the output signal generated by the DUT 14. Because the digital integrated circuit often includes timing pulses in response to the synchronous logic gate of the periodic main clock signal (CLOCK), the probe card 12 also provides a path 22 through which the tester 1 can supply the CLOCK signal to Each DUT14. The test system also includes a power supply 24 for supplying power to the DUTs 14 when they are tested, and the probe card 12 is connected to the power input pad 26 of each DUT 14 via the probe 18. Each switching transistor in DUT 14 has an inherent input capacitance. (2) (2) 200302539. In order to turn the transistor on or off, the driver of the transistor must charge or discharge the input capacitance of the transistor. When the driver charges the input capacitance of the transistor, it will get the charging current from the power supply 24. Once the input capacitance of the transistor is fully charged, its driver only needs to supply a relatively small amount of leakage current 'required to keep the input capacitance of the transistor charged to keep the transistor on or off. In the DUTs implementing synchronous logic, most of the switching of the transistors will occur immediately after the edge of each CLOCK signal pulse, so immediately after the CLOCK signal of each pulse, the power supply current input to each DUT 1 4 There is a temporary increase in 11, and the charging current required to change the switching state of different transistors in the DUT is provided. Then in the CLOCK signal cycle, after the transistors have changed state, the demand for the supply current 11 will become > The steady state level of the static chirp is maintained there until the next CLOCK signal cycle begins. Through this, the probe card 12 can be connected to the power supply 24 in the signal path 28 of each DUT 14 and has the inherent impedance represented by the resistor R1 in the first figure. Because there is a voltage drop between the output of the power supply 24 and the power input 26 of the DUT 14, the supply voltage input VB of the DUT 14 will be somewhat less than the output voltage VA of the power supply 24, and although VA can be better adjusted , But VB will change with the magnitude of the current 11. After the start of each CLOCK signal cycle, a temporary increase in 11 required by the input capacitance of the charging switch transistor will increase the voltage drop across R1, thus temporarily reducing VB. Since the slope in the supply voltage V B that occurs after the edge of each CLOCK signal is a noise pattern that can adversely affect the performance of the DUTs 14 (3) (3) 200302539, it is hoped to limit its size and duration. We can limit the noise by reducing the reactance of these paths 28 between the power supply 24 and the DUTs 14, such as by increasing the size of the conductor or by minimizing the length of the path 28. However, by this, we will have practical restrictions on reducing the amount of this reactance. We can also reduce power noise by setting capacitor C1 on the probe card 12 near the power input 26 of each DUT 14. Figure 2 depicts the behavior of the supply voltage VB and current II at the power input 26 of IC14 in response to the pulse of the CLOCK signal input to 1C 14 when capacitor C1 is not very large. It should be noted that, after the edge of the CLOCK signal at time T1, a temporary rise above its static level IQ in 11 will produce a temporary increase in the voltage drop on R1, which will sequentially be in the supply voltage VC Produces a temporary tilt below its static level VQ. Figure 3 depicts the behavior of VB and II when capacitor C1 is very large. Between the CLOCK signal pulses, when DUT 14 is static, capacitor C1 is charged to the static level of VB. After the rising (or falling) edge of the CLOCK signal at time T1, when DUT 14 temporarily needs more current, capacitor C1 will supply some of its stored charge to DUT 14, thereby reducing the amount of additional current, so The power supply 24 must be provided to meet the increased demand. For example, it can be found in FIG. 3 that the presence of the capacitor C 1 reduces the magnitude of the temporary voltage drop of R 1 and thus reduces the magnitude of the slope in the supply voltage VB input to the DUT 14. For a capacitor to sufficiently limit the change in VB, the capacitor must be large enough to supply the required charge to DUT 14 and must be positioned close to DUT 14 such that the path impedance between C1 and DUT 14 is extremely low. (4) (4) 200302539 Unfortunately, it is not always convenient or feasible to install a large capacitor above the probe card 12 near the power input terminal 26 of each DUT 14. Figure 4 is a simplified plan view of a typical probe card 12, with the 1C tester 10 located above the probe card and wafers containing DUTs 14 held below the probe card. Because the I / O terminals of the 1C tester 10 of FIG. 1 are distributed over a relatively large area compared to the surface area of the wafer under test, the probe card 12 provides a relatively large upper surface 25 for holding Tester access point 16. On the other hand, the probes 18 (not shown) under the probe card 12 that contact the DUTs 14 on the wafer are concentrated under the relatively small center area 27 of the probe card 12. The path impedance between the contacts on the upper surface 25 of the probe card 12 and the probes 18 below the area 27 is a function of the distance between each contact 16 and its corresponding probe. In order to minimize the distance between the capacitors C1 and DUTs, these capacitors should be mounted on the probe card 12 near (or above) the small central area 27. However, when the wafer contains a large number of ICs to be tested or 1C with a large number of densely packed terminals, there is not enough space to install the required number of capacitors C 1 sized sufficiently close to the central area 27. [Summary of the Invention] During the test of the integrated circuit device (DUT) in the test of synchronous logic, after each successive leading or trailing edge of the clock signal input to the DUT, the DUT will experience a temporary increase in power supply current demand When the transistor forming the logic device undergoes a state transition in response to the edge of the Risi pulse signal, the DUT will need additional current to charge the input capacitance of the crystal. (5) (5) 200302539 The present invention will limit the change in the power supply voltage of the DUT power input terminal caused by the transient increase in the power supply current after each clock signal pulse wave. Therefore, the present invention can reduce the power supply noise of the DUT power input terminal. . According to the present invention, the charging current pulse is supplied to the power input of the DUT after the edge of each clock signal, and during the test, the current continuously supplied by the main power supply is supplemented by the charging properly supplied by the auxiliary power supply The current pulse reduces the need for the main power supply to increase its output current to match the increased demand of the DUTs. Although the DUT's demand for increased current has a substantially constant output current from the main power supply, the voltage drop across the path impedance between the main power supply and the DUT will be substantially constant, so the DUT The supply voltage at the power input terminal will also remain substantially constant. After each clock signal edge, the amount of additional charging current required by the DUT will change based on the number and nature of state transitions experienced by its internal logic device to respond to the clock signal edge. Because the 1C test requires the 1C to perform a predetermined sequence of state changes, the behavior of the 1C during the test, including its current demand during the edges of each clock signal, is predictable. Therefore, the magnitude of the current pulse supplied after each clock signal edge can be adjusted to fit the predicted amount of additional charging current required by the DUT after each clock signal edge, and for each clock signal edge by the DUT The prediction of the increase in the induced current can be based on, for example, the measurement of the current caused by borrowing the same DUT under the same test conditions, or subjecting the analog DUT to similar tests. -10- (6) (6) 200302539 Although the amount of charging current that can be caused by a particular form of 1C can be predicted with considerable accuracy in any test cycle, the amount of additional charging current caused by a given DUT in that form The actual amount will be more or less than the predicted amount. In particular, changes in the random process in the manufacture of ICs will cause all ICs to behave slightly differently relative to the amount of charge current required by the transistors during the state change. To compensate for these differences between DUTs, a feedback circuit can be configured to monitor the voltage at the power supply terminal of the DUT and appropriately measure the predicted current pulse size in order to minimize the change in the voltage. Therefore, the magnitude of the current pulse supplied to the power input of the DUT after each clock signal cycle is a function of the predicted magnitude of the extra current caused by the form of DUT during the clock signal cycle, but the predicted pulse The wave size is measured by feedback so that the prediction can be adapted to adjust for changes in the charging current requirements of each particular DUT tested. The conclusion section of this specification specifically points out and explicitly claims the subject matter of the present invention. However, those who are familiar with this technology will better understand the organization and operation method of the present invention by reading the rest of the specification and attaching the same reference symbols with the same reference symbols. Advantages and purpose. [Embodiment] < System Architecture> Figure 5 depicts a block diagram of a 1C device connected to a group of semiconductor wafers in the same test through a probe card 32 in the form of a block diagram (-11-(7) (7) 200302539 DIJTs) 34 integrated circuit (IC) tester 30. The probe card 32 includes a set of probes 37 for accessing the input / output terminal pads 39 on the surface of the DUTs 34; and also includes a signal path 46 for connection testing. The detector 30 is at the probe 37 to allow the 1C tester 30 to transmit clock signals (CLOCK) and other test signals to the DUTs 34, and to pass the DUT output signals back to the tester, so that the tester can monitor the behavior of the DUTs. The probe card 32 also connects the main power supply to the power input terminal 41 of each DUT 34 via a conductor that is passed through the probe card to the probe 37 and extends to the terminal 41, and the power supply 36 produces a good The adjusted output voltage VA continuously supplies the current 12 to the DUT 34. For the purpose of illustration, Fig. 5 shows that the inherent impedance of the path 43 through the probe card 32 between the main power supply 36 and each DUT is the resistor R1. Due to the voltage drop across each resistor R1, the input supply voltage VB of each DUT34 is always slightly less than VA. According to the present invention, the first transistor switch SW1 mounted on the probe card 32 is connected to an auxiliary power supply 38 in a group of capacitors C2 installed in the probe card 32;-a second transistor switch SW2 also installed in the probe card 32 connects each capacitor C2 to the power input terminal of the corresponding DUT 34. The resistor R2 shown in FIG. 5 represents the inherent signal path impedance in the probe card 32 between each capacitor C1 and the power input terminal 41 of the DUT 34 when the switch SW2 is turned off. The 1C tester 30 provides an output control signal CN1 for SW1, a control signal CNT2 for controlling the switch SW2, and CNT3 for controlling the output voltage VC of the auxiliary power supply 38. As described in detail below, 'Auxiliary power supply 3 8, 8, -12- (8) 200302539 Switches SW1 and SW2, and capacitor C2 play an auxiliary power need to cooperate with any expected increase in the supply current required by the DUT in the 1C tester A current pulse 13 is injected into each rate input terminal 41 under the control of 30. < Power supply noise > DUTs 34 implement synchronous logic, in which the logic gates are turned on and off in response to the pulse of the weekly CLOCK signal provided by the tester 30. Each switching transistor is inherent and is designed to turn on or off. When the transistor is turned off, its driver must be charged with the input capacitance of the transistor. When the driver in DUTs 34 is charged with the input capacitance, it will increase the amount of current 11 that must be supplied to each DUT. When the input capacitance of the transistor is full, the charger only needs to supply the amount of leakage current required to keep the input capacitance of the transistor charged, so that the transistor remains on or off. After each pulse of the CLOCK signal, each DUT 34 is input. There will be a temporary increase in the current Π to provide the charging current required to change the different switching states. After the CLOCK signal is cycled, after the transistors have changed state, the power supply will generate a steady state level of static electricity and remain there until the beginning of the CLOCK signal cycle. Because the amount of DUT 34 external current II at the beginning of each CLOCK signal cycle will vary depending on the number and nature of the transistors that were turned off during that particular CLOCK signal cycle, the source of the charging current, when added, is the power of the DUT. When the main input capacitance of the switching transistor or the discharge transistor P ππ πϋ rate input terminal, its drive is quite small. Therefore, the slight current demand in the power supply transistor loop to the next required amount is turned on or the demand is variable -13- 200302539 〇) between cycles. If the tester 30-the straight holding switches SW1 and SW2 are turned on, the main power supply 36 will always provide all the current inputs II to each DUT 34. In this example, due to the increased switching action in each DUT 34 after each CLOCK signal pulse, the temporary increase in the supply current 11 will cause the inherent impedance of the signal path 43 between the main power supply 36 and the DUT 34 The temporary increase in the voltage drop across R 1 will then cause a temporary tilt in the voltage VB of the power input 41 of the DUT. Figure 2 represents the behavior of VB and II when SW2 is turned on. Because the slope in the supply voltage VB that occurs after the edge of each CLOCK signal pulse can adversely affect the noise form of the performance of the DUTs 34, it is desirable to limit the magnitude of the voltage slope. < Predictive current compensation > According to an embodiment of the present invention, the 1C tester 30 controls the states of the auxiliary power supply 38 and the switches SW1 and SW2, so that the capacitor C2 can supply additional charging current at the beginning of each test cycle. 13 to DUT 34. The charging current 13 flowing only during the initial part of each CLOCK signal cycle will combine the current 12 of the main power supply to provide a current input II to the DUT 34. When the charging current 13 provides approximately the same amount of charge as the capacitance of the switching transistor in the DUT 34 obtained after the CLOCK signal pulse, there is only a small change in the main power supply 3 after the CLOCK signal pulse. In the current 12 generated by 6, there is only a small change in the supply voltage VB. -14- (10) (10) 200302539 Therefore, before each CLOCK signal edge, the tester 30 will supply the data CNT3 to the auxiliary power supply 38 to indicate the desired auxiliary supply voltage VC and then close the switch SW1. Next, the power supply 38 charges all capacitors C2, and the amount of charge stored in the capacitor C2 is proportional to the magnitude of VC. When capacitor C2 has time to fully charge, tester 30 turns on switch SW1; after that, after the start of the next CLOCK signal cycle, tester 30 turns off all switches SW2, so that the charge stored in capacitor C2 can be regarded as flowing into DUTs The current 13 in 34; then, when it is considered that a transient charging current is needed, the tester 30 will turn on the switch SW2 so that only the main power supply 36 supplies current to the DUTs 34 during the remainder of the CLOCK signal cycle. This process will be repeated in the tester during each cycle of the CLOCK signal, and the size of VC is adjusted for each clock cycle via the control data CNT3 in order to provide a certain size current pulse wave 1C to satisfy the specific clock signal The predicted charge current demand during the cycle. Therefore, the magnitude of the 1C current pulse can vary between cycles. Figure 6 depicts the supply voltage VB and current II, 12 and 13 during the initial part of the CLOCK signal cycle. The current II is apparently behind the edge of the CLOCK pulse, and at time T1, a large temporary increase above its static level IQ1 to charge the capacitance in the DUT 34. The current 13 rises rapidly while providing substantially all additional charging current. The output current 12 of the main power supply 38 only shows a relatively small disturbance in its static 値 IQ2, and produces a small mismatch between the transient components of 13 and 12. Because the change in 12 is small, the change in VB is also small. Therefore, due to the switching transients in -15- (11) (11) 200302539 DUTs 34, the present invention can substantially limit the noise of the power supply. < Programming of the tester > As mentioned above, the amount of additional charging current generated by each DUT 34 at the beginning of the CLOCK signal cycle will depend on the number of transistors that are turned on or off during the CLOCK signal cycle. The current will change between cycles. In order to provide proper voltage adjustment at the DUT terminal 41, the tester 30 must predict how much charge DUT 34 will store after the edge of each CLOCK signal, because the tester must adjust the output VC of the auxiliary power supply so that capacitor C2 is at each The appropriate amount of charge is stored before the CLOCK signal is cycled. Figure 7 depicts a test system built to allow tester 30 to experimentally determine the VC level it should set during each test cycle. The well-known reference DUT 40 suitable for operation and similar to the ICs to be tested is connected to the tester 30 via the probe 32 in substantially the same manner as the DUTs 34 to be connected, so that the tester 30 can perform the same test on the reference IC 40 Moreover, the probe card 32 is also connected to the power supply terminal of the reference IC 40 to the input terminal of the tester 30, so that the tester 30 can monitor the power supply voltage VB. The tester 30 then uses the minimum VC to perform only the first CLOCK cycle of the test and observes VB. If VB falls below the desired lower limit during the CLOCK signal cycle, the tester 30 uses the higher VC of the VC to repeat the test The first CLOCK signal cycle is repeated, and this process is repeated until the proper VC of the first CLOCK signal cycle is established. Then -16- (12) (12) 200302539 after 'the tester repeatedly performed the first two CL0CK signal cycles of the test and monitored Vb during the second CLOCK signal cycle and adjusted VC accordingly, using the same procedure to The VCs that establish each successive CLOCK signal loop for this test are appropriate, and these VCs can be used when testing DUTs 34. Typically 'Designers will use circuit simulators to simulate ICs before ICs are manufactured.' When a circuit simulator performs the same tests as an ic tester would perform on its real counterparts on analog ICs, the circuit simulator can Used in a similar manner to determine the VC 値 sequence to be used during the test of this true 1C. < Probe Card > Figure 4 depicts a typical prior art probe card 12 which is connected to the power input terminals of the DUTs of the voltage adjustment capacitor C1 to limit power supply noise. These probe cards The distance between the voltage adjustment capacitors and the DUT must be minimized to minimize the impedance between these capacitors and the DUTs. Therefore, the capacitors are preferably installed in a probe card or near a small area 27 above the probes that access the DUTs. Because there is only a small space on the probe card near the probe, the size and number of adjustment capacitors C1 that can be deployed on the probe card 12 are limited. This limitation on the capacitor installation space can limit The number of DUTs tested. Fig. 8 is a simplified plan view of the probe card 32 according to Fig. 5 of the present invention. The contact points 45 reached by the 1C tester 30 of Fig. 7 are distributed on a relatively large surface 43 of the probe card 32. The probe 37 (not shown) that touches -17- (13) (13) 200302539 DUTs 34 is concentric below the relatively small central area 47 of the probe card. Because the voltage VC charged in the capacitor C2 can be adjusted to fit the effective path impedance R2 (Figure 5) between any switch SW2 and the DUT 34 terminal 41, the capacitor C2 can be located at a distance from the center area 47 above the DUT probe than in Figure 4 The capacitor c 1 is mounted on the probe card 32 at a greater distance; and because the capacitor C2 is charged to a higher voltage than the capacitor C1, the capacitor C2 can be smaller than the capacitor C1 because the probe card 32 in FIG. 8 The capacitor C2 can be smaller and further away from the center of the probe card than the capacitor C1 of the conventional probe card 12 of FIG. 4, so a large number of capacitors C2 can be installed on the probe card 32. Therefore, the test system using the probe card 32 according to the present invention can test more DUTs simultaneously than the test system using the conventional technique probe card 12 of FIG. 4. < Probe card with pattern generator on board > Figure 9 depicts an alternative embodiment of the present invention, including a probe card 50 that is substantially similar to the probe card 32 of Figure 7 except that it is already in its place. Installation on the outside, power control 1C 〃 52. The power control IC 52 includes a pattern generator 54. The pattern generator executes FIG. 7. The IC tester 30 generates control signals and data CNT1, CNT2, and CNT3 for controlling the switches SW1 and SW2 and the auxiliary power supply. 3 8 pattern generation function. The power control IC 52 includes a conventional pattern generator 54. Before the start of the test, the program planning is performed by using externally generated program planning data provided by the conventional computer bus 56. The pattern generator 54 begins to generate its output The data pattern responds to the START signal from the 1C tester 5 8 -18- (14) (14) 200302539 START signal, and the CNT1, CNT2, CNT3 data pattern that generates its output in response to the same as the tester 58 System clock (SYSCLK) operating the clock. As shown in Figure 9, when the required capacitor C2 is small enough, the switches SW1 and SW2 and the capacitor C2 can be implemented in the power control IC52. The IC52 should be installed on the probe card as close to the DUT probe as possible. Needle place. The pattern generation function of the coupling switches SW1 and SW2, the capacitor C2, and the tester 30 within a single IC52 can reduce the cost and complexity of the probe card 32, and reduce the required number of output channels of the tester 30, and as needed The capacitor C2 can be implemented outside the power control IC 52 by using discrete components. < Charge flow of pulse width modulation > Fig. 10 depicts an embodiment of the present invention, which is substantially similar to the embodiment of Fig. 5. However, in FIG. 10, the switch SW1 is omitted from the probe card 60, so that the VC output of the auxiliary power supply 38 is directly connected to the capacitor C2, and the output voltage VC is fixed and not adjusted by the 1C tester 30, so that C2 charges to the same level before each CLOCK signal pulse. In this configuration, the 1C detector 30 will use the pulse width modulation switch SW2 via the control signal CNT2 to control the charge amount of the capacitor C2 that is passed to the DUTs 34 at the beginning of each CLOCK pulse, and during the CLOCK signal pulse The amount of time after which the tester 30 turns off SW2 after the leading edge will determine the amount of charge on capacitor C2 passed to DUTs 34. Alternatively, when the tester 30 rapidly increases and then decreases the duty cycle of the CNT2 signal, as depicted by -19- (15) (15) 200302539 in Figure 11, it can be more closely approximated in Figure 6. Depicted 13 current flowing shapes. < Charge flow of analog modulation > Fig. 12 depicts an embodiment of the present invention, which is roughly similar to the embodiment of Fig. 10. However, in Figure 12, the transistor switch SW2 is replaced with a transistor Q2 operating in its active region when the DUTs 34 series undergo a state change and require additional current Π. In this configuration, the CNT2 output of the 1C tester 3◦ is applied as a data sequence input to the analog-to-digital (A / D) converter 63 installed on the probe card 61, and the data sequence CNT2 represents each CLOCK signal The demand for the charging current 13 is predicted during the cycle. The A / D converter 63 responds to the CNT2 data sequence by generating an analog signal CNT4 which varies during each CLOCK signal cycle and inputs it to the base of transistor Q2, as depicted in FIG. The analog signal CNT4 controls each transistor Q2 and allows the amount of current 13 flowing out of capacitor C2 to substantially match the predicted transient component of current II required by DUT34. The A / D converter 63 may be implemented in the 1C tester 30 instead of being mounted on the probe card 61. < Charge prediction using a reference DUT > Figure 14 depicts an embodiment of the present invention, in which a reference DUT60 of similar DUTs 34 is tested in a similar manner, except that the tester% tests the reference DUT60 by applying it to the reference. DUT60's CLOCK and other features enter the g5 Tiger Super while others are slightly beyond the other DUTs. Main power supply -20- (16) (16) 200302539 Device 62 supplies all DUTs 34 and auxiliary power supply 64 supplies reference DUT60 'Installed on probe card 66 Capacitor C4 near reference DUT60 Adjust voltage in a conventional manner VREF is at its power input 68, so that it stays within its permitted operating range. Capacitor C5 connects VREF to a group of amplifiers A1 'and capacitor C6 connects the output of each amplifier a1 to the power input of each DUT34. End 70. Due to the requirements of the reference DUT's transient charging current, through good adjustment, the supply voltage VREF at the input 68 of the reference DUT60 will fall below its static level after the start of each CLOCK signal cycle. The amount of voltage ramp in VREF is proportional to the amount of transient charging current generated by the reference DUT. Because the reference DUT is similar to DUTs 34 and the test is slightly ahead of DUTs 34, the slope in VREF can predict the amount of transient charging current of each DUT 34 after a short time. The amplifier A1 operated through the capacitors C5 and C6 can amplify the AC component of VREF to generate an output current 13 which can increase the current output 12 of the main power supply 62, and provide a current input II to each DUT 34. The amount of time that the tester 30 leads the reference DUT60 test is set equal to the delay between a change in the reference voltage VREF and a corresponding change in the current 13. With the (negative) gain of each amplifier A1 appropriately adjusted by the externally generated signal (GAIN), the current 13 will substantially match the transient charging current required by DUTs 34. < Charge prediction in a non-test environment) In addition to being effective in reducing power supply noise when testing integrated circuits-21-(17) (17) 200302539, embodiments of the present invention may also be used in integrated circuits Adopted in a series of applications with predictable status to reduce power supply noise. FIG. 15 depicts an example of the present invention, in which the integrated circuit 80 passes a predictable series of states in response to the edge of a CLOCK signal generated externally supplied there as an input, and the IC 80 receives power from the main power supply 82 The auxiliary power supply 84 charges the capacitor C2 via the switch SW1 when the switch SW1 is closed, and the capacitor C2 supplies its charge as an additional current input to the IC80 when the switch SW2 is closed. 'Charge predictor' During the period in which IC80 is a part of each CLOCK signal that is not changing state, the switch SW1 is closed by the request signal CNT1 and the switch is opened in response to the CLOCK signal without the control signal CNT2. This allows the auxiliary power supply The supplier 84 charges the capacitor C2 between state changes, and the charge prediction circuit 86 may request the control signal CNT2 to close the switch SW2 and open the switch SW1 without the control signal CNT1 during one of the 1C80 non-changing state of each of the CLOCK signal cycles In this way, the capacitor C2 circulates the current to the power input of the IC80 to provide its required transient current. The charge predictor circuit 86 also provides control data CNT2 to the auxiliary power supply 84 to adjust its output voltage VC so that it charges the capacitor C2 to a level determined based on the amount of current expected to be generated by 1C 80 during the next state change. The charge predictor 86 is suitable to be realized by a conventional pattern generator or any other device that can generate the transient current requirements applicable to IC80 for the output data sequences CNT1, CNT2 and CNT3 for its expected state sequence. The switches SW1 and SW2 can be implemented outside the 1C80 as depicted in Figure 15 or can be implemented inside the ic80. -22- (18) (18) 200302539 < Charge averaging method > Fig. 16 depicts a simple form of the present invention, which is applicable in which the amount of charging current generated by the IC80 at the beginning of each CLOCK · signal cycle is within a fairly limited and predictable range Application. As shown in FIG. 16, the inverter 90 inverts the CLOCK signal to provide a CNT1 control signal input to a switch SW1 that couples the auxiliary power supply to the capacitor C2. The CLOCK signal directly provides the CNT2 control signal input to a connection. The capacitor C2 is connected to the switch SW2 of the IC 80 power input generally driven by the main power supply 82. As shown in Figure 17, the CLOCK signal drives the CNT2 signal high during the first half of each CLOCK signal cycle to close the switch SW2, and drives the CNT1 signal high to close during the second half of each CLOCK signal cycle. Switch SW1. The output voltage VC of the auxiliary power supply 84 is set to a constant value, so that it charges the capacitor C2 to the same level before the start of each CLOCK signal cycle. The VC level is set to properly determine the range within which the power supply input voltage VB swings when 1C 80 is generating additional charging current at the beginning of each CLOCK signal cycle. For example, when we want to make the static level of VB at its In the middle of the range, we can adjust VC so that capacitor C2 can supply a current in the middle of the range of charging current expected by IC80. On the other hand, if we want to prevent VB from falling below the extreme level of its static level However, when it is willing to make VB rise above its static level, we can adjust VC so that capacitor C2 can supply a maximum amount of charging current that IC80 will be expected to generate. Although capacitor C2 can supply a very small charging current during several CLOCK signal cycles and (-23) (19) (19) 200302539, and a large charging current during other CLOCK signal cycles, in many applications, as shown in Figure 16 The system depicted can keep the VB swinging within an acceptable range when the VC is properly adjusted. It should be noted that the systems in Figures 5, 9, 14 and 15 can be programmed in the same way by setting the control data CNT3 of each CLOCK signal cycle to be the same. < Adaptive current compensation > Fig. 18 depicts another representative embodiment of the present invention. As shown in FIG. 18, the power supply 36 supplies power to the power input terminal 1 806 on the semiconductor device (DUT) 34 under test through the probe card 50, and passes through the power line 1 on the probe card 50. The inherent impedance of 8 1 2 is shown as R1 in Figure 18, and as shown in Figure 18, 1C tester 5 8 will provide the clock and other signals to DUT34 through the probe card. The clock input terminal on the ϋϋ34 is depicted as terminal 1 808. The 1C tester 58 also receives the signal from the DUT 34 through the probe card 50, and an input / output (1/1 / 〇) Sub 1810, however, DUT 34 may have additional I / O terminals 1810 or may have inputs dedicated to input only or other terminals dedicated to output only, or terminals dedicated only to input or output and other functions are Combination of input and output terminals. Obviously, the probe card 50 may be connected to a DUT as shown in FIG. 18 or a plurality of DUTs as shown in FIG. 14. As shown in FIG. 18, the current sensing device 1 804 (such as a current sensing coupler or a current transformer) can sense electricity through a bypass capacitor C 1 -24- (20) (20) 200302539 current ' The amplifier 1 802, which is preferably an inverting amplifier (for example, the amplifier has a negative gain of 1), can supply current into the transmission line 1812 through the capacitor C7, and the auxiliary power supply 38 provides power to the amplifier 1 802. Of course, other devices can be borrowed To supply power to the amplifier 1802, including power supply 36, 1C tester 58, power supply located on probe card 50, or in addition to the power supply 36, 1C tester 5 8 or probe card 50 Power supply set outside. In operation, as described above, the power terminal 1 806 typically generates a small current (assuming that the DUT 34 mainly contains a field effect transistor), and only in a few cases, the power terminal 1 806 generates a large amount of current. As described above, the most common cases occur when at least one transistor in the DUT 34 changes state, which typically occurs relative to the rising or falling edge of the clock at clock terminal 1 808. When the DUT 34 is not changing state, a small amount of current generated at power terminal 1 806 will only pass through the bypass capacitor C1 and will typically cause a small and mostly static direct current (DC) flow or no current flow. A small to zero current sensed by the current sensing device 1 804 is generated and thus the current from the inverting amplifier 1 802 will be small to zero. However, when the DUT 34 is changing state, as described above, the power terminal 1 806 will temporarily generate a large amount of current, which will generate a temporary large amount and change the flowing current through the bypass capacitor C 1 as described above. The current is sensed by the current sensing device 1 804 and inverted and amplified by the inverting amplifier 1 8 2, and is finally provided into the power line 1 8 1 2 through the isolation capacitor C 7. As described above, the additional current provided by the amplifier 1 8 02 to the power -25- (21) (21) 200302539 rate line 1 8 1 2 will reduce the change in voltage at the power terminal 1 8 0 $. FIG. 19 depicts a variation of the representative embodiment shown in FIG. 18. As shown in the figure, FIG. 19 is roughly similar to FIG. 8 and also includes a current sensing element 1 804 and an inverting amplifier 1802, configured to provide a current to the power line 1 on the probe card 50. 812. However, in FIG. 19, the electric current sensing element 1 804 will sense the current flowing through the power line 1 8 1 2 instead of the current flowing through the bypass capacitor C 1. The operation of the embodiment of Fig. 19 is similar to that of Fig. 18. When the DUT 34 is not changing state, the typical small static direct current (DC) generated by the power terminal 1 806 via the line 1 804 is sensed by the current sensing device 1 804. Therefore, the inverting amplifier 1 802 Provides small or no charge current. However, when the DUT 34 is changing state, the current sensing device 1 0 0 4 will sense a large current change through the power line 1 8 0 4 at the power terminal 1 8 0. The inverting amplifier 1 8 0 2 will amplify and reverse the sensed current and provide additional charging current to the power line 1 8 1 2 through the isolation capacitor C7. As mentioned above, this additional charging current will reduce the change in voltage at the power terminal 186. < Interconnection system> The probe card described in any one of the embodiments for providing a signal path between an integrated circuit tester, a power supply, and a DUT is representative. The present invention may be combined with Many other designs of interconnect systems are implemented. For example, Figure 20A depicts a fairly simple probe card, which contains a base plate-26- (22) (22) 200302539 2002, with a terminal 2004 for connection to a 1C test. Device (not shown in FIG. 20A) and a probe element 2008 for electrical connection to a DUT (not shown in FIG. 20A). As shown in the figure, the terminal 2004 is electrically connected to the probe card component 2008 through the interconnection component 2006. For example, the substrate may be a single or multilayer printed circuit board or ceramic or other material. Obviously, the material composition of the substrate is not important to the present invention. The probe element 2008 can be any type of probe that can be electrically connected to the DUT, including but not limited to needle probes, COBRA probes, bumps, columns, rods, spring contacts, and the like. An unrestricted example of a suitable spring contact is disclosed in U.S. Patent No. 54762 111, U.S. Patent Application No. 08/802054, filed February 18, 997, corresponding to PCT Publication No. W097 / 44676 , US Patent No. 6268015 B1, and US Patent Application No. 09/3 6485 5 corresponding to PCT Publication No. WO01 / 09952, filed on June 30, 1999, which will be incorporated herein by reference reference. These spring contacts can be considered as those in U.S. Patent No. 6 1 50 0 8 6 or 200 U.S. Patent Application No. 10/027476, filed December 21, 2001, which are also incorporated herein by reference. Described by. Alternatively, these ~ probes may be pads or terminals for contacting a raised element on the DUT such as a spring contact formed on the DUT. An unrestricted example of the interconnection path 2006 includes a combination of vias and / or vias and conductive traces on or within the substrate 2002. Figure 20B depicts another unrestricted example of a probe card that can be used in the present invention. As shown, a representative probe card shown in FIG. 20B includes a base plate 2018, an inserter 2012, and a probe head 2032. Terminal 2022 is in contact with -27- (23) (23) 200302539 1C tester (not shown in Figure 20B), and probe element 2034, which may be similar to the above-mentioned probe element 2008, is in contact with DUT (not shown in 20B Figure). The interconnection path 2020, the elastic connection element 2016, the interconnection path 2014, the elastic connection element 2010, and the interconnection path 2036 provide a conductive path from the terminal 2022 to the probe element 2034. The base plate 2018, the interposer 2012, and the probe head 2032 can be made of these materials similar to the above-mentioned related 2002. Indeed, the material composition of the substrate 2018, the interposer 2012, and the probe head 2032 is not essential to the present invention, and any composition may be used. The interconnection paths 2020, 2014, 2036 may be similar to the interconnection paths 2006 described above. The elastic connecting elements 2016 and 2010 are preferably elongated elastic elements, and unrestricted examples of these elements are depicted in US Patent No. 54762 111; US Patent Application No. 08 filed on February 18, 997 / 802054, which corresponds to PCT Publication No. WO 97/44676; U.S. Patent No. 6268015B1; and U.S. Patent Application No. WO 1/0995 2 filed on July 30, 1999 No. 09/364855, all of which are incorporated herein by reference. A more detailed description of a representative probe card including a plurality of substrates, such as the substrate shown in Figure 20B, is found in U.S. Patent No. 5,979,62, which is also incorporated herein by reference. Many variations of the representative design shown in FIG. 20B are possible. For example, for only one example, the interconnection path 2014 may be replaced with a hole and one or more fixed in the hole and extending to the hole. The outer elastic element 20 1 6 and / or 20 1 0 is in contact with the substrate 2018 and the probe card 2032. However, it should be understood that the architecture or design of the interconnected system is not essential to the present invention and any architecture or design may be used. As shown in the embodiments described herein, the circuit for reducing the change in voltage at the power terminals on the DUT is preferably configured on a probe card. If a multi-substrate probe card is used, Such as the representative probe shown in Figure 20B, the circuit can be located on any of these substrates, or it can be distributed among two or more of these substrates. So, for example, the circuit may be located on one of the probe head 2032, the interposer 2012, or the substrate 2018 depicted in FIG. 20B or the circuit may be located on the probe head, the interposer, and / or the substrate. A combination of two or more. It should be understood that the circuit may be integrally formed of interconnected discrete circuit elements, may be integrally formed on an integrated circuit, or may be composed of a part of the discrete circuit elements and a part of the integrated circuit. < Predictive / adaptive circuit compensation > As mentioned above, the predictive system for controlling changes in the supply voltage at the power input terminals of the DUT can predict the amount of charging current that the DUT will require during each clock signal cycle, and Then, based on the prediction, the magnitude of the supplementary current pulse applied to the power input terminal of the DUT is determined during the clock signal cycle; on the other hand, the adaptive system can monitor the power signal applied to the terminal of the DUT and utilize feedback. To adjust the size of the supplementary current pulse while maintaining the constant voltage of the power signal. Fig. 21 depicts an embodiment of the present invention in which the amount of additional charging current required at the power input terminal 26 of the DUT 34 is determined by a combination of prediction and adaptation. Auxiliary power supply 3 8 Supply power VC to electricity -29- (25) (25) 200302539 Current pulse generator 2102. When it is necessary to increase the normal supply current from the main power supply 36, the current pulse generator 2 1 02 will supply the current pulse 13 to the power input terminal 26 of the DUT. At the beginning of each test cycle, the 1C tester 58 will supply the signal CNT5 to the current pulse generator 2102 to indicate the predicted size of the current pulse, and during each test cycle, the 1C tester 58 will request a control signal CNT6 indicates when the current pulse wave generator 2102 generates a current pulse wave. The 1C tester 58 is a program designed to test a specific form of DUT 34, and the predictions made relative to the size and time period of the current pulse 13 during each test cycle can be generated as described above based on the form of the DUT. Measurement of current or simulation of DUT behavior. However, due to process variations in the manufacture of DUTs and other factors, the magnitude of the additional charging current required by each DUT of this type during each test cycle may vary from the predicted charging current. For any given DUT, the ratio of the actual charge current to the predicted charge current tends to be fairly consistent on a cycle-by-cycle basis. For example, a DUT can consistently produce a more than predicted charge during each test cycle. The charging current is 5% more, and another DUT at the same time consistently generates a charging current 5% less than the predicted charging current during each test cycle. The feedback controller 2104 compensates for these changes in the charging current requirement and prediction by supplying an adaptive gain (or > adaptive signal) signal G to the current pulse generator 2 102, which appropriately increases or decreases the current The size of the pulse 13 is such that the current pulse is suitable for the requirements of the particular DUT 34 in the current test. Therefore, the predicted signal CNT5 indicates the predicted size of the charging current required by the form -30- (26) (26) 200302539 DUT, and the gain (a adapted 〃) signal size indicates the specific situation of the DUT being tested Prediction error. Prior to testing the DUT 34, the 1C tester 58 performs a pre-test procedure that can be similar to the test to be performed, in which it transmits the test and CLOCK signal pulses to the DUT 34, making the DUT 34 behave substantially the same as it did during the test. During the pre-test procedure, the feedback control circuit 2104 monitors the voltage VB at the power input terminal 26 of the DUT and adjusts the magnitude of the gain signal G, so that changes occur in VB when the magnitude of 13 is too large or too small minimize. The pre-test procedure enables the feedback controller 2 104 to adjust the size of the gain signal G in a timely manner to meet the charging current demand of the specific Dim4 to be tested. After that, during the test, the feedback controller 2104 will continuously monitor VB And adjusting the gain signal, but the adjustments made are small. Therefore, although the size of the charging current 13 supplied during each test cycle is mainly a function of the predicted charging current demand of the DUT, the gain control feedback provided by the controller 2 04 will eventually adjust the current pulse size to The tendency to adapt to any consistency of the actual charging current demand of the DUT varies from the predicted demand. Those skilled in the art will understand that the feedback controller 2 1 04 in FIG. 21 can be any of many designs that can generate an output gain control signal G and minimize changes in VB. Those familiar with this technology will also understand that the current pulse generator can be any of many designs that can generate the current pulse 13, where the timing of 13 is controlled by the input signal CNT6, and the size of 13 is It is a function of the magnitude of the current pulse wave and the size of the adaptive gain signal G, which are represented by the control signal CNT5, -31-(27) (27) 200302539. FIG. 22 depicts a non-limiting example of the feedback controller 2 1 04, which integrates the AC component of VB to generate a gain control signal G. A DC blocking capacitor C10 passes the AC component of VB to an integrator 2106, which is an integrator. 2106 is formed by an operational amplifier A1 connected in parallel with a capacitor C8 and a resistor R5 and having a resistor R4 connected in series to its input. Fig. 23 depicts a non-limiting example of the current pulse generator 2106 of Fig. 21. In this example, the control signal CNT5 transmits data representing the predicted size of the required current pulse 13 and the digital-to-analog converter (DAC) 2 1 1 2 converts the predicted data of the current test cycle to be proportional to the size of the predicted data Analog signal P. When the 1C tester 58 requests the CNT6 signal and indicates when the current pulse 13 will be generated, the switch 2 1 1 0 will be closed to apply the signal P to the variable power supplied by the VC output of the auxiliary power supply 38 of FIG. 21 Gain amplifier 2 1 1 2 Input. The gain control signal output of the feedback controller 2104 in Figure 21 will control the gain of the amplifier 2112. The amplifier 2 11 2 will generate an output current pulse 13 that is proportional to the product of P and G. The capacitor C7 passes the 13 signal. The pulse wave transmits the signal path from the probe card 50 in FIG. 21 to the DUT 34. Fig. 24 depicts another non-limiting example of the current pulse generator 2106 of Fig. 21. In this example, the 1C tester 58 in FIG. 21 requires that the time length of the CNT5 control signal is proportional to the predicted size of the current pulse 13 required during the next CLOCK signal cycle, in the current pulse generator 2102. After each pulse of 13 signals is generated, the 1C tester 58 will request the CNT5 signal to be closed and coupled to the auxiliary power supply via the resistor. -32- (28) (28) 200302539 Output signal VC to switch 2116 of capacitor C8, 1C test The device 58 continuously requires the CNT5 signal for an amount of time. The amount of time will increase with the predicted size of the next 13 signal pulses. Therefore, the auxiliary power supply 3 in FIG. 21 3 The charging capacitor C8 is proportional to one A voltage of the predicted magnitude of a 13-signal pulse. After that, when the 1C tester 58 requests the CNT6 signal to indicate that the next 13 signal pulse will be generated, the switch 2117 will connect the capacitor C8 to a gain control signal output G having a feedback controller 2 1 04 as shown in FIG. 21 Input of the controlled gain amplifier 2 11 8. Coupling capacitor C9 transmits the 13 signal generated to the probe card conductor 2114 of DUT35 in Figure 21, and after capacitor C8 has been substantially discharged in time, the control signal CNT6 turns on switch 2117. Because the magnitude of the 13 current pulse rises rapidly and then tilts when C8 is discharged, the time-varying behavior of the 13 pulse is easy to match the charge current demand of the DUT time. Figure 25 depicts the current pulse in Figure 21. Another non-limiting example of the generator 2106, in which the data transmitted by the CNT5 signal represents the predicted size of the 13-signal pulse wave, and the gain control signal G acts as a reference voltage for the DAC 2120 that converts the data transmitted by the CNT5 into an analog signal P, gain The voltage scale of the control signal G will define the range of the DAC output signal P such that P is proportional to the product of G and CNT5. The switch 2122 will temporarily pass the P signal to the amplifier 2124 in response to the pulse of the control signal CNT6, thereby causing the amplifier 2125 to transmit a 13-signal pulse to the power conductor 2 1 1 4 via the coupling capacitor C5. The size of the 13-signal pulse is Will be proportional to the product of G and P sizes. -33- (29) (29) 200302539 Figure 26 depicts a still undefined example of a predictive / adaptive system according to the present invention, in which an auxiliary power supply 38 supplies power to a variable gain amplifier 2126, regardless of When the 1C tester 58 predicts that additional charging current will be required at the power input terminal 26 of the DUT 34, it will supply the control signal pulse wave CNT6 to the amplifier 2126. The capacitor C11 transmits 13 signal pulses to the power signal path 2 11 4 in the probe card 50 connected to the power supply 36 to the DUT power input terminal 26, and the feedback control circuit 2 1 04 will monitor the voltage VB appearing at the terminal 26 And adjust the gain of the amplifier 2126 to minimize the change in VB. At the beginning of each CLOCK cycle, the 1C tester 58 will supply the control signal CNT5 as an input to the auxiliary power supply 38 to set its output voltage VC according to the size of the data transmitted by the CNT5 control signal. Therefore, the magnitude of 13 is a function of the product of the gain control signal G and the magnitude of the auxiliary power supply voltage VC. Therefore, Figures 21 to 26 depict the power input terminal 26 for providing additional charging current to the DUT after each edge of the CLOCK signal in accordance with the present invention to match the temporaryness required by the initial switch due to the edge of the CLOCK signal A different representative embodiment of a predictive / adaptive control system that adjusts the voltage of the power signal VB applied to the DUT 34 with an increase in current. The control system is v 'predictive chirp, which predicts the amount of additional current that the DUT will require during each cycle of the test; the control system is also an adaptive chirp, which uses feedback to determine the resulting response to the forecast. The magnitude of the current pulse is adapted to the observed changes in the magnitude of the current actually produced by the individual DUTs to be tested. Although the present invention is depicted herein as reducing noise in a system employing only a single main power supply -34- (30) (30) 200302539, it will be understood that the present invention can be applied to more than one main The power supply provides power in the environment of DUTs. Although the present invention is depicted as operating in conjunction with DUTs having a single power input, it will be understood that the device may be adapted to operate in conjunction with DUTs having multiple power inputs. Although the present invention is described as providing additional charging current after the leading edge of the CLOCK signal pulse, it can also provide additional charging current after the trailing edge of the CLOCK signal pulse for use in the switch of the trailing edge of the CLOCK signal. DUTs. Although the present invention has been described as being used in combination with a 1C tester that uses probe cards to access ICs terminals formed on a semiconductor wafer, those skilled in the art will understand that the present invention can be used in combination 1C tester uses other forms of interface equipment to provide DUT terminals for ICs that are still at wafer level, or DUT terminals that can be separated from ICs on the wafers they form; Will be combined with DUT terminals of packaged ICs at the time of its test. Such interface equipment includes, but is not limited to, load boards, burn-in boards, and final test boards. The invention in its broadest form is not intended to be limited to applications involving any particular form of 1C tester, any particular form of tester-to-DUT interconnect system, or any particular form of IC DUT. Those skilled in the art will also understand that although the invention described above uses the test integrated with integrated circuits, it can also be used when testing any kind of electronic device, such as Including flip-flop combinations, circuit boards and the like, or whenever you want to precisely adjust the -35- (31) (31) 200302539 voltage at the power input terminal of the device during the test. Therefore, although the above-mentioned specifications have described the preferred embodiments of the present invention, those skilled in the art can accomplish many modifications to these embodiments without departing from the present invention in its broader form. Therefore, the appended patent application scope is intended to cover all such amendments as included within the true scope and spirit of the invention. [Brief description of the drawings] Figure 1 is a block diagram depicting a typical conventional technology testing system for a integrated circuit tester including a integrated circuit device (DUTs) under test connected to a set of probes through a probe card; Figure 3 is a timing diagram depicting the signal behavior in the conventional technology of Figure 1; Figure 4 is a simplified plan view of the conventional technology probe card of Figure 1; Figure 5 is a block diagram depicting The test system of the first embodiment of the invention, wherein a system for reducing noise in the power supply input of a group of DUTs is implemented; FIG. 6 is a timing chart depicting signal behavior in the test system of FIG. 5; Figure 8 is a block diagram depicting the operation of the test system of Figure 5 during the calibration procedure; Figure 8 is a simplified plan view of the probe card of Figure 6; Figures 9 and 10 are block diagrams depicting the second implementation of the invention And the third embodiment of the test system; -36- (32) (32) 200302539 Fig. 11 is a timing chart depicting signal behavior in the test system of Fig. 10, and Fig. 12 is a block diagram depicting implementing the present invention The test system of the fourth embodiment; Sequence diagram 'depicts the signal behavior in the test system shown in Figures 12 and 12. Figure 14 is a block diagram depicting a fifth embodiment of the present invention; Figure 15 is a block diagram depicting a sixth embodiment of the present invention; Figure 16 is a block diagram depicting a seventh embodiment of the present invention; Figure 17 is a timing diagram depicting signal behavior within the circuit of Figure 16; Figure 18 is a block diagram depicting an eighth embodiment of the present invention; Example; Figure 19 is a block diagram depicting a ninth embodiment of the present invention; Figure 20A depicts a representative probe card; Figure 20B depicts another representative probe card; Figure 2 1 Figure 22 is a block diagram depicting a tenth embodiment of the present invention; Figure 22 is a block diagram depicting a representative embodiment of the feedback control circuit of Figure 21; Figures 23 to 25 are block diagrams depicting a 21st embodiment The representative representative embodiment of the current pulse generator is shown in the figure; and the table 26 is a block diagram depicting the eleventh embodiment of the present invention. [Comparison Table of Main Components] 10, 30, 38 1C Tester-37- (33) (33) 200302539 12, 32, 50, 60, 61, 66 Probe Cards 14, 34, 35 Devices under Test (DUTs) 15 Spring pins 16 Contacts 1 8, 3 7 Probes 19, 39, 1810, 1 808 Input / output (I / O) pads 20 Conductive paths 22, 43 Path impedances 24, 36, 62, 82 Main power supply 26, 41, 68, 1806 Power input terminals 28, 46 Signal path 25 Upper surface 27, 47 Center area 38, 84 Auxiliary power supply 40 Reference DUT (reference 1C) 45 Contact point

5 2 Power control 1C 54 Pattern generator 56 Computer bus 63 Analog to digital (A / D) converter 80 Integrated circuit 86 Charge predictor circuit 90 Inverter 1812 Transmission line -38- (34) (34) 200302539 1 804 Current sensing device 1802, 2112, 2118, 2124, 2125, 2126 Amplifier 2002, 2018 Substrate 2008 Probe 2004, 2022 Terminal 2006, 2020 Interconnect path 2 012 Inserter 203 2 Probe head 2034 Probe element 2010, 2016 Flexible connection element 2014, 2036 Interconnection path 2102 Current pulse generator 2104 Feedback controller 2114 Power signal path 2 1 1 6, 2 1 1 7, 2 1 1 0 Switch 2120 DAC (digital to analog converter) G gain Control signal CNT1 ~ CNT6 Control signal 210 6 Integrator-39-

Claims (1)

(1) (1) 200302539 Patent application scope 1. A device for supplying current to a semiconductor device by using an integrated circuit tester during a semiconductor device test. The integrated circuit tester accesses the input of the semiconductor device through an interface device / Output (I / O) terminal, the interface device provides a signal path between the I / O terminals and the integrated circuit tester, wherein the semiconductor device includes a power input terminal for providing through the interface device A power conductor receives a supply current, and the semiconductor device temporarily increases its demand for a supply current after applying the edges of a group of edges of a clock signal input to the semiconductor device, the supply current to the semiconductor device The device is characterized by: a first device for supplying a first current to the power input terminal during the test; a second device for supplying a supplementary first after the edges of the clock signal The current pulse wave of the current reaches the power input terminal. The magnitude of the current pulse wave is shown by a predicted signal and an adaptive signal. A function of the size shown; and a third device for adjusting the size represented by the adaptive signal in response to the voltage presented at the power input terminal, where the size represented by the predicted signal is set proportional to a predicted With this predicted amount, the semiconductor device can increase the current demand at its power input terminal after the next such clock edge. 2. For a device that supplies current to a semiconductor device as described in the first patent application, wherein the integrated circuit tester generates the predicted signal. 3 · If the current in the scope of the patent application is 1 to supply the current to the -40 of the semiconductor device-(2) (2) 200302539 device, wherein the magnitude of the current pulse is proportional to the predicted signal and the signal indicated by the adaptation signal. Product of sizes. 4. For a device that supplies current to a semiconductor device as described in item 1 of the patent application range, wherein the magnitude represented by the adaptation signal is a function of the voltage of the time-varying portion of the time integral at the power input terminal location. 5. The device for supplying current to a semiconductor device, such as the item 4 of the scope of patent application, wherein the third device includes: a device for filtering, filtering the voltage presented at the power input terminal to produce a proportion proportional to that presented in the A filtering voltage of varying magnitude in the magnitude of the voltage at the power input terminal; and a device for integration that integrates the filtered voltage to generate the adaptation signal. 6. A device that supplies a current to a semiconductor device as described in the first patent application range. Wherein the second device comprises: a digital-to-analog converter for receiving the prediction signal and for generating an analog signal proportional to the size represented by the prediction signal; an amplifier having a control by the adaptation signal A gain; a device for temporarily applying the analog signal as an input to the amplifier after each of the clock signal edges, so that the amplifier generates a current pulse wave after each of the clock signal edges, wherein the current pulse wave The magnitude is a function of the magnitude of the analog signal and the magnitude represented by the adaptation signal. 7. The device for supplying electric current to the semiconductor device as described in the first patent application scope, wherein the second device includes: an amplifier; -41-(3) (3) 200302539 in response to the prediction signal and the adaptation signal for Means for generating an analog signal having a magnitude that is a function of the magnitudes represented by the predicted signal and the adaptive signal; and for temporarily applying the analog signal after the edges of the clock signals The input device of the amplifier makes the amplifier generate a current pulse wave after each edge of the clock signal, wherein the magnitude of the current pulse wave is a function of the magnitude of the analog signal. 8. The device for supplying current to a semiconductor device as claimed in item 1 of the patent application scope, wherein the second device includes: an amplifier having a gain controlled by the adaptation signal; a capacitor; Means for charging the capacitor to a capacitor voltage before each of the clock signal edges, the capacitor voltage being a function of the magnitude represented by the predicted signal; and for temporarily connecting the capacitor after each of the clock signal edges is The input device of the amplifier causes the amplifier to generate a current pulse wave after each edge of the clock signals, wherein the magnitude of the current pulse wave is a function of the magnitude of the capacitor voltage and the magnitude represented by the adaptive signal. 9. The device for supplying a current to a semiconductor device as described in the first patent application scope, wherein the second device includes: a power supply that generates a voltage output signal as a function of the magnitude represented by the predicted signal; an amplifier, Powered by the output signal of the power supply and having a gain controlled by the adaptation signal; and -42-(4) (4) 200302539 for temporarily applying an analogy after each of these clock signal edges The signal is an input device of the amplifier, so that the amplifier generates a current pulse wave after each of the clock signals, wherein the magnitude of the current pulse wave is the voltage of the output signal of the power supply and the adaptation signal A function of that size. 10. The device for supplying electric current to a semiconductor device according to item 1 of the patent application scope, wherein the interface device includes a probe card, and wherein the second device is mounted on the probe card. 1 1 · The device for supplying electric current to a semiconductor device according to item 1 of the patent application range, wherein the interface device includes a probe card, and wherein the third device is mounted on the probe card. 12. The device for supplying current to a semiconductor device according to item 1 of the scope of the patent application, wherein the feedback provided by the third device can adjust the size indicated by the adaptation signal so that the voltage presented at the power input terminal Minimize changes. 1 3 · If the device for supplying current to a semiconductor device according to item 1 of the patent application scope, wherein the integrated circuit tester generates the predicted signal, wherein the magnitude of the current pulse is proportional to the predicted signal and the adaptive signal. The product of the sizes indicated, and the feedback provided by the third device can adjust the size represented by the adaptation signal to minimize variations in the voltage presented at the power input terminal. 14. The device for supplying electric current to a semiconductor device according to item 13 of the scope of patent application, wherein the interface device includes a probe card, and wherein the second (5) (5) 200302539 and the third device are mounted on the probe Above the board. 1 5 · —A method for testing a supply current to a semiconductor device by using an integrated circuit during a semiconductor device test. The integrated circuit tester accesses an input / output (I / O) terminal of the semiconductor device through an interface device. The interface The device provides a signal path between the I / O terminals and the integrated circuit test. The semiconductor device includes a power input terminal for receiving a supply current through a power conductor provided by the interface device, and the semiconductor. The device temporarily increases its demand for supply current after applying the edges of a set of edges of a clock signal input to the semiconductor device. The method includes the following steps: (a) supplying a first current during the test To the power input terminal b) to generate a predicted signal that is proportional to the magnitude of a predicted amount, by which the semiconductor device can be behind one of the edges of the clock signal, and then increase the current demand at its power input terminal C) generating an adaptation signal representing a magnitude determined in response to the voltage present at the power input terminal And d) supplying a current pulse to the power input terminal after each edge of the edges of the clock signals to supplement the first current, wherein the magnitude of the current pulse is a function of the magnitude represented by the predicted signal and the adaptive signal . 16. The method according to item 15 of the scope of patent application, wherein the integrated circuit tester performs step b. 17. The method according to item 15 of the scope of patent application, wherein the magnitude of the current pulse is proportional to the product of the large -44-(6) (6) 200302539 represented by the predicted signal and the adaptive signal. 1 8. The method according to item 5 of the scope of the patent application, wherein the magnitude represented by the adaptation signal is a function of the voltage of the time-varying portion of the time integral at the power input terminal location. 19 · The method according to item 18 of the scope of patent application, wherein step c includes the following ancillary steps: c 1) Filtering the voltage presented at the power input terminal to generate a proportion proportional to the voltage presented at the power input terminal A filtered voltage of varying magnitude; and c2) integrating the filtered voltage to generate the adaptation signal. 20. The method according to item 15 of the patent application scope, wherein step d comprises the following subsidiary steps: dl) generating an analog signal in response to the prediction signal, the size of the analog signal being proportional to the size represented by the prediction signal; And d2) temporarily applying the analog signal as an input of an amplifier after each of the clock signal edges, so that the amplifier generates a current pulse wave after each of the clock signal edges, wherein the magnitude of the current pulse wave is A function of the magnitude of the analog signal and the magnitude represented by the adaptation signal. 2 1. The method according to item 15 of the patent application scope, wherein step d includes the following auxiliary steps: d 1) generating an analog signal in response to the predicted signal and the adaptation signal, the analog signal has a size, the size is The predicted signal and the functions of the magnitudes represented by the adaptation signal; and d2) temporarily applying the analog signal (7) (7) 200302539 as the input of the amplifier after each of the clock signal edges, so that the amplifier is in A current pulse is generated after each of the clock signal edges, where the magnitude of the current pulse is a function of the magnitude of the analog signal. 2 2. The method according to item 15 of the patent application scope, wherein step d includes the following ancillary steps: dl) charging a capacitor to a capacitor voltage before responding to each of the clock signal edges in response to the predicted signal, the capacitor voltage Is a function of the magnitude represented by the predicted signal; and d2) the capacitor is temporarily connected as an input of the amplifier after each of the clock signal edges, so that the amplifier generates a current pulse after each of the clock signal edges The magnitude of the current pulse is a function of the magnitude of the capacitor voltage and the magnitude represented by the adaptation signal. 23. The method according to item 15 of the patent application, wherein step d includes the following auxiliary steps: dl) responding to the prediction signal by generating a voltage output signal, the voltage output signal being a function of the magnitude represented by the prediction signal; d2) responding to the adaptation signal by adjusting the gain of an amplifier powered by the output signal generated in step d1; and d3) temporarily applying a signal pulse to the amplifier after each of the clock signal edges The input causes the amplifier to generate a current pulse wave in response to each signal pulse wave, wherein the magnitude of the current pulse wave is a function of the voltage of the output signal and the magnitude represented by the adaptation signal. 24. The method as described in item 15 of the scope of patent application, wherein the size represented by the adaptation signal is borrowed for adjustment so that the power present at the input terminal of the power -46-(8) (8) 200302539 The change in voltage is minimal. 25 · —A method for reducing the change in the voltage supplied to the power input terminals of the semiconductor device under test, used in a semiconductor test system including a probe card and a supplemental current source, the method includes the following steps: provided through the probe card Power to the power input terminal of the semiconductor device under test; providing an input signal to the supplementary current source, the input signal being responsive to a temporary change in current generated by the input terminal of the semiconductor device; and from the supplementary current source A supplementary current is provided to the input terminal in response to the input signal. 26. The method of claim 25, further comprising changing the state of the semiconductor device, which causes the temporary change in the current generated by the input terminal of the semiconductor device. 27. The method of claim 25, further comprising sensing a change in a current generated by the input terminal of the semiconductor device. 28. The method of claim 27, wherein the sensing a change in the current generated by the input terminal includes sensing a change in the current through a bypass capacitor electrically connected to the power input terminal. 29. The method of claim 27 in the scope of patent application, wherein the sensing of a change in the current generated by the input terminal includes transmitting a conductive path electrically connected to the power input terminal on the probe card for sensing The change in current 〇30. The method of item 25 of the patent application range, wherein the amount of the supplementary current -47-200302539 0) corresponds to the amount of current generated by the input terminal. 3 1. The method of claim 25, wherein the supplementary current source includes an amplifier. 32. The method of claim 25, wherein the supplementary current is provided to the input terminal through a capacitor. 33. The method of claim 25, wherein the supplementary current source is disposed on the probe card. 34. The method of claim 25, wherein the probe card includes a plurality of interconnected substrates. 35. The method of claim 34, wherein the plurality of interconnected substrates include a probe head. 36. The method of claim 35, wherein the supplementary current source is disposed on the probe head. 37. The method of claim 25, further comprising allocating at least one leading signal to a reference device. 38. The method according to item 37 of the scope of patent application, wherein the input signal of the supplemental current source corresponds to the amount of current generated by the reference device 'in response to the at least one leading signal. 39. The method of claim 25, wherein the providing power further comprises providing power through the probe card to a power input λ terminal of each of the plurality of semiconductor devices under test; providing an input signal to the supplementary current source The method further includes providing an input signal to each of the plurality of supplementary current sources. Each of the input signals corresponds to a current generated by an input terminal of one of the semiconductor devices; and -48-(10) (10) 200302539. It further includes supplying supplementary current from each of the supplementary current sources & to the input terminals in response to the input signals. 40. A test device for a semiconductor device, including a power input terminal and a signal terminal, the test device includes: a probe card including a conductive connection structure for contacting the power input A terminal and the signal terminals; and The supplementary current source has an output and is electrically connected to the connection structure for contacting the power input terminal. One of the supplementary current sources is electrically connected to a signal corresponding to one of the signal terminals. A change in the current generated by the power input terminal caused by a change in the signal ', wherein the supplementary current source provides supplemental current to the power input terminal in response to a change in the current generated by the power input terminal. 4 1 · If the testing device under item 40 of the patent application scope further includes a current sensing device configured to sense a change in the current generated by the power input terminal, the current sensing device provides a corresponding signal to the This input supplements the current source. 42. The testing device of claim 41, wherein the current sensing device comprises a current sensing coupler. 4 3 · The test device according to item 41 of the scope of patent application, wherein the current sensing device includes a current converter. 4 4. The test type I device according to item 41 of the scope of patent application, wherein the electric sensing device is configured to sense a change in current through a bypass capacitor electrically connected to the power input terminal. 4 5 · If the test § type device of the scope of patent application No. 41, 'where the electric power -49-(11) (11) 200302539, the sensing device is configured to be electrically connected to the power input through a probe card The conductive path of the terminal senses a change in current. 46. The testing device of claim 40, wherein the supplementary current source includes an amplifier. 47. The testing device of claim 40, wherein the output of the supplemental current source is electrically connected to the power input terminal through a capacitor. 48. The testing device according to claim 40, wherein the supplementary current source is arranged on the probe card. 49. The testing device of claim 48, wherein the probe card includes a plurality of interconnected substrates. 50. The testing device of claim 49, wherein the plurality of interconnected substrates include a probe head. 5 1 · The test device according to item 50 of the scope of patent application, wherein the supplementary current source is arranged on the probe head. 52. If the test device under the scope of patent application No. 40 further includes a reference device, a power input terminal of the reference device is electrically connected to the input of the supplementary power supply device. 53. If the test device of the scope of application for a patent No. 52, further includes a tester 'electrically connected to the probe card, the tester is configured to change a signal provided to the reference device and then change a supply to the semiconductor Similar signals for devices. 54. The test device of claim 40, wherein the test device tests a plurality of semiconductor devices. -50-(12) (12) 200302539 5 5. The test device according to item 54 of the patent application scope, wherein the probe card provides power to the input terminals of each of the plurality of semiconductor devices. 56. A test device for a semiconductor device, comprising a power input terminal and a signal terminal, the test device comprising: a probe device for supplying power to the input terminal and providing a signal to at least one of the signal terminals; and a supplement A current device for supplying supplementary current to the power input terminal in response to a change in the current generated by the power input terminal caused by a change in a signal on one of the signal terminals. The supplementary current device has an input and a The output is electrically connected to a signal corresponding to a change in the current generated by the power input terminal, and the output is electrically connected to the power input terminal. 57. If the testing device under the scope of patent application No. 56 further includes a current sensing device for sensing a change in the current generated by the power input terminal, the current sensing device provides a corresponding signal to the supplemental current device That input. 58. The testing device of claim 56 in which the supplementary current device includes an amplifier. 59. The testing device according to item 56 of the application, wherein the output of the supplementary current device is electrically connected to the power input terminal through a capacitor. 60. The testing device of claim 56 in which the supplementary current device is disposed on the probe device. 61. The test device according to item 56 of the patent application scope, wherein the test -51-(13) 200302539 device tests a plurality of semiconductor devices. 62. The test device of claim 61, wherein the probe device provides power to input terminals of each of the plurality of semiconductor devices. -52-