TWI707356B - Method of checking memory operating conditions - Google Patents

Abstract

A method for checking memory operating conditions is implemented by a memory operating condition checking device, which enables the central processing unit (CPU) on the motherboard to be installed on several memory modules (device under test, DUT) input voltage (VDD, VDDQ and VPP) supply terminals of the measurement unit feedback voltage measurement value, can more accurately adjust the correct supply voltage to each memory module under test, so that the central processing unit can play The highest efficiency. The three operating voltages of VDD, VDDQ and VPP solve the problem of memory power supply voltage deviation, so that the correct supply voltage input to each memory module under test can be accurately adjusted during mass production testing. , In order to achieve consistent correction.

Description

Method of checking memory operating conditions

The present invention relates to a method for checking the operating conditions of a memory, in particular to a The three operating voltages of VDD, VDDQ and VPP solve the problem of memory power supply voltage deviation, which can more accurately adjust the correct supply voltage to each memory module under test, so that the central processing unit can exert the highest efficiency, especially the energy During mass production testing, the correct supply voltage input to each memory module under test can be accurately adjusted to achieve a consistent calibrator.

Such as a dynamic random access memory (dynamic random access memory, DRAM) is a semiconductor device in which the memory die can be mounted on a motherboard and receive a power supply from a central processing unit (CPU), which can transmit the externally supplied power to a power source The power management circuit (PMC) manages the power supplied to the components of the memory system. Power can be supplied to different components at different voltages and with different current needs. Among them, the power supply terminals VDD and VDDQ on the motherboard are usually the same value (1.2 V), and in general use, VDDQ and VDD are combined into one power supply.

However, due to the influence from program changes, the load voltage at the end, etc., the power supply The voltage may deviate from the value set by the pulse width modulation (PWM) unit in the power management circuit.

In view of the fact that the electric power output from the power management circuit terminal reaches the memory This section of the path received by the terminal will produce an unavoidable voltage deviation, which will actually reach the value of the memory terminal Unknown, the existing technology does not measure this. Even if the PWM itself generates the feedback voltage, it can only know the set value that was just output, but the memory reception value at the end has been affected. It has been deviated by the end load voltage during operation, so it is impossible to accurately know the power consumption of each memory.

Therefore, for the conventional skills, the output from the power management circuit to the memory input The voltage value is measured to compensate for the lack of power supply voltage deviation. Therefore, the general user is unable to accurately adjust the correct voltage value input to each memory terminal during actual use to achieve a consistent calibration. need.

The main purpose of the present invention is to overcome the above-mentioned problems encountered by conventional techniques and to provide Provides a more precise adjustment to provide the correct supply voltage for each memory module under test, so that the central processing unit can exert the highest efficiency. With the three operating voltages of VDD, VDDQ and VPP, the problem of memory power supply voltage deviation is solved, During the mass production test, the correct supply voltage input to each memory module under test can be accurately adjusted to achieve a consistent calibration method for checking memory operating conditions.

Another object of the present invention is to provide a reference circuit which can accurately monitor the operation. Voltage (VREF) and other parameters, by quickly changing the operating conditions, you can quickly change the basic input and output system (Basic Input and Output System, BIOS) frequency and delay time (CAS latency, CL) settings, which can effectively perform under various conditions The operating ability test of the memory operating condition inspection method.

In order to achieve the above objectives, the present invention is a method for checking the operating conditions of the memory. The method includes the following steps: Step 1: Provide several original supply voltages to several memory modules under test (device under test) via a power management integrated circuit (PMIC) , DUT), where each memory module under test is installed on a motherboard and connected to the power management chip. Each memory module under test includes a first input voltage (VDD) supply terminal, a first Two input voltage (VDDQ) supply terminals and a third input voltage (VPP) supply terminal, each of the original supply voltages is input to the first to third input voltage supply terminals of each memory module under test, and each The original supply voltage includes VDD, VDDQ, and VPP; Step 2: Enable a measurement unit coupled to the first to third input voltage supply terminals of each memory module under test, wherein each measurement unit includes a coupling A first measurement element connected to the first input voltage supply terminal, a second measurement element coupled to the second input voltage supply terminal, and a third measurement element coupled to the third input voltage supply terminal Measuring components; Step 3: Use each of the measurement units to measure the input voltage and current of the first to third input voltage supply terminals of each of the memory modules under test to generate the corresponding current supply voltage and feed it back to a center Processing unit (central processing unit, CPU); Step 4: The central processing unit compares each current supply voltage fed back by each measurement unit with each original supply voltage, and generates a corresponding compensation voltage according to the comparison result And Step 5: For the memory module to be tested related to the compensation voltage, the central processing unit controls the power management chip to provide the compensation voltage to the corresponding memory module to be tested for compensation, thereby being able to accurately adjust Input the correct supply voltage to each end of the memory module under test.

In the above embodiment of the present invention, the central processing unit is connected to each of the memory to be tested respectively The body module, the power management chip and each of the measurement units are connected, and the power management chip is connected with each of the memory modules to be tested.

In the above embodiment of the present invention, the central processing unit has a built-in storage element, which can Through software, the power management chip controls the original supply voltage provided to each memory module under test, and provides the compensation voltage to the corresponding memory module under test.

In the foregoing embodiment of the present invention, each of the measurement units is a digital multimeter (digital multimeter, DMM).

In the above-mentioned embodiment of the present invention, the first to third measuring elements are respectively applied with a resistance The value measurement corresponds to the input voltage and current of the coupled first to third input voltage supply terminals, and generates the corresponding current supply voltage according to the change of the intermediate bias voltage of the resistance value.

In the above embodiment of the present invention, the resistance value is 8-12 milliohms (mΩ).

Please refer to "Figure 1 and Figure 2", which are schematic diagrams of the process of the present invention, And the block diagram of the present invention. As shown in the figure: The present invention is a method for checking memory operating conditions, implemented by a memory operating condition checking device, which includes several memory modules under test (device under test, DUT) 1. A power management chip (Power management integrated circuit, PMIC) 2, a number of measurement units 3 and a central processing unit (central processing unit, CPU) 4. The method for checking memory operating conditions includes the following steps: Step one s1: Provide a number of original supply voltages to a number of memory modules 1 under test through the power management chip 2, where each memory module 1 under test is installed on a motherboard and is connected to the power management chip 2 connection, each memory module 1 under test includes a first input voltage (VDD) supply terminal 11, a second input voltage (VDDQ) supply terminal 12, and a third input voltage (VPP) supply terminal 13, Each of the original supply voltages is input to the first to third input voltage supply terminals 11-13 of each of the memory modules 1 under test, and each of the original supply voltages includes VDD, VDDQ, and VPP. Step two s2: enable each of the measurement units 3 coupled to the first to third input voltage supply terminals 11-13 of each of the memory modules 1 under test, wherein each measurement unit 3 includes A first measuring element 31 of the first input voltage supply terminal 11, a second measuring element 32 coupled to the second input voltage supply terminal 12, and one of the third input voltage supply terminal 13 The third measuring element 33. Step three s3: Use each measurement unit 3 to measure the input voltage and current of the first to third input voltage supply terminals 11-13 of the memory module 1 under test to generate the corresponding current supply voltage and feed it back to The central processing unit 4, in which the central processing unit 4 is connected to each of the memory module under test 1, the power management chip 2 and each of the measurement units 3, and has a built-in storage element 41, which can be accessed through software In this way, the power management chip 2 controls the original supply voltage provided to each memory module 1 under test. Step 4: s4: The central processing unit 4 compares each of the current supply voltages fed back by each of the measurement units 3 with each of the original supply voltages, and generates a corresponding compensation voltage according to the comparison result. Step 5 s5: For the memory module 1 under test related to the compensation voltage, the central processing unit 4 manages the power management chip 2 through the storage element 41 to control and provide the compensation voltage to the corresponding memory module 1 under test Compensation is performed to accurately adjust the correct supply voltage input to each end of the memory module under test. If so, a brand-new method for checking memory operating conditions is formed by the above-disclosed process.

When used, the present invention measures the power consumption of each memory module 1 under test more accurately. The operating voltage VDD and VDDQ, which are usually combined together on the traditional motherboard, are separated according to the The three separate first to third input voltage supply terminals 11-13 of VDD, VDDQ and VPP of the memory module 1 under test are used to measure the input voltage and current. In a preferred embodiment, the present invention is provided with a plurality of measurement units 3, such as a digital multimeter (DMM). Each of the measurement units 3 is correspondingly coupled to the first to the third input voltage supply terminals 11-13 of the memory module 1 under test from the first to the third input voltage supply terminals 11-13 on the motherboard. The three measuring components 31 to 33 measure the input voltage and current supplied to the first to third input voltage supply terminals 11 to 13 of the memory module 1 under test at the end to generate the corresponding current supply voltage. In this embodiment, although a digital multimeter is used as the measurement unit 3, it is described. However, the above-mentioned measuring unit 3 types are only examples of current mainstream measuring current components, and other components that have the same or similar functions that are not specified are also considered to be covered by the present invention.

The above-mentioned measuring unit 3 is implemented with the first to third measuring elements 31 to 33 respectively Add a resistance value of 8-12 milliohms (mΩ) to measure the input voltage and current of the first to third input voltage supply terminals 11-13 that are coupled to each other, and generate the corresponding current according to the change of the intermediate bias voltage of the resistance value Supply voltage, each of the measurement units 3 sends the measured current supply voltage back to the central processing unit 4. The central processing unit 4 supplies the power management chip 2 to each memory module under test according to the previous setting 1 original supply voltage (for example: 1.2 V), compare the current supply voltage (for example: 1.19 V) of each memory module 1 under test returned from each measurement unit 3, and know the supply voltage from the After the voltage deviation value (ΔV=1.2-1.19=0.01) between the output terminal of the power management chip 2 and the input terminal of the memory module 1 under test, a corresponding compensation voltage (for example: 0.01) is generated. V). The central processing unit 4 then controls the power management chip 2 through the storage element 41 to compensate the memory module 1 to be tested related to the compensation voltage, and adjust it according to the voltage required to increase or decrease. The traditional method does not have this technology. The motherboard of the present invention can more accurately adjust the correct supply voltage provided to each memory module 1 under test through the feedback of the above-mentioned measured values, so that the central processing unit 4 can perform the highest Efficiency, using these three operating voltages VDD, VDDQ and VPP to solve the problem of memory power supply voltage deviation, so that during mass production testing, the correct supply voltage input to each memory module under test can be accurately adjusted , In order to achieve consistent correction.

Thus, the present invention can accurately monitor the reference voltage (VREF) and other parameters in operation. By quickly changing the operating conditions, the frequency and CAS latency (CL) settings of the Basic Input and Output System (BIOS) can be quickly changed, so that the operating capability test under various conditions can be effectively performed.

In summary, the present invention is a method for checking memory operating conditions, which can effectively improve Conventional shortcomings. The central processing unit on the motherboard can provide more precise adjustments through the voltage measurement values returned by the measurement unit set at the input voltage (VDD, VDDQ, and VPP) supply terminals of each memory module under test. Provide the correct supply voltage for each memory module under test, so that the central processing unit can exert the highest efficiency. With the three operating voltages of VDD, VDDQ and VPP, the problem of memory power supply voltage deviation can be solved. The correct supply voltage input to each memory module under test can be accurately adjusted to achieve consistent calibration, so that the production of the present invention can be more advanced, more practical, and more in line with the needs of users. In accordance with the requirements of an invention patent application, Yan filed a patent application in accordance with the law.

However, the above are only preferred embodiments of the present invention, and should not be limited by this The scope of implementation of the present invention; therefore, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the description of the invention should still fall within the scope of the patent of the present invention.

1: Memory module to be tested

１１: The first input voltage supply terminal

12: The second input voltage supply terminal

13: The third input voltage supply terminal

2: Power management chip

3: Measuring unit

31: The first measuring component

32: The second measuring element

33: The third measuring element

4: Central Processing Unit

41: Storage element

s1～s5: Step 1～Step 5

Figure 1 is a schematic diagram of the process of the present invention. Figure 2 is a block diagram of the present invention.

1: Memory module to be tested

11: The first input voltage supply terminal

12: The second input voltage supply terminal

13: The third input voltage supply terminal

2: Power management chip

3: Measuring unit

31: The first measuring component

32: The second measuring element

33: The third measuring element

4: Central processing unit

41: storage components

Claims (5)

A method for checking operating conditions of a memory is implemented by a device for checking operating conditions of a memory. The method includes the following steps: Step 1: Provide several original supply voltages to several via a power management integrated circuit (PMIC) Memory modules under test (device under test, DUT), where each memory module under test is installed on a motherboard, and each memory module under test includes a first input voltage (VDD) supply terminal , A second input voltage (VDDQ) supply terminal, and a third input voltage (VPP) supply terminal, each of the original supply voltages is input to the first to third input voltage supplies of each memory module under test Terminal, and each of the original supply voltages includes VDD, VDDQ, and VPP; Step 2: Enable multiple measurement units coupled to the first to third input voltage supply terminals of each of the memory modules under test, each of which A measurement unit includes a first measurement element coupled to the first input voltage supply terminal, a second measurement element coupled to the second input voltage supply terminal, and a third input voltage Supply one of the third measurement elements of the terminal; Step 3: Use each of the measurement units to measure each of the memory modules to be tested, and each of the measurement units applies a resistance value to each of the first to third measurement elements Measure the input voltage and current corresponding to the first to third input voltage supply terminals that are coupled, and generate the corresponding current supply voltage according to the change of the intermediate bias voltage of the resistance value and feed it back to a central processing unit (CPU) ); Step 4: The central processing unit compares each of the current supply voltages fed back by each of the measurement units with each of the original supply voltages, and generates corresponding compensation voltages according to the comparison results; and Step 5: For the Compensation voltage related to the memory module under test, the central processing unit controls the power management chip to provide the compensation voltage to the corresponding memory module under test for compensation, so as to accurately adjust the input to each memory under test The correct supply voltage of the module. According to the method for checking the operating conditions of the memory described in the scope of patent application 1, the central processing unit is respectively connected to each of the memory modules to be tested, the power management chip and each of the measurement units, and the power supply The management chip is connected with each memory module to be tested. According to the method for checking the operating conditions of the memory described in the first item of the patent application, the central processing unit has a built-in storage element, and the power management chip can be managed by software, and the control is provided to each memory model under test The original supply voltage of the group and the compensation voltage are provided to the corresponding memory module under test. According to the method for checking the operating conditions of the memory described in item 1 of the scope of patent application, the plurality of measurement units are digital multimeters (DMM). According to the method for checking the operating conditions of the memory described in item 1 of the scope of patent application, the resistance value is 8-12 milliohms (mΩ).

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