CN113496758A - Memory operation capability prediction method - Google Patents
Memory operation capability prediction method Download PDFInfo
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- CN113496758A CN113496758A CN202010248370.2A CN202010248370A CN113496758A CN 113496758 A CN113496758 A CN 113496758A CN 202010248370 A CN202010248370 A CN 202010248370A CN 113496758 A CN113496758 A CN 113496758A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000012360 testing method Methods 0.000 claims abstract description 62
- 238000005259 measurement Methods 0.000 claims description 23
- 238000012545 processing Methods 0.000 claims description 22
- 230000001934 delay Effects 0.000 claims description 4
- 230000006870 function Effects 0.000 claims description 3
- 238000012216 screening Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000010998 test method Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
Abstract
A memory operation ability prediction method can be implemented by a memory operation ability prediction structure, by quickly changing the frequency of a Basic Input/Output System (BIOS) and the delay of a read-write time sequence, the mainboard test mode of the invention can measure accurate voltage value and current value, and is close to the mode that actually a plurality of Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) chips are applied together, and the operation interval range of each single DRAM IC chip can be measured under an operation mode, thereby predicting the operation ability of each IC chip, further effectively testing the operation ability under various conditions and improving the classified accurate value.
Description
Technical Field
The present invention relates to a method for predicting memory operation capability, and more particularly, to a method for testing a motherboard capable of measuring accurate voltage and current values, and more particularly, to a method for measuring an operation interval range of each DRAM IC chip by rapidly changing a BIOS frequency and a read/write timing delay, so as to predict the operation capability of each DRAM IC chip, thereby effectively performing operation capability tests under various conditions and improving classified accurate values.
Background
During the manufacturing process of memory circuits and devices, such as Dynamic Random Access Memory (DRAM), it is necessary to test the memory circuits or devices. This testing is typically accomplished using Automated Test Equipment (ATE) coupled to the memory circuit or device (i.e., Device Under Test (DUT)): certain predetermined test signals are generated by the ATE and transmitted to the DUT, and the DUT is evaluated based on the responses by receiving response signals from the DUT.
ATE itself currently provides accurate voltage, meter, and timing control, which is basically a classification of automated testing. However, because test equipment like ATE is expensive, high test costs diminish price competitiveness; moreover, the operation capability of each single Integrated Circuit (IC) obtained from the test result is not tested in the operation mode, and thus cannot meet the requirement of actual use. In addition, in addition to ATE, the known technology uses a relatively inexpensive motherboard in an actual operation mode to test multiple ICs together, which is relatively close to the way in which the actual ICs are used to operate applications, so the motherboard is a test method that is selected by many people; however, the most serious drawback of this method is that the voltage is not accurate enough, the current cannot be measured, and it cannot be known which IC among many ICs consumes more power, and the timing control aspect is only the frequency-enabled or non-enabled test. Therefore, although the motherboard is a test performed in the actual operation mode, the classification of the motherboard is not accurate enough.
Therefore, although ATE is a standard practice in the field of memory testing, the cost of the testing apparatus is still high, and each IC is not tested in the operating mode, but the classification of the motherboard is not precise enough. Therefore, it is generally not suitable for the actual use of the user.
Disclosure of Invention
The main objective of the present invention is to overcome the above problems encountered in the prior art, and to provide a method for predicting the operation capability of a memory, which can measure the accurate voltage and current values by rapidly changing the BIOS frequency and CL, and can measure the operation interval range of each single DRAM IC chip by using a method close to the actual application of multiple DRAM IC chips together, thereby predicting the operation capability of each DRAM IC chip, and further effectively performing the operation capability test under various conditions, and improving the classification accuracy.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows: a memory operation capability prediction method implemented by a memory operation capability prediction structure, the method comprising the steps of:
the method comprises the following steps: inserting a plurality of to-be-tested memory modules (DUT) onto a mainboard;
step two: starting an Input module on the mainboard, and reading a Basic Input/Output System (BIOS) with a memory margin test function into how to test the memory module to be tested, wherein the memory margin test is a memory test mode under an operation mode of a specific time sequence;
step three: starting a switching module on the mainboard, switching a measuring mode for each memory module to be tested according to one of measuring voltage or measuring current, and enabling each memory module to be tested to carry out the memory margin test;
step four: starting a measuring module on the mainboard to measure the memory characteristics of each memory module to be measured through memory margin tests in different measuring modes, wherein the measuring module comprises a voltage measuring unit and a current measuring unit, the voltage measuring unit can measure the power supply voltage of each memory module to be measured in the voltage measuring mode, the current measuring unit can measure the current flowing through each memory module to be measured in the current measuring mode, and the measured memory characteristics of each memory module to be measured are sent to a processing module on the mainboard; the memory characteristics comprise voltage information and current information measured by a memory margin test;
step five: the processing module reads the memory characteristics of each memory module to be tested through the memory margin test sent by the measuring module, the memory characteristics are measured through the memory margin test and the voltage and current measurement, the operable interval of each memory module to be tested is set through different BIOS frequencies and different read-write time sequence delays, the currently operable interval range of each memory module to be tested is recorded, and therefore fast screening and classification are achieved, each memory module to be tested can be accurately operated in a single memory margin test mode, the accurate value of the classified interval of each memory module to be tested is obtained, and the operation capability of each memory module to be tested is predicted.
In the above embodiment of the present invention, the switching module is connected to the input module and each of the memory modules to be tested, the measuring module is connected to the switching module, and the processing module is connected to the measuring module.
In the above embodiments of the present invention, each of the memory modules to be tested may be a Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) chip.
In the above embodiments of the present invention, the processing module may be a Central Processing Unit (CPU).
In the above embodiments of the present invention, the memory margin test is a memory test mode under an operation mode with a specific timing of 3200 MHz, 3600 MHz or 4000 MHz.
In the above embodiments of the present invention, the voltage measuring unit measures a power supply voltage of each memory module to be tested from small to large, and the current measuring unit measures a current flowing through each memory module to be tested from small to large. In the above embodiments of the present invention, the processing module further includes a storage unit, which is used to record the currently operable interval range of each memory module to be tested into the storage unit.
Drawings
FIG. 1 is a schematic flow diagram of the present invention.
FIG. 2 is a block diagram of the present invention.
Reference numbers refer to:
Memory module 1 to be tested
Input module 2
Measuring module 4
A storage unit 51.
Detailed Description
Please refer to fig. 1 and fig. 2, which are a schematic flow chart and a block diagram of the present invention, respectively. As shown in the figure: the invention relates to a memory operation capability prediction method, which is implemented by a memory operation capability prediction structure and comprises a plurality of memory modules (DUT) 1 to be tested, an input module 2, a switching module 3, a measuring module 4 and a processing module 5. The memory operation capability prediction method comprises the following steps:
step one s 1: a plurality of memory modules (DUT) 1 to be tested are plugged into a motherboard 100, and each memory module 1 to be tested may be a Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) chip, which is a DRAM IC chip 1 to a DRAM IC chip N.
Step two s 2: starting the Input module 2 on the main board 100, and reading in how to test each memory module 1 to be tested by using a Basic Input/Output System (BIOS) having a memory margin test function through the Input module 2; wherein the memory margin test is a memory test mode in an operation mode of a specific timing.
Step three s 3: the switching module 3 connecting the input module 2 and each memory module 1 to be tested on the motherboard 100 is activated, and the measurement mode is switched for each memory module 1 to be tested according to one of the measurement voltage or the measurement current, so that each memory module 1 to be tested performs the memory margin test.
Step four s 4: starting the measurement module 4 connected to the switching module 3 on the motherboard 100, and measuring the memory characteristics of each memory module 1 to be tested through the measurement module 4 in a memory margin test in different measurement modes (measuring voltage or measuring current). The measurement module 4 includes a voltage measurement unit 41 and a current measurement unit 42, and the voltage measurement unit 41 can measure the power supply voltage of each memory module 1 to be measured when the measurement module is switched to the voltage measurement mode, and the current measurement unit 42 can measure the current flowing through each memory module to be measured when the measurement module is switched to the current measurement mode, and the memory characteristics of each memory module 1 to be measured are fed back to the processing module 5 on the motherboard 100; the memory characteristics include voltage information and current information measured in a specific timing operation mode.
Step five s 5: the processing module 5 is connected to the measuring module 4, the processing module 5 may be a Central Processing Unit (CPU), the processing module 5 reads the memory characteristics of each memory module 1 to be tested under the operation mode of a specific time sequence, the memory margin test and the voltage and current measurement are combined together, the operable interval of each memory module 1 to be tested is set by different BIOS frequencies and different read-write time sequence delays, and the currently operable interval range of each memory module 1 to be tested is recorded, so that the memory modules 1 to be tested can be rapidly screened and classified by single accurate operation in the memory margin test, and an accurate value of the classified interval of each memory module 1 to be tested is obtained, so as to predict (predict) the operation capability of each memory module 1 to be tested. Thus, the method for predicting the operation capability of the memory is completely new by the process disclosed above.
In one embodiment, the memory margin test provided by the present invention is in a memory test mode under an operation mode of a specific timing, the operation mode of the specific timing is: such as modes of operation at 3200 MHz, 3600 MHz or 4000 MHz. In practical applications, a measuring module 4 for detecting the memory characteristics of each memory module 1 to be tested may be disposed in front of each memory module 1 to be tested, and includes a voltage measuring unit 41 and a current measuring unit 42 for measuring the voltage information and the current information of each memory module 1 to be tested, including the voltage measuring unit 41 measuring the power supply voltage of each memory module 1 to be tested from small to large, and the current measuring unit 42 measuring the current flowing through each memory module 1 to be tested from small to large. Each measuring module 4 is directly connected with the processing module 5, so that the processing module 5 can obtain the memory characteristics of each memory module 11 to be tested; for example, when the timing is set by the BIOS in the 4000 MHz operation mode, the measurement module 4 detects whether each memory module 1 to be tested can read and write the voltage and current information of each memory module 1 to be tested at the timing during the test, and if the memory module 1 to be tested can be successfully read and written, it indicates that the test can be passed in the 4000 MHz operation mode. Therefore, the successfully read/written memory module 1 to be tested can know the operation interval under 4000 MHz, and in this way, the voltage value and the current value under each specific time sequence operation mode can be known. The processing module 5 records the remaining margin of each memory module 1 to be tested, i.e. writes the operating window range of each memory module 1 to be tested into a storage unit 51 for recording.
The present invention is based on certain parameters in operation (e.g., reference voltage (V)REF) Can be measured and compared, by quickly changing BIOS frequency and CL setting, the DRAM IC chips are classified, the operable interval of each DRAM IC chip is set by different frequencies and different read-write time sequence delays, so that the currently operable interval range of each DRAM IC chip is known, and by the quick screening, quick classification is achieved, so that each single DRAM IC chip can be operated in a single accurate mode in an operation mode, and the accurate value of the classified interval is found, thereby the operation capability of each DRAM IC chip can be predicted, and further each DRAM IC chip can have higher operation efficiency in actual operation. Therefore, by quickly changing the BIOS frequency and the CL, the mainboard test method can measure accurate voltage value and current value, is close to the mode that a plurality of DRAM IC chips are actually applied together, and can measure the operation interval range of each single DRAM IC chip, thereby effectively carrying out the operation capability test under various conditions and improving the classified accurate value.
In summary, the method for predicting the operation capability of the memory of the present invention can effectively improve various defects in the prior art, and by rapidly changing the frequency of the basic input/output system (BIOS) and the delay of the read/write timing sequence, the main board test method of the present invention can measure the accurate voltage value and current value, and is close to the way of actually using a plurality of Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) chips together, and can measure the operation interval range of each single DRAM IC chip, thereby predicting the operation capability of each DRAM IC chip, and thus effectively performing the operation capability test under various conditions, improving the classified accurate value, further making the present invention more advanced, more practical, and more in line with the needs of users, and confirming that the requirements of the invention patent application are met, and accordingly providing the patent application.
However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention should not be limited thereby. Therefore, all the equivalent changes and modifications made according to the claims and the content of the specification should be covered by the scope of the present invention.
Claims (7)
1. A memory operation capability prediction method implemented by a memory operation capability prediction structure, the method comprising the steps of:
the method comprises the following steps: a plurality of memory modules to be tested are plugged on the mainboard;
step two: starting an input module on the mainboard, reading in how to test the memory module to be tested by a basic input and output system with a memory margin test function, wherein the memory margin test is a memory test mode under an operation mode with a specific time sequence;
step three: starting a switching module on the mainboard, switching a measuring mode for each memory module to be tested according to one of measuring voltage or measuring current, and enabling each memory module to be tested to carry out the memory margin test;
step four: starting a measuring module on the mainboard to measure the memory characteristics of each memory module to be measured through memory margin tests in different measuring modes, wherein the measuring module comprises a voltage measuring unit and a current measuring unit, the voltage measuring unit can measure the power supply voltage of each memory module to be measured in the voltage measuring mode, the current measuring unit can measure the current flowing through each memory module to be measured in the current measuring mode, and the measured memory characteristics of each memory module to be measured are sent to a processing module on the mainboard; the memory characteristics comprise voltage information and current information measured by a memory margin test;
step five: the processing module reads the memory characteristics of each memory module to be tested through the memory margin test sent by the measuring module, the memory characteristics are measured through the memory margin test and the voltage and current measurement, the operable interval of each memory module to be tested is set through different BIOS frequencies and different read-write time sequence delays, the currently operable interval range of each memory module to be tested is recorded, and therefore fast screening and classification are achieved, each memory module to be tested can be accurately operated in a single memory margin test mode, the accurate value of the classified interval of each memory module to be tested is obtained, and the operation capability of each memory module to be tested is predicted.
2. The method as claimed in claim 1, wherein the switch module is connected to the input module and each of the memory modules under test, the measurement module is connected to the switch module, and the processing module is connected to the measurement module.
3. The method as claimed in claim 1, wherein each of the memory modules under test is a dynamic random access memory integrated circuit chip.
4. The method of claim 1, wherein the processing module is a central processing unit.
5. The method of claim 1, wherein the memory margin test is a memory test mode in an operation mode with a specific timing of 3200 MHz, 3600 MHz or 4000 MHz.
6. The method of claim 1, wherein the voltage measurement unit measures a power supply voltage from small to large for each memory module under test, and the current measurement unit measures a current from small to large through each memory module under test.
7. The method as claimed in claim 1, wherein the processing module further comprises a storage unit for recording a current operational window of each memory module under test into the storage unit.
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| CN202010248370.2A CN113496758A (en) | 2020-04-01 | 2020-04-01 | Memory operation capability prediction method |
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| CN202010248370.2A CN113496758A (en) | 2020-04-01 | 2020-04-01 | Memory operation capability prediction method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116913368A (en) * | 2023-09-08 | 2023-10-20 | 合肥康芯威存储技术有限公司 | Test system and test method for memory chip |
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| CN104615518A (en) * | 2015-03-04 | 2015-05-13 | 浪潮集团有限公司 | Memory rank margin test method combined with temperature and voltage variables |
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2020
- 2020-04-01 CN CN202010248370.2A patent/CN113496758A/en active Pending
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| US6002622A (en) * | 1998-02-19 | 1999-12-14 | Micron Technology, Inc. | Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116913368A (en) * | 2023-09-08 | 2023-10-20 | 合肥康芯威存储技术有限公司 | Test system and test method for memory chip |
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