CN220040663U - Testing device and testing machine box - Google Patents
Testing device and testing machine box Download PDFInfo
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- CN220040663U CN220040663U CN202321493915.1U CN202321493915U CN220040663U CN 220040663 U CN220040663 U CN 220040663U CN 202321493915 U CN202321493915 U CN 202321493915U CN 220040663 U CN220040663 U CN 220040663U
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- 238000012360 testing method Methods 0.000 title claims abstract description 167
- 238000005259 measurement Methods 0.000 claims abstract description 18
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Abstract
The utility model relates to a testing device and a testing machine box. The test device comprises: the test board comprises a test fixture and a test circuit, wherein the test fixture is used for bearing a plurality of chips to be tested; the source measurement unit board card comprises a processor chip, wherein the processor chip is used for controlling a test circuit to perform open-short circuit test on a chip to be tested. The utility model directly forms the test circuit for open-short circuit test on the test board card, effectively reduces the number of instruments and meters required by the peripheral circuit, reduces the cost, simultaneously reduces the test time cost and improves the test efficiency.
Description
Technical Field
The present utility model relates to the field of chip testing technologies, and in particular, to a testing device and a testing box.
Background
Chip testing is also becoming increasingly diverse in response to the development of chips. For example, the chip test includes an open-short test, a power-on function test, a serial port function test, and the like.
The diversified chip tests increase the number of peripheral circuits to be built, greatly increase the test cost and waste the test time.
Disclosure of Invention
Based on this, it is necessary to provide a testing device and a testing box which effectively reduce peripheral circuits and save testing time.
A test apparatus comprising:
the test board comprises a test fixture and a test circuit, wherein the test fixture is used for bearing a plurality of chips to be tested;
the source measurement unit board card comprises a processor chip, wherein the processor chip is used for controlling the test circuit to perform open-short circuit test on the chip to be tested.
In the testing device, the testing circuit for performing open-short circuit testing is directly formed on the testing board card, so that the number of instruments and meters required by the peripheral circuit is effectively reduced, the cost is reduced, meanwhile, the testing time cost is reduced, and the testing efficiency is improved.
In one embodiment, the source measurement unit board card includes an enable pin and a chip selection pin, where the enable pin and the chip selection pin jointly control the target chip to be measured to be connected to the test circuit, and the target chip to be measured is one of the chips to be measured.
In one embodiment, the plurality of chips includes a first chip to be tested, a second chip to be tested, a third chip to be tested, and a fourth chip to be tested,
the chip select pins include a first pin and a second pin,
when the enabling pin is at a high level, the first pin and the second pin select one of the chips to be tested to access the test circuit.
In one embodiment, the source-measurement-unit board further includes a control circuit, and the control circuit is connected to the processor chip.
In one embodiment, the test device further comprises:
and the upper computer is connected with the control circuit.
In one embodiment, the test board card is further provided with a writing circuit, and the writing circuit is connected with the upper computer and used for writing the chip to be tested.
In one embodiment, the source measurement unit board further includes a strobe pin, where the strobe pin is used to control the chip to be tested to perform an open-short circuit test or a software burn.
In one embodiment, the processor chip includes a chip open short test chip, a chip power-on function test chip, and a switch control chip.
In one embodiment, the source measurement unit board card further includes a power enable pin for controlling a power supply of the test board card.
A test case comprises a power supply device and the test device, wherein the power supply device is used for supplying power to the test device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present utility model, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a block diagram of a test apparatus according to an embodiment;
FIG. 2 is a block diagram of a test apparatus according to another embodiment;
fig. 3 is a schematic connection diagram of a testing device according to an embodiment.
Reference numerals illustrate: 100-source measuring unit board card, 110-control circuit, 120-processor chip, 200-test board card, 210-test circuit, 220-test fixture, 221-first chip to be tested, 222-second chip to be tested, 223-third chip to be tested, 224-fourth chip to be tested, 230-burning circuit, 240-power supply end and 300-upper computer.
Detailed Description
In order that the utility model may be readily understood, a more complete description of the utility model will be rendered by reference to the appended drawings. Embodiments of the utility model are illustrated in the accompanying drawings. This utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model.
It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the utility model. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
In one embodiment, a test case is provided that includes a power supply device and a test device, the power supply device being operable to power the test device. For example, the test chassis includes a PXIe chassis.
In one embodiment, referring to fig. 1, a test apparatus is provided, the test apparatus includes a test board 200 and a source measurement unit board 100.
The test board 200 includes a test fixture 220 and a test circuit 210, wherein the test fixture 220 is used for carrying a plurality of chips to be tested, and the plurality of chips can be two or more than two. The test circuit 210 is connected to the test fixture 220, and specifically, the test circuit 210 is connected to the test chip through the test fixture 220.
The source measurement unit board 100 includes a processor chip 120, and the processor chip 120 is used for controlling the test circuit 210 to perform an open-short test on a chip to be tested. As an example, the source measurement unit board 100 may be provided with a plurality of processor chips 120, and each processor chip 120 may correspond to a different test pin of the chip to be tested, and may test the chip to be tested by sending a different control signal to the chip to be tested. Specifically, the processor chip 120 includes a plurality of digital-to-analog conversion chips and a plurality of analog-to-digital conversion chips. The analog-to-digital conversion chip can send different voltage or current signals to different pins of the chip to be tested, and the pins of the chip to be tested are tested.
The source-measurement unit (Source Measure Unit, SMU) board card has four functions, respectively: supply current (Force Current Measure Current, FIMI), supply voltage (Force Voltage Measure Current, FVMI), supply current voltage (Force Current Measure Voltage, FIMV) and supply voltage (Force Voltage Measure Voltage, FVMV). The source-measurement-unit board 100 can accommodate 32 external power screens and support a maximum current of 80 milliamps. Source-measuring cell board 100 may provide accurate voltage or current source measurement for PXI systems.
In this embodiment, the test circuit 210 for performing the open-short circuit test is directly formed on the test board 200, so that the number of instruments and meters required by the peripheral circuit is effectively reduced, the cost is reduced, and meanwhile, the test time cost is reduced, and the test efficiency is improved.
In one embodiment, the source measurement unit board 100 includes an enable pin and a chip select pin, where the enable pin and the chip select pin together control the chip under test to be connected to the test circuit 210, and the target chip under test is one of the chips under test.
As an example, referring to fig. 3, the chip select pins may include a first pin and a second pin, and at this time, the plurality of chips to be tested may include a first chip to be tested 221, a second chip to be tested 222, a third chip to be tested 223, and a fourth chip to be tested 224. When the enable pin is at a high level, the first pin and the second pin select one of the first chip under test 221, the second chip under test 222, the third chip under test 223, and the fourth chip under test 224 to be connected to the test circuit 210. Specifically, when the first pin and the second pin are both at the low level, the first chip 221 to be tested is connected to the test circuit 210, and the first chip 221 to be tested performs an open-short circuit test; when the first pin is at low level and the second pin is at high level, the second chip 222 to be tested is connected to the test circuit 210, and the second chip 222 to be tested performs an open-short circuit test; when the first test pin is at high level and the second pin is at low level, the third chip to be tested 223 is connected to the test circuit 210, and the third chip to be tested 223 performs an open-short circuit test; when the first test pin and the second pin are both at high level, the fourth chip 224 to be tested is connected to the test circuit 210, and the fourth chip 224 to be tested performs an open-short circuit test.
However, when the enable pin is at a low level, no chip to be tested is connected to the test circuit 210, i.e. no open-circuit test is performed on any chip to be tested, regardless of the level of the first pin and the second pin.
In other examples, the number of the chip selection pins is not limited, and when the number of the chip selection pins is three, the number of the chips to be tested may be eight, and by setting the level of the three chip selection pins, one of the eight chips to be tested may be selected to be connected to the test circuit 210, so as to complete the open-short circuit test of the chip to be tested.
In this embodiment, the control of the IO is implemented by using the channel of the source measurement unit board 100, so that a large number of test functions can be completed for a plurality of chips to be tested.
In one embodiment, referring to fig. 2, the source-measurement-unit board 100 further includes a control circuit 110, and the control circuit 110 is connected to the processor chip 120. For example, the control circuit 110 may be a Field Programmable Gate Array (FPGA) that controls the processor chip 120 to perform the relevant operations of open-short testing.
In one embodiment, the testing device further includes a host computer 300, and the host computer 300 is connected to the control circuit 110. The upper computer 300 communicates with the control circuit 110, the upper computer 300 sends out an instruction, and the control circuit 110 further controls the processor chip 120 to execute related operations of the open-short circuit test according to the test instruction of the upper computer 300.
In one embodiment, please refer to fig. 2, the test board 200 is further provided with a writing circuit 230, the writing circuit 230 is connected to the host computer 300, and the writing circuit 230 is used for writing software to the chip to be tested. Recording may refer to recording data onto a recording disc with a recorder. The writing can write the written program execution file onto the chip to be tested, so that the chip to be tested can complete the preset function. The preset parameters (such as the IP address and the data of the port of the wifi module) can be burnt on the chip to be tested. The upper computer 300 realizes the software programming of the chip to be tested through the programming circuit 230.
In addition, the test board 200 further has a power supply end 240, and the host computer 300 supplies power to the test board 200 through a universal serial bus (Universal Serial Bus, USB) interface. The upper computer 300 also communicates with the chip to be tested through the serial bus interface, so that the serial port function test of the chip to be tested is realized, meanwhile, the upper computer 300 can also send an instruction to the chip to be tested, and the chip to be tested can execute related operation or feedback signals according to the instruction.
In the embodiment, however, the burning circuit 230 is directly arranged on the test board 200, so that the software burning of the chip to be tested is more convenient and faster, the problem that the serial communication rate of the chip is not matched with the firmware downloading rate is effectively avoided, and the reliability of communication and firmware downloading is improved. Meanwhile, the burning circuit 230, the testing circuit 210 and the testing jig 220 are integrated on the testing board 200, which increases the integration level of the testing board 200.
In one embodiment, the source-measurement-unit board 100 further includes a strobe pin for controlling the chip under test to perform an open-short test or software burn-in. When the on pin is at a high level, the chip to be tested performs an open-short circuit test; when the power-on pin is at a low level, the chip to be tested is subjected to software burning.
As an example, the source-measuring cell board 100 includes a power enable pin for controlling the power supply of the test board 200. When the power enable pin is high, the power supply of the test board 200 is active. The source measurement unit board 100 also includes a serial communication enable pin, active high. In addition, the source-measurement unit board 100 also includes a plurality of pins that connect to open-short test resources.
In one embodiment, processor chip 120 includes a chip open short test chip, a chip power-on function test chip, and a switch control chip.
The chip open-circuit test chip is used for controlling the test circuit 210 to perform open-circuit test on the chip to be tested. The chip power-on function test chip is used for controlling other test circuits to perform power-on function test on the chip to be tested. The switch control chip is used for sending a control instruction to the multiplexing switch, and then different chips are selected for testing.
In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present utility model, which are described in more detail and are not to be construed as limiting the scope of the present utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of the utility model should be assessed as that of the appended claims.
Claims (10)
1. A test device, comprising:
the test board comprises a test fixture and a test circuit, wherein the test fixture is used for bearing a plurality of chips to be tested;
the source measurement unit board card comprises a processor chip, wherein the processor chip is used for controlling the test circuit to perform open-short circuit test on the chip to be tested.
2. The test device of claim 1, wherein the source measurement unit board card includes an enable pin and a chip select pin, the enable pin and the chip select pin together control access of a target die under test to the test circuit, the target die under test being one of the plurality of dies under test.
3. The test device according to claim 2, wherein,
the plurality of chips to be tested comprise a first chip to be tested, a second chip to be tested, a third chip to be tested and a fourth chip to be tested,
the chip select pins include a first pin and a second pin,
when the enabling pin is at a high level, the first pin and the second pin select one of the chips to be tested to access the test circuit.
4. The test device of claim 1, wherein the source-measurement-unit board card further comprises a control circuit, the control circuit being coupled to the processor chip.
5. The test device of claim 4, further comprising:
and the upper computer is connected with the control circuit.
6. The device according to claim 5, wherein the test board card is further provided with a burning circuit, and the burning circuit is connected to the host computer and is used for burning the chip to be tested.
7. The test device of claim 6, wherein the source-measurement unit board card further comprises a strobe pin for controlling the chip under test to perform an open-short test or a software burn-in.
8. The test device of claim 1, wherein the processor chip comprises a chip open short test chip, a chip power-on function test chip, and a switch control chip.
9. The test device of claim 1, wherein the source-measurement unit board further comprises a power enable pin for controlling a power supply of the test board.
10. A test chassis comprising power supply means for supplying power to the test apparatus as claimed in any one of claims 1 to 9 and the test apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321493915.1U CN220040663U (en) | 2023-06-13 | 2023-06-13 | Testing device and testing machine box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321493915.1U CN220040663U (en) | 2023-06-13 | 2023-06-13 | Testing device and testing machine box |
Publications (1)
| Publication Number | Publication Date |
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| CN220040663U true CN220040663U (en) | 2023-11-17 |
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| CN202321493915.1U Active CN220040663U (en) | 2023-06-13 | 2023-06-13 | Testing device and testing machine box |
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| CN (1) | CN220040663U (en) |
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- 2023-06-13 CN CN202321493915.1U patent/CN220040663U/en active Active
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