CN219392962U - MRAM chip test system - Google Patents

Abstract

The utility model discloses an MRAM chip test system, and relates to the technical field of chip verification test. The system comprises an upper computer, an FPGA test bottom plate provided with an FPGA core plate and an MRAM chip adapter plate; the upper computer is connected with the FPGA test base plate and used for transmitting target test excitation to the FPGA core plate on the FPGA test base plate; the FPGA testing bottom plate is connected with the MRAM chip adapter plate and is used for testing the MRAM chip on the MRAM chip adapter plate by utilizing the FPGA core plate according to target testing excitation and feeding back testing information to the upper computer. Therefore, the MRAM chip testing system realizes the test of the MRAM chip; because the FPGA test bottom plate and the MRAM chip adapter plate in the system have the advantages of simple structure, small volume and low development cost, the test efficiency can be effectively improved, and the multiple functional verification tests of different packaging forms of the MRAM chip are satisfied.

Description

MRAM chip test system

Technical Field

The present utility model relates to the field of chip verification testing technologies, and in particular, to an MRAM chip testing system.

Background

Spin-Transfer torque-magnetic Random Access Memory (STT-MRAM) is a nonvolatile Memory having high integration of dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) and high-speed read/write capability of Static Random Access Memory (SRAM). The system testing of MRAM chips generally includes: full array read-write, array random read-write, register read-write, analog voltage of internal power supply, external access power supply voltage (external supply for short), array function test, read-write speed, reliability test and the like of the test chip. Systematic chip testing is an indispensable step in product design and manufacturing.

The current MRAM chip test is based on automatic test equipment (Automatic Test Equipment, ATE), but ATE test equipment is expensive, cannot be flexibly carried, is inconvenient to carry, has strict requirements on test environment, and is difficult to deeply study each test mode of the chip by using the traditional software debugging technology.

In view of the above problems, an automatic verification testing system which has a simple structure, is flexible to operate, has low development cost and wide testing range, and is suitable for a common experimental environment is provided, which is a problem to be solved by those skilled in the art.

Disclosure of Invention

The utility model aims to provide an MRAM chip test system which has the advantages of simple structure, flexible operation, low development cost, wide test range and suitability for common experimental environments.

In order to solve the above technical problems, the present utility model provides an MRAM chip testing system, which is characterized in that: the upper computer, the FPGA test bottom plate provided with the FPGA core plate and the MRAM chip adapter plate;

the upper computer is connected with the FPGA test base plate and is used for transmitting target test excitation to the FPGA core plate on the FPGA test base plate;

the FPGA testing bottom plate is connected with the MRAM chip adapter plate and is used for testing the MRAM chip on the MRAM chip adapter plate by utilizing the FPGA core plate according to the target testing excitation and feeding back testing information to the upper computer.

Preferably, the FPGA test board is provided with a USB Uart1 interface, and is connected to the host computer through the USB Uart1 interface, so as to feed back the test information.

Preferably, the FPGA test board is provided with a JTAG interface, and is connected to the host computer through the JTAG interface, so as to receive the target test stimulus.

Preferably, the FPGA core panel is connected to the FPGA test chassis via a BTB connector.

Preferably, the MRAM chip adapter plate is connected with the FPGA test board through a BTB connector.

Preferably, the FPGA test bottom plate is provided with an ADC module and a DAC module;

the communication interface of the ADC module and the communication interface of the DAC module are respectively connected with the FPGA test bottom plate through SPI interfaces.

Preferably, the connection position of the communication interface of the ADC module and the FPGA test board is the same as the connection position of the communication interface of the DAC module and the FPGA test board.

Preferably, the FPGA test bottom plate is provided with a switch key and a power interface;

the switch key is used for controlling the on-off of the FPGA test base plate; the power interface is used for connecting a power supply to supply power for the FPGA test bottom plate, the ADC module and the DAC module.

Preferably, the MRAM chip adapter plate is provided with a Socket, and the Socket is used for connecting the MRAM chip adapter plate with the MRAM chip.

Preferably, the number of sockets is a plurality.

The utility model provides an MRAM chip testing system, which comprises an upper computer, an FPGA testing bottom plate provided with an FPGA core plate and an MRAM chip adapter plate; the upper computer is connected with the FPGA test base plate and used for transmitting target test excitation to the FPGA core plate on the FPGA test base plate; the FPGA testing bottom plate is connected with the MRAM chip adapter plate and is used for testing the MRAM chip on the MRAM chip adapter plate by utilizing the FPGA core plate according to target testing excitation and feeding back testing information to the upper computer. Therefore, the scheme realizes the test of the MRAM chip through the upper computer, the FPGA test bottom plate provided with the FPGA core plate and the MRAM chip adapter plate; because the FPGA test bottom plate and the MRAM chip adapter plate have the advantages of simple structure, small volume and low development cost, the test efficiency can be effectively improved, and the multiple functional verification tests of different packaging forms of the MRAM chip are satisfied.

Drawings

For a clearer description of embodiments of the present utility model, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of an MRAM chip testing system according to an embodiment of the present disclosure;

FIG. 2 is a block diagram of an MRAM chip test system according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an MRAM chip interposer according to an embodiment of the present disclosure;

fig. 4 is a block diagram of another MRAM chip interposer according to an embodiment of the present application.

Wherein 10 is the upper computer, 11 is the FPGA test bottom plate, 12 is the MRAM chip keysets, 101 is the FPGA core plate.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present utility model.

The core of the utility model is to provide an MRAM chip test system which has the advantages of simple structure, flexible operation, low development cost, wide test range and suitability for common experimental environment.

In order to better understand the aspects of the present utility model, the present utility model will be described in further detail with reference to the accompanying drawings and detailed description.

Fig. 1 is a schematic diagram of an MRAM chip test system according to an embodiment of the present application. As shown in fig. 1, the MRAM chip test system includes: the upper computer 10, an FPGA test base plate 11 provided with an FPGA core plate 101 and an MRAM chip adapter plate 12;

the upper computer 10 is connected with the FPGA test base plate 11 and is used for transmitting target test excitation to the FPGA core plate 101 on the FPGA test base plate 11;

the FPGA test board 11 is connected to the MRAM chip adapter 12, and is configured to test the MRAM chip on the MRAM chip adapter 12 by using the FPGA core board 101 according to the target test excitation, and feed back test information to the upper computer 10.

It can be understood that, in the process of testing the MRAM chip, the upper computer 10 is responsible for creating a test project of the MRAM chip through a field programmable gate array (Field Programmable Gate Array, FPGA) development tool, completing configuration of bit width and Input/Output attribute of each pin of the MRAM chip to be tested, completing a one-to-one correspondence between pins of the chip to be tested and pins of a general Input/Output (I/O) port of the FPGA, and writing preparation work of chip test such as target test stimulus, and further sending the target test stimulus for performing the chip test to the FPGA test base plate 11, so that the FPGA core plate 101 obtains the target test stimulus.

It should be noted that the specific type of the upper computer 10 is not limited in this embodiment, and may be a personal computer (Personal Computer, PC), a server, and other controllers with a master control function, depending on the specific implementation.

The FPGA test board 11 is used for connecting the upper computer 10 with the MRAM chip adapter board 12, and testing MRAM chips in the MRAM chip adapter board 12 through the FPGA core board 101 and target test excitation arranged thereon, and feeding back test information generated by the FPGA core board 101 to the upper computer 10. The FPGA core board 101 has the functions of high-speed data processing and storage, and meets the requirement of a high buffer area in the data processing process. In specific implementation, a proper model of the FPGA core board can be selected according to specific implementation conditions so as to complete chip testing.

In addition, in this embodiment, the connection mode between the FPGA test board 11 and the host computer 10 and the connection mode between the FPGA test board 11 and the MRAM chip interposer 12 are not limited, and are determined according to specific implementation conditions. The specific structure of the FPGA test chassis 11 is not limited, and depends on the specific implementation.

The MRAM chip interposer 12 is an interposer of the MRAM chip under test, and has a main function of fixing the MRAM chip and transmitting data between the MRAM chip and the FPGA core board 101. The specific structure of the MRAM chip interposer 12 is not limited in this embodiment, and depends on the specific implementation.

In this embodiment, the MRAM chip test system includes an upper computer, an FPGA test board provided with an FPGA core board, and an MRAM chip adapter board; the upper computer is connected with the FPGA test base plate and used for transmitting target test excitation to the FPGA core plate on the FPGA test base plate; the FPGA testing bottom plate is connected with the MRAM chip adapter plate and is used for testing the MRAM chip on the MRAM chip adapter plate by utilizing the FPGA core plate according to target testing excitation and feeding back testing information to the upper computer. Therefore, the scheme realizes the test of the MRAM chip through the upper computer, the FPGA test bottom plate provided with the FPGA core plate and the MRAM chip adapter plate; because the FPGA test bottom plate and the MRAM chip adapter plate have the advantages of simple structure, small volume and low development cost, the test efficiency can be effectively improved, and the multiple functional verification tests of different packaging forms of the MRAM chip are satisfied.

Fig. 2 is a block diagram of an MRAM chip test system according to an embodiment of the present application. As shown in fig. 2, based on the above embodiment, as a preferred embodiment, the FPGA test board 11 is provided with a USB Uart1 interface, and is connected to the host computer 10 through the USB Uart1 interface for feeding back test information.

It will be appreciated that in order to implement MRAM chip automated testing, the FPGA test backplane 11 should have a communication interface that satisfies its communication with the host computer 10. Specifically, a USB Uart1 interface is disposed on the FPGA test board 11, and is connected with the upper computer 10 through a USB data line by using the USB Uart1 interface, so as to implement serial data communication between the upper computer 10 and the FPGA core board 101, and feedback test information.

As a preferred embodiment, the FPGA test backplane 11 is provided with a JTAG interface and is connected to the host computer 10 through the JTAG interface for receiving target test stimuli.

In a specific implementation, the upper computer 10 is connected to the FPGA test backplane 11 using a JTAG interface, i.e., (Joint Test Action Group, joint test workgroup) interface. The basic principle of the JTAG interface is to define a Test Access Port (TAP) inside the device, and Test the internal node by a special JTAG Test tool. JTAG test allows multiple devices to be connected in series through JTAG interfaces to form a JTAG chain, so that each device can be tested separately. Therefore, in this embodiment, the target test stimulus is downloaded to the FLASH memory on the FPGA core board 101 through the JTAG interface, so that the FPGA core board 101 realizes the test on the MRAM chip.

Furthermore, in order to better realize the connection of the FPGA test chassis 11 and the FPGA core board 101, and the connection of the FPGA test chassis 11 and the MRAM chip interposer 12, as a preferred embodiment, the FPGA core board 101 is connected to the FPGA test chassis 11 through a BTB connector. The MRAM chip adapter plate 12 is connected with the FPGA test backplane 11 through a BTB connector.

BTB Connectors, i.e., board-to-Board Connectors (Connectors), are a common connector product in the electronics market. Among various types of connector products, the BTB connector has the strongest transmission function and the widest application range, and can play a good role in various fields, especially industries such as communication networks, office equipment, intelligent home appliances, medical equipment, power systems, industrial manufacturing and the like. Along with the development of light, thin, short and small electronic products, the development of BTB connectors is also towards the development of small Pitch, multiple pins, low height and high frequency application, and is widely applied to the test of portable electronic products such as mobile phones, flat panels and the like.

As shown in fig. 2, in the implementation, part of the general purpose IO ports extended by the FPGA core board 101 are led out to the A1-A4 ports on the FPGA test chassis 11, and BTB connectors are installed on the A1-A4 ports. It can be understood that a large number of general IO ports meet the chip function test with a large number of pins; the BTB connector is arranged at the IO port on the FPGA test base plate 11, so that the detachable matching connection between the FPGA test base plate 11 and the FPGA core plate 101 is realized.

Fig. 3 is a structural diagram of an MRAM chip interposer according to an embodiment of the present application. As shown in FIG. 3, the MRAM chip adapter board 12 mounts a BTB connector at the B1-B4 ports. It should be noted that the relative positions and distances of the B1-B4 ports are identical to the positions and distances between A1-A4 on the FPGA test backplane 11. In this embodiment, the BTB connectors of the ports B1-B4 on the MRAM chip adapter plate 12 are detachably connected with the BTB connector slots of the ports A1-A4 on the FPGA test board 11.

On the basis of the above embodiment, in order to realize the internal analog power supply test of the MRAM chip, as a preferred embodiment, the FPGA test board 11 is provided with an ADC module and a DAC module;

the communication interface of the ADC module and the communication interface of the DAC module are connected to the FPGA test board 11 through the SPI interface, respectively.

Furthermore, as a preferred embodiment, the connection position of the communication interface of the ADC module and the FPGA test chassis 11 and the connection position of the communication interface of the DAC and the FPGA test chassis 11 are the same.

As shown in fig. 2, in the implementation, the communication interface of the ADC module is connected to the IO port of the FPGA core board 101 through a standard SPI interface. The SPI interface, serial peripheral interface (Serial Peripheral Interface), is a synchronous peripheral interface that allows a single-chip microcomputer to communicate with various peripheral devices in a serial fashion to exchange information.

Specifically, the measurement channel port of the ADC module is led out to the IO port on the FPGA test board 11, as shown in fig. 2, and the communication interface of the ADC module is connected to the "AO/AI" IO port at the A2 position. The 'AO/AI' interface is connected with an analog IO port on the MRAM chip adapter plate 12 through a BTB connector; the measurement channel of the ADC module will measure the value of the "AO" port in real time when testing the analog output signal of the MRAM chip.

The communication interface of the DAC module is connected with the IO port of the FPGA core board 101 through a standard SPI interface. The output channel of the DAC module is led out to an IO port on the FPGA test base plate 11, and as shown in fig. 2, the communication interface of the DAC module is connected with the 'AO/AI' IO port. When the MRAM chip is verified to need to be provided with voltage externally, the software controls the DAC module to output corresponding voltage values.

Furthermore, as a preferred embodiment, the FPGA test chassis 11 is provided with switch keys and a power interface; the switch key is used for controlling the on-off of the FPGA test base plate 11; the power interface P is used for connecting a power supply to supply power to the FPGA test chassis 11, the ADC module and the DAC module.

On the basis of the above embodiment, in order to better realize the connection between the MRAM chip interposer 12 and the MRAM chip, as a preferred embodiment, as shown in fig. 3, the MRAM chip interposer 12 is provided with a Socket for connecting the MRAM chip interposer 12 and the MRAM chip through the Socket.

Socket, in particular, in order to better realize connection between the MRAM chip and the MRAM chip adapter plate 12, according to needs, different MRAM chip adapter plates 12 with sockets are fabricated for MRAM chips with different sizes and different package types. The advantage of the MRAM chip adapter plate 12 for mounting Socket is that the MRAM chip to be tested can be taken and placed at any time.

Specifically, in the implementation process of the MRAM chip adapter plate 12, according to the packaging of the MRAM chip, a pad matched with the MRAM chip pin position is arranged on the MRAM chip adapter plate 12; each pad is led out to the FPGA test chassis 11 through a trace and is provided with a pad, specifically in the positions B1-B4 in fig. 3.

In addition, through holes are formed in the MRAM chip adapter plate 12 at the positions where the sockets are mounted, in the implementation, the sockets can be fixed on the MRAM chip adapter plate 12 by using screws, and the Socket pogos are in one-to-one contact with the bonding pads. After the MRAM chip is installed, the MRAM chip is connected with a control pin of the FPGA core plate 101. When testing the MRAM chip, the FPGA core board 101 transmits a test excitation signal of the IO port to the MRAM chip in the Socket on the MRAM chip adapter plate 12 through the BTB connector according to a test program time sequence so as to complete each function verification test; the output signals of the MRAM chip are also fed back to the FPGA core board 101 through the BTB connector for verification.

Fig. 4 is a block diagram of another MRAM chip interposer according to an embodiment of the present application. As shown in fig. 4, in order to realize simultaneous testing of a plurality of MRAM chips, the number of sockets is a plurality as a preferred embodiment.

In a specific implementation, a plurality of sockets are installed on the MRAM chip adapter 12, and the software configures signal control between the FPGA core board 101 and each Socket, so as to implement testing of a plurality of MRAM chips by the same MRAM chip adapter 12. In this embodiment, by arranging a plurality of sockets on the MRAM chip adapter plate 12, the number and efficiency of simultaneous testing of the chips can be improved, thereby reducing the testing cost of the MRAM chip.

In order to better understand the specific functions of the MRAM chip test system by those skilled in the art, in this embodiment, the specific process of the MRAM chip test system in performing the MRAM chip test will be further described with reference to the structures of fig. 2 and fig. 3.

Specifically, under the Vivado development environment of the upper computer 10 (a design suite, which is an integrated design environment issued by the company's siren of FPGA manufacturer), a project is created using a hardware description language, and the FPGA chip model is configured to be consistent with the model on the FPGA test chassis 11; according to the specification of the MRAM chip to be tested, general-purpose input/output (GPIO) is added in sequence, and the pin name, the input/output state and the data bit width are set. Wherein, MRAM chip analog pin sets up at "AO/AI" IO mouth. Setting GPIO states used by control signals of the ADC module and the DAC module; configuring the corresponding relation between the pins of the tested MRAM chip and the IO pins of the FPGA core plate 101 through the constraint file; and adding modules such as a serial port and the like, generating a bitfile file, and finishing engineering creation. And according to the test instruction of the tested MRAM chip, a test program module is customized, and the test program is downloaded to the FPGA core board 101 through a JTAG interface and debugged.

The chip test program comprises a chip test mode program and a serial port communication program. Setting the input or output state of the FPGA general IO port through software, and realizing the reading or writing operation of the data of the MRAM chip; the input/output is indicated by 1 when the input/output is high, and by 0 when the input/output is low. Each test mode program of the MRAM chip includes: initialization of an MRAM chip, writing of a data program (the data mode can be changed at will), comparing of a writing data error address with an error bit, writing and reading of each register configuration, cyclic writing and reading frequency configuration, internal analog voltage trimming (trim) test, external analog voltage configuration, complex functions combined by basic writing and reading operation according to requirements and the like.

The detection programs of the ADC module and the DAC module are configured, and the method is particularly realized that when the output voltage of the analog port of the MRAM chip changes, the ADC module measurement channel automatically acquires the voltage and displays the numerical value on the upper computer 10 after processing; the software controls the output voltage of the DAC module to provide a quantitative voltage input to the chip. Program modularization is carried out on all functions of the MRAM chip, namely, analog function test programs including but not limited to the MRAM chip are matched with the call of the ADC module and the DAC module detection program.

The serial communication program configuration comprises a start bit, an address bit, an operation bit, a termination bit and a baud rate, and a test mode instruction execution module is configured. The test mode instruction execution module is connected with each test mode program block of the chip in a matching way, for example: the instruction 01 calls the program block 1 to execute the test chip function 1; instruction 02 invokes block 2 to perform test chip function 2. The serial port tool of the host computer 10 sends instructions to gate the program blocks of each test mode respectively, or to select a full-flow automatic verification test. The test procedure is illustrated below:

for example, an excitation instruction "AA A1 00" is input to the FPGA core board 101 through the serial port of the upper computer 10, and when the serial port of the FPGA core board 101 receives the first data AA, it indicates that the instruction is successfully sent, and whether the second data is received correctly is continuously determined. For example, if A1 is used, that is, the A1 program block in the test module is called and the test is executed, the FPGA core board 101 sends the corresponding high-low level logic to each input pin of the MRAM chip according to the test timing signal, and reads the level value of each output pin of the MRAM chip to be tested according to the timing signal and performs verification and comparison with the preset value, and the test data fed back during and after the test is sent to the upper computer 10 through the serial port to be displayed and stored as a document. In addition, the non-fixed parameters such as specific test data mode, test address length, cycle write-read times, register trimming value and the like of the MRAM chip can be changed on line, and the test can be automatically executed according to the requirement.

In addition, MRAM chip analog functional verification is a very important step in the MRAM chip system verification stage, and is mainly divided into two main categories: the internal analog supply voltage is output and trimmed, and the external supply voltage is supplied to verify each function of the MRAM chip.

In specific implementation, the internal power supply voltage of the MRAM chip is tested, specifically, the analog power supply voltage values are respectively adjusted by modifying XX in a serial port tool window "AA A1 XX" of the upper computer 10, and 16 gears can also be automatically adjusted at the same time, wherein XX generally represents adjustment values of 0-15 gears from 00-0F. And the measured MRAM chip adapter plate 12 is arranged, and a measuring channel of the ADC module on the FPGA test bottom plate 11 is connected with an analog signal pin of the measured MRAM chip through a BTB connector. And correctly installing the tested MRAM chip, completing the power-on initialization of the chip, outputting a default voltage by each analog pin of the MRAM chip, and recording each analog voltage initial value by the ADC module measuring channel. When the analog power supply is modified, the ADC module converts the analog quantity into a digital quantity when detecting the voltage change, and the display voltage value is updated in real time at the serial port of the upper computer 10.

Furthermore, as each output channel of the DAC module is connected with the analog pin of the tested MRAM chip through the BTB connector, when each function of the tested MRAM chip needs to be verified when the external power supply voltage is required, the DAC module program is called to provide voltage for each analog pin of the chip, and the voltage value can be rapidly controlled in real time through software on line so as to debug the functions of the MRAM chip. In the application, the ADC module and the DAC module are integrated on the FPGA test base plate 11 at the same time, so that each analog function verification of the test MRAM chip is met, test instruments such as a desk-top multimeter and a direct current power supply are not needed, and the test cost is reduced.

The MRAM chip test system provided by the present utility model is described in detail above. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the utility model can be made without departing from the principles of the utility model and these modifications and adaptations are intended to be within the scope of the utility model as defined in the following claims.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims (10)

1. An MRAM chip test system, comprising: the device comprises an upper computer (10), an FPGA test bottom plate (11) provided with an FPGA core plate (101) and an MRAM chip adapter plate (12);

the upper computer (10) is connected with the FPGA test base plate (11) and is used for transmitting target test excitation to the FPGA core plate (101) on the FPGA test base plate (11);

the FPGA test base plate (11) is connected with the MRAM chip adapter plate (12) and is used for testing the MRAM chip on the MRAM chip adapter plate (12) by utilizing the FPGA core plate (101) according to the target test excitation and feeding back test information to the upper computer (10).

2.MRAM chip test system according to claim 1, characterized in that the FPGA test backplane (11) is provided with a USB Uart1 interface and is connected to the host computer (10) via the USB Uart1 interface for feeding back the test information.

3. MRAM chip test system according to claim 1, characterized in that the FPGA test backplane (11) is provided with a JTAG interface and is connected to the host computer (10) via the JTAG interface for receiving the target test stimulus.

4. MRAM chip test system according to claim 1, characterized in that the FPGA core board (101) is connected to the FPGA test backplane (11) by means of BTB connectors.

5. MRAM chip test system according to claim 1, characterized in that the MRAM chip interposer (12) is connected to the FPGA test backplane (11) by means of BTB connectors.

6. MRAM chip test system according to claim 1, characterized in that the FPGA test backplane (11) is provided with an ADC module and a DAC module;

the communication interface of the ADC module and the communication interface of the DAC module are respectively connected with the FPGA test bottom plate (11) through SPI interfaces.

7. MRAM chip test system according to claim 6, characterized in that the connection location of the communication interface of the ADC module with the FPGA test backplane (11) and the connection location of the communication interface of the DAC module with the FPGA test backplane (11) are the same.

8. MRAM chip test system according to claim 6, characterized in that the FPGA test backplane (11) is provided with switch keys and a power interface;

the switch key is used for controlling the on-off of the FPGA test base plate (11); the power interface is used for connecting a power supply to supply power for the FPGA test base plate (11), the ADC module and the DAC module.

9. MRAM chip test system according to claim 1, characterized in that the MRAM chip interposer (12) is provided with a Socket for connecting the MRAM chip interposer (12) with the MRAM chip via the Socket.

10. The MRAM chip test system of claim 9, wherein the number of sockets is a plurality.