TWI717222B - Prediction method of memory operation ability - Google Patents

Abstract

A method for predicting memory operating capability can be implemented by a memory operating capability predicting structure. By quickly changing the basic input/output system (BIOS) frequency and the delay of reading and writing sequence, the motherboard of the present invention can be tested The method can measure accurate voltage and current values, and is close to the practical method of using multiple dynamic random access memory (DRAM) integrated circuit (IC) chips together. In the operating mode, the operating range of each single DRAM IC chip is measured, so that the operating ability of each DRAM IC chip can be predicted, and then the operating ability test under various conditions can be effectively performed to improve the accuracy of classification.

Description

Prediction method of memory operation ability

The present invention relates to a method for predicting the operating capability of a memory, in particular to a motherboard testing method that can measure accurate voltage and current values, and in particular to a method for quickly changing the basic input/output system (Basic Input/Output System). , BIOS) frequency and read/write timing delay, can measure the operating range of each single dynamic random access memory (DRAM) integrated circuit (IC) chip, so that Predict the operation ability of each DRAM IC chip, and then can effectively carry out the operation ability test under various conditions, and improve the accuracy of classification.

In the manufacturing process of memory circuits and devices, such as dynamic random access memory (DRAM), it is necessary to test the memory circuits or devices. Usually, automatic test equipment (ATE) coupled to the memory circuit or device (ie, device under test (DUT)) is used to complete this test. The ATE generates certain predetermined test signals and transmits them to the DUT and the response signals are received from the DUT and the DUT is evaluated based on the responses.

At present, ATE itself already provides accurate voltage, meter and timing control, which is basically a classification of automated testing. However, because the test equipment like ATE is very expensive, the high test cost weakens the price competitiveness; moreover, the operation ability of every single integrated circuit (IC) obtained from the test results is not in the operating mode The test is not able to meet the needs of actual use.

In addition, in addition to ATE, the conventional technologies are relatively cheap to use and in actual operation. Use the motherboard in the mode to test multiple ICs together. This method is closer to the way that ICs are actually used to operate applications, so the motherboard is the test method that more people choose to use; however, this method has the most criticized shortcoming Because the voltage is not accurate enough and the current cannot be measured, it is impossible to know which of the many ICs consumes more power. In terms of timing control, only the frequency can be operated and cannot be tested. Therefore, although the motherboard is a test performed in the actual operating mode, the classification is not accurate enough.

In this regard, although the ATE method is already a standard practice in the field of memory testing, the cost of the test device is still very high, and each IC is not tested in the operating mode, and the motherboard is in Tested in operating mode but the classification is not accurate enough. Therefore, ordinary users cannot meet the needs of users in actual use.

The main purpose of the present invention is to overcome the above-mentioned problems encountered by the prior art and provide a way to quickly change the BIOS frequency and delay time (Column Address Strobe latency or CAS latency, CL) so that the motherboard testing method of the present invention can be measured. The accurate voltage value and current value are measured, and it is close to the practical method of using multiple DRAM IC chips together. The operating range of each single DRAM IC chip can be measured, so as to predict the size of each DRAM IC chip. Operation ability, which can effectively carry out operation ability test under various conditions, and improve the prediction method of memory operation ability of classification accuracy value.

In order to achieve the above objective, the present invention is a method for predicting memory operating capability, which is implemented by a memory operating capability predicting structure. The method includes the following steps: Step 1: Put a number of memory modules under test (device under test) , DUT) is plugged into a motherboard; Step 2: Start an input module on the motherboard, read the basic input/output system (BIOS) with memory margin test function into how to test the standby The memory module is tested, and the memory margin test is the memory test mode in a specific timing operation mode; Step 3: Start a switch module on the motherboard, The memory module under test switches the measurement mode according to one of the measured voltage or the measured current, so that each memory module under test performs the memory margin test; Step 4: Start a measurement on the motherboard The measurement module measures a memory characteristic of each memory module under test in a specific timing operation mode. The measurement module includes a voltage measurement unit and a current measurement unit. In the voltage measurement mode, the voltage measurement unit can measure the power supply voltage of each of the memory modules under test, and in the measurement current mode, the current measurement unit can measure the power supply voltage flowing through each A current of the memory module to be tested, and the memory characteristic of each memory module to be tested is fed back to a processing module on the motherboard, wherein the memory characteristic includes operating mode at a specific timing The voltage information and current information obtained by the measurement; and Step 5: The processing module reads the measurement module to measure a memory characteristic of each memory module under test in a specific timing operation mode, and passes The memory margin test is combined with the voltage and current measurement. The operating range of each memory module under test is recorded through different BIOS frequency settings and different read/write timing delays. The current operational range of the memory module is quickly screened and classified, so that each memory module under test can be precisely operated under a specific timing operation mode to obtain each memory under test The precise value of the module classification interval is used to predict the operation capability of each memory module under test.

In the foregoing embodiment of the present invention, the switching module is connected to the input module and each of the memory modules to be tested, the measurement module is connected to the switching module, and the processing module is connected to the Measurement module connection.

In the above-mentioned embodiment of the present invention, each of the memory modules under test can be a dynamic random access memory (DRAM) integrated circuit (IC) chip.

In the foregoing embodiment of the present invention, the processing module may be a central processing unit (CPU).

In the above embodiment of the present invention, the memory margin test is performed at a specific timing 3200 Memory test mode in MHz, 3600MHz or 4000MHz operation mode.

In the above embodiment of the present invention, the voltage measurement unit measures the power supply voltage of each memory module under test from small to large, and the current measurement unit measures the flow through each memory under test The body module has a current from small to large.

In the above-mentioned embodiment of the present invention, the processing module further includes a storage unit for recording the current operational range of each memory module under test in the storage unit.

100: Motherboard

1: Memory module to be tested

2: Input module

3: Switch module

4: Measurement module

41: Voltage measurement unit

42: Current measurement unit

5: Processing module

51: storage unit

s1~s5: Step 1~Step 5

Figure 1 is a schematic flow diagram of the present invention.

Figure 2 is a block diagram of the present invention.

Please refer to "FIG. 1 and FIG. 2", which are the schematic flow diagram of the present invention and the block schematic diagram of the present invention, respectively. As shown in the figure: the present invention is a method for predicting memory operating capability, implemented by a memory operating capability predicting structure, which includes several memory modules under test (device under test, DUT)1, and an input module 2. Consists of a switching module 3, a measurement module 4, and a processing module 5. The method for predicting memory operation capability includes the following steps:

Step one s1: Connect several DUTs 1 to a motherboard 100. Each DUT 1 can be a dynamic random access memory ( Dynamic random access memory (DRAM) integrated circuit (IC) chips are DRAM IC chip 1 to DRAM IC chip N.

Step two s2: Start the input module 2 on the motherboard 100, and use the input module 2 to connect a basic input/output system (Basic Input/Output System, BIOS) reads how to test each memory module 1, and the memory margin test is a memory test mode under a specific timing operation mode.

Step three s3: Start the switch module 3 on the motherboard 100 connecting the input module 2 and each memory module 1 under test, and measure the voltage or quantity for each memory module 1 under test One of the currents is measured and the measurement mode is switched so that each memory module 1 to be tested performs the memory margin test.

Step 4: s4: Start the measurement module 4 connected to the switching module 3 on the motherboard 100, and measure each memory module 1 under test in a specific timing operation mode through the measurement module 4 A memory characteristic. The measurement module 4 includes a voltage measurement unit 41 and a current measurement unit 42. When switched to the voltage measurement mode, the voltage measurement unit 41 can measure each of the to-be-measured The memory module 1 has a power supply voltage, and when switched to the current measurement mode, a current flowing through each memory module under test can be measured by the current measurement unit 42, and each of the The memory characteristics of the memory module 1 to be tested are fed back to the processing module 5 on the motherboard 100, wherein the memory characteristics include voltage information and current information measured in a specific timing operation mode.

Step 5 s5: The processing module 5 is connected to the measurement module 4, which can be a central processing unit (CPU), and the processing module 5 reads the measurement module 4 at a specific time sequence. In the operation mode, a memory characteristic of each memory module 1 under test is measured. Through the combination of the memory margin test and the voltage and current measurement, each memory module 1 under test is operable The interval is based on different BIOS frequency settings and different read and write timing delays, and records the current operational interval range of each memory module 1 under test, so as to quickly filter and classify each memory under test. The module 1 can perform a single precise operation in the operation mode of a specific time sequence to obtain the accurate value of the classification interval of each memory module 1 under test, so as to predict each memory module 1 under test. The operation ability. If so, a new method for predicting memory operation capability is formed by the above-disclosed process.

In a specific embodiment, the memory margin test provided by the present invention is performed at a specific time sequence, for example, a memory test mode in an operating mode of 3200MHz, 3600MHz or 4000MHz. In actual use, a measurement module 4 for detecting the memory characteristics of each memory module 1 under test can be provided in front of each memory module 1 under test, which includes a voltage measurement unit 41 And the current measurement unit 42 measures the voltage information and current information of each memory module 1 under test, including the measurement by the voltage measurement unit 41 of each memory module 1 under test from small to large A power supply voltage, and the current measuring unit 42 measures a current flowing through each memory module 1 under test from small to large. Moreover, each measurement module 4 is directly connected to the processing module 5, so that the processing module 5 can know the memory characteristics of each memory module under test 11; for example, when the timing is set by the BIOS In the 4000MHz operating mode, the measurement module 4 detects whether each memory module 1 under test can read and write the voltage and current of each memory module 1 under test at this timing during the test Information, if the memory module 1 under test can be successfully read and written, it means that it can pass the test in the 4000MHz operation mode. Therefore, the memory module 1 under test that successfully reads and writes can know its operating range at 4000 MHz, and in this way, the voltage value and current value in each operation mode of a specific time sequence can be known. Then the processing module 5 records the remaining margin of each memory module 1 under test, that is, writes the operating range of each memory module 1 under test into a storage unit 51 for recording .

In the present invention, some specific parameters (for example, reference voltage (VREF)) in operation can be measured and compared, and DRAM IC chips can be classified by quickly changing BIOS frequency and CL settings. Each DRAM IC chip can be The operation interval is based on different frequency settings and different read and write timing delays, so that each DRAM IC chip can be operated at present. Through such fast screening, fast classification is achieved, so that each single chip DRAM IC chips can be precisely operated in a single chip in the operation mode, and the precise value of their classification interval can be found, so as to predict the operation ability of each DRAM IC chip, so that in practice, each DRAM IC chip can have Higher operating efficiency. Thus, by quickly changing the BIOS frequency and CL, the motherboard test method of the present invention can be measured To the precise voltage and current values, and it is close to the practical way that multiple DRAM IC chips are used together, and the operating range of each single DRAM IC chip can be measured, so that it can effectively operate under various conditions Ability test to improve the accuracy of classification.

In summary, the present invention is a method for predicting memory operation capability, which can effectively improve the various shortcomings of conventional use. By quickly changing the BIOS frequency and the delay of reading and writing sequence, the motherboard testing method of the present invention Accurate voltage and current values can be measured, and it is close to the way that multiple dynamic random access memory (DRAM) integrated circuit (IC) chips are used together in practice, and each single DRAM IC can be measured The operating range of the chip can thus predict the operating capability of each DRAM IC chip, so that the operating capability test under various conditions can be effectively performed, and the accurate value of classification can be improved, so that the production of the present invention can be more advanced, more practical, and more practical. It is more in line with the needs of users, and it has indeed met the requirements of an invention patent application.

However, the above are only preferred embodiments of the present invention, and should not be used to limit the scope of implementation of the present invention; therefore, all simple equivalent changes and modifications made in accordance with the scope of the patent application of the present invention and the content of the description of the invention , Should still fall within the scope of the invention patent.

100: Motherboard

1: Memory module to be tested

2: Input module

3: Switch module

4: Measurement module

41: Voltage measurement unit

42: Current measurement unit

5: Processing module

51: storage unit

Claims (7)

A method for predicting memory operation capability is implemented by a structure for predicting memory operation capability. The method includes the following steps: Step 1: Connecting a number of memory modules (device under test, DUT) to a motherboard Above; Step 2: Start an input module on the motherboard, read the basic input/output system (BIOS) with memory margin test function into how to test the memory module under test, and the memory The margin test is a memory test mode under a specific timing operation mode; Step 3: Start a switch module on the motherboard, and switch each memory module under test according to one of the measured voltage or the measured current The measurement mode enables each memory module to be tested to perform the memory margin test; Step 4: Start a measurement module on the motherboard to measure each memory module to be tested in a specific timing operation mode A memory characteristic of the module. The measurement module includes a voltage measurement unit and a current measurement unit. When switched to the voltage measurement mode, the voltage measurement unit can measure each memory under test. One of the modules has a power supply voltage, and when switched to the current measurement mode, a current flowing through each memory module under test can be measured by the current measurement unit, and each memory under test The memory characteristics of the module are fed back to a processing module on the motherboard, where the memory characteristics include voltage information and current information measured in a specific timing operation mode; and step 5: the processing module reads Take the measurement module to measure the memory characteristics of each memory module under test in a specific time sequence operation mode, and combine the memory margin test with the voltage and current measurement to use each The operating range of the memory module to be tested is recorded through different BIOS frequency settings and different read/write timing delays. The current operating range of each memory module to be tested is recorded to quickly filter and classify. Each memory module to be tested can be precisely operated by a single chip in the operation mode of a specific time sequence to obtain the accurate value of the classification interval of each memory module to be tested, in order to predict Prediction (prediction) the operation capability of each memory module under test. According to the method for predicting memory operation capability described in the first item of the patent application, the switching module is connected to the input module and each of the memory modules to be tested, and the measurement module is connected to the switching Module connection, the processing module is connected with the measurement module. According to the method for predicting memory operation capability described in the first item of the patent application, each of the memory modules to be tested can be a dynamic random access memory (DRAM) integrated circuit (integrated circuit). circuit, IC) chip. According to the method for predicting memory operation capability described in the first item of the scope of patent application, the processing module can be a central processing unit (CPU). According to the method for predicting memory operation capability described in the first item of the scope of patent application, the memory margin test is a memory test mode under a specific time sequence of 3200MHz, 3600MHz or 4000MHz operation mode. According to the method for predicting memory operation capability described in the first item of the patent application, the voltage measurement unit measures the power supply voltage of each memory module under test from small to large, and the current measurement The unit measures the current flowing through each memory module under test from small to large. According to the method for predicting the operation capability of the memory according to the first item of the scope of patent application, the processing module further includes a storage unit for recording the current operational range of each memory module under test to the In the storage unit.

Images