WO2021212984A1

WO2021212984A1 - On-chip measurement circuit and measurement method for low-voltage sram time parameters

Info

Publication number: WO2021212984A1
Application number: PCT/CN2021/076791
Authority: WO
Inventors: 蔡志匡; 余昊杰; 周正; 吕凯; 王子轩; 谢祖帅; 郭静静; 郭宇锋
Original assignee: 南京邮电大学
Priority date: 2020-04-20
Filing date: 2021-02-19
Publication date: 2021-10-28
Also published as: CN111210865A; DE202021102005U1; CN111210865B

Abstract

An on-chip measurement circuit and measurement method for low-voltage SRAM time parameters, the measurement circuit comprising a measurement control module and a time measurement module, wherein the time measurement module is connected to the measurement control module; the time measurement module is controlled by means of the measurement control module; the measurement control module has a memory-based built-in self-test module; the measurement control module comprises BIST control logic, BIST test vector generation logic, and a time measurement control module; and the time measurement module comprises a delay unit, a comparator, and an accumulator. By means of adding a measurement control module and a time measurement module, a large quantity of SRAMs are tested in a large-scale chip. While performing MBIST testing, the measurement of the access time of each memory unit of the SRAM is also implemented, and the access time for one or more SRAMs is measured at the same time, thus achieving "full speed" self-measurement and accurate measurement results, reducing dependence on ATE, and effectively reducing test costs.

Description

A low-voltage SRAM time parameter on-chip measurement circuit and measurement method

Technical field

The invention relates to the technical field of integrated circuit testing, in particular to an on-chip measurement circuit and a measurement method for low-voltage SRAM time parameters.

Background technique

In the tide of informatization, artificial intelligence, Internet of Things, big data, and blockchain are mutually empowering, industrial optimization and upgrading, and rapid economic development. Data plays a central role in the development of these high-tech industries, which of course puts forward higher requirements for electronic information storage products-high density, high speed, low power consumption, low cost, etc. FLASH, DRAM, and SRAM storage are the mainstream in the current market. DRAM has a high density, a relatively simple storage structure using capacitors, low latency, high performance, and durability close to unlimited access, and low power consumption. SRAM has a very fast read and write speed, and data can be sent to the CPU for processing in the shortest time and quickly output to the outside, so SRAM is widely used in various occasions.

The contradiction between low power consumption and high speed of the chip, the industry has always believed that the balance between the two is the most critical solution not to avoid this contradiction. In the low-power SRAM design, reducing the power supply voltage is the most effective. In the low-voltage design, the pursuit of lower operating voltage and power consumption will inevitably impose stricter constraints on the performance of SRAM. SRAM access time is one of the main time parameters of performance. Usually, the adverse effects of external detection on high-performance circuits, as well as the magnitude of the parameters and errors that need to be considered, make it very difficult to measure with external equipment. Therefore, for testers or external devices to measure accurate access time, an on-chip solution with built-in measurement is usually required. There are many test schemes for measuring the time parameters of SRAM, but at present, the proportion of SRAM on the chip is increasing, and there are more and more types of SRAM with different specifications, especially the demand for low power consumption. The performance requirements of the time parameters of the voltage SRAM are more demanding. The traditional solutions can no longer meet the current time parameter measurement requirements. It is extremely important to explore a large-scale, large-scale, accurate and convenient method.

Summary of the invention

In view of the shortcomings of the prior art, the purpose of the present invention is to provide a low-voltage SRAM time parameter on-chip measurement circuit and measurement method. By adding a measurement control module and a time measurement module, the large-scale in-chip mass SRAM test can be achieved. While carrying on the MBIST test, also realized the measurement of the access time of each storage unit of SRAM.

The present invention provides an on-chip measurement circuit for low-voltage SRAM time parameters, which includes a measurement control module and a time measurement module, the time measurement module is connected to the measurement control module, and the time measurement module is controlled by the measurement control module. The measurement control module is based on A self-test module is built in the memory. The measurement control module includes BIST control logic, BIST test vector generation logic, and a time measurement control module. The time measurement module includes a delay unit, a comparator, and an accumulator.

A further improvement is that: the time measurement control module is a multiplexer that selects or shields the signal, and the module connects the input SRAM test vector generated by the built-in memory self-test and the result output from the SRAM to be tested to the time measurement module.

A further improvement is that the time measurement module includes a total of 15 stages of delay units D0-D14 connected in series, and the system clock CLK is connected to D0. The signal CLK generates signals CLK_1-CLK_15 after D0-D14. The delay unit is composed of two-stage inverters. The delay of the first-stage delay unit D0 is 1 ns, and the delays of the other delay units D1-D14 are all 20 ps.

A further improvement is that the clock terminals of the comparators C0-C15 receive the measured SRAM output signal Q_0, the C0 data terminal is connected to the system clock signal, the C1 data terminal is connected to the system clock via the D0 delay unit signal CLK_1, and the C2 data terminal is connected to the system clock via D0, D1 delay unit signal CLK_2, and so on, CLK, CLK_1-CLK_15 are respectively connected to the data terminals of the comparators C0-C15, and then the results obtained by the comparator Z0-Z15 are input to the accumulator (ACC), and finally the accumulator result OUT output.

The present invention also provides a measurement method of the low-voltage SRAM time parameter on-chip measurement circuit, the method includes the following steps:

Step 1: Start MBIST and time measurement, set bist_en and bitm_en to "1";

Step 2: Capture the output data signal Q_0 of the SRAM under test and the system clock CLK;

Step 3: CLK generates CLK_1-CLK_15 through delay units D0-D14;

Step 4: The comparator samples the data terminal signal until the 16-level comparator has finished sampling;

Step 5: The accumulator counts and encodes the number of level "1" in the sampled signal, and finally outputs the result to the off-chip for calculation.

A further improvement is that the calculation formula in the fifth step is ΔT=1+(N-1)*0.02, where N is the final output result of the accumulator (N<15), and the time unit is nanoseconds.

On the basis of the MBIST (Memory Built-in Self Test) circuit, a measurement control module and a time measurement module are added. The measurement control module includes a BIST controller, a BIST test vector generator, and a time measurement control circuit. Among them, the time measurement control circuit is used to control the signal gating between the memory test circuit and the time measurement module. While performing the BIST test, the access time of the SRAM can be measured.

MBIST is a mature technical solution for memory testing in the industry. The test vector required for time parameter measurement is write 0 to read 0, write 1 to read 1. Such test vectors generally exist in the MBIST algorithm. Therefore, the MBIST test vector set is sufficient The test vector required for time parameter measurement. In view of the integration of SRAMs of different specifications and large quantities of SRAMs in the chip, designing a control module separately for the selection of multiple SRAMs will increase the area overhead, and it is more appropriate to share this part of the logic with MBIST. In summary, it is undoubtedly simpler and the least costly to carry out SRAM time parameter measurement design on the basis of the MBIST test scheme.

The time measurement control module is a multiplexer that selects or shields the signal. The module connects the input SRAM test vector generated by the built-in memory and the result output from the SRAM to be tested to the time measurement module. The outside world controls by communicating with the BIST controller (bist_en=1, bitm_en=1), starts the controller to enter the time parameter measurement mode, the BIST controller starts the BIST test vector generator, and generates a series of pre-designed test stimuli based on the algorithm , Applied to the circuit under test, and the time measurement control circuit controls the signal gating between the memory test circuit and the time measurement module, and inputs the response (Q_0) of the SRAM under test to the time measurement module.

The beneficial effects of the present invention are: by adding a measurement control module and a time measurement module, a large-scale SRAM test in a large-scale chip is performed. While the MBIST test is performed, it also realizes the measurement of the access time of each storage unit of the SRAM. Or multiple SRAMs can measure the access time at the same time to achieve "full speed" self-measurement, the measurement results are more accurate, and the dependence on ATE is reduced, which effectively reduces the cost of testing.

Description of the drawings

Figure 1 is a schematic diagram of the overall measurement circuit of the present invention.

Fig. 2 is a schematic diagram of the measurement control module of the present invention.

Fig. 3 is a schematic diagram of the time measurement module of the present invention.

Fig. 4 is a schematic diagram of the comparator of the present invention.

Fig. 5 is a schematic diagram of the measurement process of the present invention.

Fig. 6 is a schematic diagram of an example access time parameter measurement circuit of the present invention.

Fig. 7 is a schematic diagram of measurement waveforms of an example circuit of the present invention.

Detailed ways

In order to deepen the understanding of the present invention, the present invention will be described in further detail below in conjunction with examples. The examples are only used to explain the present invention and do not constitute a limitation on the protection scope of the present invention. As shown in Figure 1, this embodiment provides a low-voltage SRAM time parameter on-chip measurement circuit, including a measurement control module and a time measurement module, the time measurement module is connected to the measurement control module, and the time measurement is controlled by the measurement control module Module, the measurement control module is based on a memory built-in self-test module, the measurement control module includes BIST control logic, BIST test vector generation logic, and a time measurement control module, and the time measurement module includes a delay unit, a comparator, and an accumulator.

The measurement control module is shown in Figure 2. The time measurement control module is a multiplexer that selects or shields the signal. The module is connected to the built-in memory to input the SRAM test vector generated by the test and the result output from the SRAM to be tested to the time Measurement module. The outside world controls by communicating with the BIST controller (bist_en=1, bitm_en=1), starts the controller to enter the time parameter measurement mode, the BIST controller starts the BIST test vector generator, and generates a series of pre-designed test stimuli based on the algorithm , Applied to the circuit under test, and the time measurement control circuit controls the signal gating between the memory test circuit and the time measurement module, and inputs the response (Q_0) of the SRAM under test to the time measurement module.

The time measurement module is shown in Figure 3. In view of accuracy and area considerations, the time measurement module includes a total of 15 delay units D0-D14 in series, the system clock CLK is connected to the D0 delay unit, and the signal CLK generates the signal CLK_1-CLK_15 after D0-D14 , The delay unit is composed of two-stage inverters, the first-stage delay unit D0 has a delay of 1 ns, and the other delay units D1-D14 have delays of 20 ps. In the design, more delay units can be added according to the requirements of accuracy and area. The access time parameter of the measurement object selected in this patent is slightly larger than 1ns, so the combination of 1ns (D0) and 20ps (D1-D14) is finally selected. The delayed unit can be modified according to the actual measurement object.

The clock terminals of the comparators C0-C15 and C0-C15 receive the test SRAM output signal Q_0, the C0 data terminal is connected to the system clock signal CLK, the C1 data terminal is connected to the system clock via the D0 delay unit signal CLK_1, and the C2 data terminal is connected to the system clock via D0. , D1 delay unit signal CLK_2, and so on, CLK, CLK_1-CLK_15 are respectively connected to the data terminals of the comparators C0-C15. The specific working waveform of the comparator is shown in Figure 4. When the clock pulse is over, the trigger can record how many time units are delayed, that is, the time that the trigger clock terminal signal lags behind the trigger data terminal signal. The results Z0-Z15 obtained by the comparator are input to the accumulator (ACC). The accumulator is realized by a counter. The accumulator counts the number of level "1" in the sampled signal, and then encodes the output result according to the designed delay unit information The SRAM access time (T _access ) can be determined very intuitively.

The measurement steps are shown in the flowchart in Figure 5:

The first step is to start MBIST and time measurement, and set bist_en and bitm_en to "1".

The second step is to capture the output data signal Q_0 of the SRAM under test and the system clock CLK.

In the third step, CLK generates CLK_1-CLK_15 through delay units D0-D14, respectively.

In the fourth step, the comparator samples the data terminal signal until the 16-level comparator has finished sampling.

In the fifth step, the accumulator counts and encodes the number of level "1" in the sampled signal, and finally outputs the result to the off-chip for calculation. The measurement calculation formula: ΔT=1+(N-1)*0.02, where N is the final output result of the accumulator (N<15), and the time unit is nanoseconds.

In order to verify the validity of the measurement circuit, the verification object is selected as a low-voltage 6T SRAM (capacity: 32x16), the row address is 4, and the column address is 8. Figure 6 shows the access time parameter measurement circuit for verifying this method example. Figure 7 is the actual measured waveform of the first memory cell of the first address. According to the measurement calculation method in step 5, the following formulas are listed and the result is obtained: ΔT=1+(10-1)*0.02=1.180ns .

Claims

An on-chip measurement circuit for low-voltage SRAM time parameters, characterized in that it comprises a measurement control module and a time measurement module, the time measurement module is connected to the measurement control module, and the time measurement module is controlled by the measurement control module, the measurement control module Based on the memory built-in self-test module, the measurement control module includes BIST control logic, BIST test vector generation logic, and time measurement control module. The time measurement module includes a delay unit, a comparator, and an accumulator.
The on-chip measurement circuit for low-voltage SRAM time parameters according to claim 1, wherein the time measurement control module is a multiplexer, which selects or shields signals, and the module is connected to the built-in self-test of the memory. Input the test vector of the SRAM to be tested and the result output from the SRAM to be tested to the time measurement module.
The on-chip measurement circuit for low-voltage SRAM time parameters according to claim 1, wherein the time measurement module includes a total of 15 delay units D0-D14 connected in series, the system clock CLK is connected to D0, and the signal CLK passes through D0- Signals CLK_1-CLK_15 are generated after D14, where the delay unit is composed of two-stage inverters, the first-stage delay unit D0 has a delay of 1 ns, and the other delay units D1-D14 have delays of 20 ps.
The on-chip measurement circuit for low-voltage SRAM time parameters according to claim 3, characterized in that: the clock terminals of the comparators C0-C15 receive the test SRAM output signal Q_0, the C0 data terminal is connected to the system clock signal, and the C1 data terminal The system clock is connected to the D0 delay unit signal CLK_1, the C2 data terminal is connected to the system clock through the D0, D1 delay unit signal CLK_2, and so on, CLK, CLK_1-CLK_15 are respectively connected to the data terminals of the comparators C0-C15, and then the comparator is The results Z0-Z15 are input to the accumulator, and finally the accumulator result OUT is output.
A method for measuring a low-voltage SRAM time parameter on-chip measurement circuit according to any one of claims 1 to 4, wherein the method comprises the following steps:

Step 1: Start MBIST and time measurement, set bist_en and bitm_en to "1";

Step 2: Capture the output data signal Q_0 of the SRAM under test and the system clock CLK;

Step 3: CLK generates CLK_1-CLK_15 through delay units D0-D14;

Step 4: The comparator samples the data terminal signal until the 16-level comparator has finished sampling;

Step 5: The accumulator counts and encodes the number of level "1" in the sampled signal, and finally outputs the result to the off-chip for calculation.
The measurement method of a low-voltage SRAM time parameter on-chip measurement circuit as claimed in claim 5, characterized in that: the calculation formula in step 5 is ΔT=1+(N-1)*0.02, where N is The final output result of the accumulator (N<15), and the time unit is nanoseconds.