WO2021212984A1 - Circuit de mesure sur puce et procédé de mesure destiné à des paramètres de temps de mémoire vive statique (sram) basse tension - Google Patents

Circuit de mesure sur puce et procédé de mesure destiné à des paramètres de temps de mémoire vive statique (sram) basse tension Download PDF

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WO2021212984A1
WO2021212984A1 PCT/CN2021/076791 CN2021076791W WO2021212984A1 WO 2021212984 A1 WO2021212984 A1 WO 2021212984A1 CN 2021076791 W CN2021076791 W CN 2021076791W WO 2021212984 A1 WO2021212984 A1 WO 2021212984A1
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Prior art keywords
measurement
time
clk
module
control module
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PCT/CN2021/076791
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English (en)
Chinese (zh)
Inventor
蔡志匡
余昊杰
周正
吕凯
王子轩
谢祖帅
郭静静
郭宇锋
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南京邮电大学
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Publication of WO2021212984A1 publication Critical patent/WO2021212984A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

Definitions

  • the invention relates to the technical field of integrated circuit testing, in particular to an on-chip measurement circuit and a measurement method for low-voltage SRAM time parameters.
  • DRAM has a high density, a relatively simple storage structure using capacitors, low latency, high performance, and durability close to unlimited access, and low power consumption.
  • SRAM has a very fast read and write speed, and data can be sent to the CPU for processing in the shortest time and quickly output to the outside, so SRAM is widely used in various occasions.
  • the purpose of the present invention is to provide a low-voltage SRAM time parameter on-chip measurement circuit and measurement method.
  • the large-scale in-chip mass SRAM test can be achieved.
  • the MBIST test While carrying on the MBIST test, also realized the measurement of the access time of each storage unit of SRAM.
  • the present invention provides an on-chip measurement circuit for low-voltage SRAM time parameters, which includes a measurement control module and a time measurement module, the time measurement module is connected to the measurement control module, and the time measurement module is controlled by the measurement control module.
  • the measurement control module is based on A self-test module is built in the memory.
  • the measurement control module includes BIST control logic, BIST test vector generation logic, and a time measurement control module.
  • the time measurement module includes a delay unit, a comparator, and an accumulator.
  • a further improvement is that: the time measurement control module is a multiplexer that selects or shields the signal, and the module connects the input SRAM test vector generated by the built-in memory self-test and the result output from the SRAM to be tested to the time measurement module.
  • the time measurement module includes a total of 15 stages of delay units D0-D14 connected in series, and the system clock CLK is connected to D0.
  • the signal CLK generates signals CLK_1-CLK_15 after D0-D14.
  • the delay unit is composed of two-stage inverters. The delay of the first-stage delay unit D0 is 1 ns, and the delays of the other delay units D1-D14 are all 20 ps.
  • a further improvement is that the clock terminals of the comparators C0-C15 receive the measured SRAM output signal Q_0, the C0 data terminal is connected to the system clock signal, the C1 data terminal is connected to the system clock via the D0 delay unit signal CLK_1, and the C2 data terminal is connected to the system clock via D0, D1 delay unit signal CLK_2, and so on, CLK, CLK_1-CLK_15 are respectively connected to the data terminals of the comparators C0-C15, and then the results obtained by the comparator Z0-Z15 are input to the accumulator (ACC), and finally the accumulator result OUT output.
  • ACC accumulator
  • the present invention also provides a measurement method of the low-voltage SRAM time parameter on-chip measurement circuit, the method includes the following steps:
  • Step 1 Start MBIST and time measurement, set bist_en and bitm_en to "1";
  • Step 2 Capture the output data signal Q_0 of the SRAM under test and the system clock CLK;
  • Step 3 CLK generates CLK_1-CLK_15 through delay units D0-D14;
  • Step 4 The comparator samples the data terminal signal until the 16-level comparator has finished sampling
  • Step 5 The accumulator counts and encodes the number of level "1" in the sampled signal, and finally outputs the result to the off-chip for calculation.
  • the measurement control module includes a BIST controller, a BIST test vector generator, and a time measurement control circuit. Among them, the time measurement control circuit is used to control the signal gating between the memory test circuit and the time measurement module. While performing the BIST test, the access time of the SRAM can be measured.
  • MBIST is a mature technical solution for memory testing in the industry.
  • the test vector required for time parameter measurement is write 0 to read 0, write 1 to read 1.
  • Such test vectors generally exist in the MBIST algorithm. Therefore, the MBIST test vector set is sufficient
  • the test vector required for time parameter measurement In view of the integration of SRAMs of different specifications and large quantities of SRAMs in the chip, designing a control module separately for the selection of multiple SRAMs will increase the area overhead, and it is more appropriate to share this part of the logic with MBIST. In summary, it is undoubtedly simpler and the least costly to carry out SRAM time parameter measurement design on the basis of the MBIST test scheme.
  • the time measurement control module is a multiplexer that selects or shields the signal.
  • the module connects the input SRAM test vector generated by the built-in memory and the result output from the SRAM to be tested to the time measurement module.
  • the beneficial effects of the present invention are: by adding a measurement control module and a time measurement module, a large-scale SRAM test in a large-scale chip is performed. While the MBIST test is performed, it also realizes the measurement of the access time of each storage unit of the SRAM. Or multiple SRAMs can measure the access time at the same time to achieve "full speed" self-measurement, the measurement results are more accurate, and the dependence on ATE is reduced, which effectively reduces the cost of testing.
  • Figure 1 is a schematic diagram of the overall measurement circuit of the present invention.
  • Fig. 2 is a schematic diagram of the measurement control module of the present invention.
  • Fig. 3 is a schematic diagram of the time measurement module of the present invention.
  • Fig. 4 is a schematic diagram of the comparator of the present invention.
  • Fig. 5 is a schematic diagram of the measurement process of the present invention.
  • Fig. 6 is a schematic diagram of an example access time parameter measurement circuit of the present invention.
  • Fig. 7 is a schematic diagram of measurement waveforms of an example circuit of the present invention.
  • this embodiment provides a low-voltage SRAM time parameter on-chip measurement circuit, including a measurement control module and a time measurement module, the time measurement module is connected to the measurement control module, and the time measurement is controlled by the measurement control module Module, the measurement control module is based on a memory built-in self-test module, the measurement control module includes BIST control logic, BIST test vector generation logic, and a time measurement control module, and the time measurement module includes a delay unit, a comparator, and an accumulator.
  • MBIST is a mature technical solution for memory testing in the industry.
  • the test vector required for time parameter measurement is write 0 to read 0, write 1 to read 1.
  • Such test vectors generally exist in the MBIST algorithm. Therefore, the MBIST test vector set is sufficient
  • the test vector required for time parameter measurement In view of the integration of SRAMs of different specifications and large quantities of SRAMs in the chip, designing a control module separately for the selection of multiple SRAMs will increase the area overhead, and it is more appropriate to share this part of the logic with MBIST. In summary, it is undoubtedly simpler and the least costly to carry out SRAM time parameter measurement design on the basis of the MBIST test scheme.
  • the measurement control module is shown in Figure 2.
  • the time measurement control module is a multiplexer that selects or shields the signal.
  • the module is connected to the built-in memory to input the SRAM test vector generated by the test and the result output from the SRAM to be tested to the time Measurement module.
  • the time measurement module is shown in Figure 3.
  • the time measurement module includes a total of 15 delay units D0-D14 in series, the system clock CLK is connected to the D0 delay unit, and the signal CLK generates the signal CLK_1-CLK_15 after D0-D14 ,
  • the delay unit is composed of two-stage inverters, the first-stage delay unit D0 has a delay of 1 ns, and the other delay units D1-D14 have delays of 20 ps. In the design, more delay units can be added according to the requirements of accuracy and area.
  • the access time parameter of the measurement object selected in this patent is slightly larger than 1ns, so the combination of 1ns (D0) and 20ps (D1-D14) is finally selected.
  • the delayed unit can be modified according to the actual measurement object.
  • the clock terminals of the comparators C0-C15 and C0-C15 receive the test SRAM output signal Q_0, the C0 data terminal is connected to the system clock signal CLK, the C1 data terminal is connected to the system clock via the D0 delay unit signal CLK_1, and the C2 data terminal is connected to the system clock via D0. , D1 delay unit signal CLK_2, and so on, CLK, CLK_1-CLK_15 are respectively connected to the data terminals of the comparators C0-C15.
  • the specific working waveform of the comparator is shown in Figure 4. When the clock pulse is over, the trigger can record how many time units are delayed, that is, the time that the trigger clock terminal signal lags behind the trigger data terminal signal.
  • the results Z0-Z15 obtained by the comparator are input to the accumulator (ACC).
  • the accumulator is realized by a counter.
  • the accumulator counts the number of level "1" in the sampled signal, and then encodes the output result according to the designed delay unit information
  • T access The SRAM access time (T access ) can be determined very intuitively.
  • the first step is to start MBIST and time measurement, and set bist_en and bitm_en to "1".
  • the second step is to capture the output data signal Q_0 of the SRAM under test and the system clock CLK.
  • CLK generates CLK_1-CLK_15 through delay units D0-D14, respectively.
  • the comparator samples the data terminal signal until the 16-level comparator has finished sampling.
  • the accumulator counts and encodes the number of level "1" in the sampled signal, and finally outputs the result to the off-chip for calculation.
  • the measurement calculation formula: ⁇ T 1+(N-1)*0.02, where N is the final output result of the accumulator (N ⁇ 15), and the time unit is nanoseconds.
  • the verification object is selected as a low-voltage 6T SRAM (capacity: 32x16), the row address is 4, and the column address is 8.
  • Figure 6 shows the access time parameter measurement circuit for verifying this method example.

Abstract

Circuit de mesure sur puce et procédé de mesure destiné à des paramètres de temps de SRAM basse tension, le circuit de mesure comprenant un module de commande de mesure et un module de mesure de temps, le module de mesure de temps étant connecté au module de commande de mesure ; le module de mesure de temps est commandé au moyen du module de commande de mesure ; le module de commande de mesure comporte un module d'auto-test intégré (BIST) basé sur une mémoire ; le module de commande de mesure comprend une logique de commande BIST, une logique de génération de vecteur de test BIST et un module de commande de mesure de temps ; et le module de mesure de temps comprend une unité de retard, un comparateur, et un accumulateur. Au moyen de l'ajout d'un module de commande de mesure et d'un module de mesure de temps, une importante quantité de SRAM est testée dans une puce à grande échelle. Tout en effectuant un test MBIST, la mesure du temps d'accès de chaque unité de mémoire de la SRAM est également mise en œuvre, et le temps d'accès pour une ou plusieurs SRAM est mesuré en même temps, ce qui permet d'obtenir une auto-mesure « pleine vitesse » et des résultats de mesure précis, réduisant la dépendance à l'ATE, et réduisant efficacement les coûts de test.
PCT/CN2021/076791 2020-04-20 2021-02-19 Circuit de mesure sur puce et procédé de mesure destiné à des paramètres de temps de mémoire vive statique (sram) basse tension WO2021212984A1 (fr)

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CN111210865B (zh) * 2020-04-20 2020-09-01 南京邮电大学 一种低电压sram时间参数的片上测量电路及测量方法
CN111752794B (zh) * 2020-06-04 2022-08-12 Oppo广东移动通信有限公司 供电信息的采集方法、系统以及芯片

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JP2001208804A (ja) * 2000-01-25 2001-08-03 Hitachi Ltd 半導体集積回路装置
US20100027359A1 (en) * 2008-08-04 2010-02-04 Nec Electronics Corporation Memory test circuit which tests address access time of clock synchronized memory
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