CN111210865B - 一种低电压sram时间参数的片上测量电路及测量方法 - Google Patents

一种低电压sram时间参数的片上测量电路及测量方法 Download PDF

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Publication number
CN111210865B
CN111210865B CN202010311269.7A CN202010311269A CN111210865B CN 111210865 B CN111210865 B CN 111210865B CN 202010311269 A CN202010311269 A CN 202010311269A CN 111210865 B CN111210865 B CN 111210865B
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China
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clk
delay unit
time
module
termination
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CN202010311269.7A
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Chinese (zh)
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CN111210865A (zh
Inventor
吕凯
施明旻
王明
杨涵
王运波
王子轩
蔡志匡
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Nanjing University of Posts and Telecommunications
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Nanjing University of Posts and Telecommunications
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Priority to CN202010311269.7A priority Critical patent/CN111210865B/zh
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Priority to PCT/CN2021/076791 priority patent/WO2021212984A1/fr
Priority to DE202021102005.9U priority patent/DE202021102005U1/de
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012Marginal testing, e.g. race, voltage or current testing of timing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36Data generation devices, e.g. data inverters
CN202010311269.7A 2020-04-20 2020-04-20 一种低电压sram时间参数的片上测量电路及测量方法 Active CN111210865B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202010311269.7A CN111210865B (zh) 2020-04-20 2020-04-20 一种低电压sram时间参数的片上测量电路及测量方法
PCT/CN2021/076791 WO2021212984A1 (fr) 2020-04-20 2021-02-19 Circuit de mesure sur puce et procédé de mesure destiné à des paramètres de temps de mémoire vive statique (sram) basse tension
DE202021102005.9U DE202021102005U1 (de) 2020-04-20 2021-04-14 On-Chip-Messkreis für Zeitparameter von Niederspannungs-SRAM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010311269.7A CN111210865B (zh) 2020-04-20 2020-04-20 一种低电压sram时间参数的片上测量电路及测量方法

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CN111210865B true CN111210865B (zh) 2020-09-01

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CN (1) CN111210865B (fr)
DE (1) DE202021102005U1 (fr)
WO (1) WO2021212984A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111210865B (zh) * 2020-04-20 2020-09-01 南京邮电大学 一种低电压sram时间参数的片上测量电路及测量方法
CN111752794B (zh) * 2020-06-04 2022-08-12 Oppo广东移动通信有限公司 供电信息的采集方法、系统以及芯片

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001208804A (ja) * 2000-01-25 2001-08-03 Hitachi Ltd 半導体集積回路装置
JP2001266595A (ja) * 2000-03-24 2001-09-28 Nec Microsystems Ltd 半導体集積回路装置
US6424583B1 (en) * 2000-11-30 2002-07-23 Taiwan Semiconductor Manufacturing Co., Ltd System and measuring access time of embedded memories
JP2010040092A (ja) * 2008-08-04 2010-02-18 Nec Electronics Corp 半導体集積回路
CN103886913B (zh) * 2014-03-31 2016-09-14 西安紫光国芯半导体有限公司 Sram读取时间自测试电路及测试方法
KR102088221B1 (ko) * 2016-11-23 2020-03-12 주식회사 디비하이텍 메모리 접근 시간 측정 시스템
CN109192239A (zh) * 2018-07-25 2019-01-11 上海交通大学 Sram存储器的片上测试电路和测试方法
CN111210865B (zh) * 2020-04-20 2020-09-01 南京邮电大学 一种低电压sram时间参数的片上测量电路及测量方法

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CN111210865A (zh) 2020-05-29
WO2021212984A1 (fr) 2021-10-28
DE202021102005U1 (de) 2021-04-21

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