CN111210865A - On-chip measuring circuit and measuring method for low-voltage SRAM time parameter - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
Abstract
The invention provides an on-chip measuring circuit and a measuring method of low-voltage SRAM time parameters, and the on-chip measuring circuit comprises a measuring control module and a time measuring module, wherein the time measuring module is connected with a measuring control module, the time measuring module is controlled by the measuring control module, the measuring control module is based on a memory built-in self-test module, the measuring control module comprises a BIST control logic, a BIST test vector generation logic and a time measuring control module, and the time measuring module comprises a delay unit, a comparator and an accumulator. By adding the measurement control module and the time measurement module, the access time of each storage unit of the SRAM is measured when the MBIST is tested for a large batch of SRAM in a large-scale chip, the access time is measured for one or more SRAMs at the same time, full-speed self-measurement is realized, the measurement result is accurate, the dependence on ATE is reduced, and the test cost is effectively reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuit testing, in particular to an on-chip measuring circuit and a measuring method for low-voltage SRAM time parameters.
Background
In an informatization tide, artificial intelligence, the Internet of things, big data and a block chain are mutually energized, and industrial optimization and upgrading and economy are rapidly developed. The data plays a core role in the development of these high and new technologies, which certainly puts higher demands on electronic information storage products, such as high density, high speed, low power consumption, low cost, etc. FLASH, DRAM, and SRAM storage are the mainstream in the current market. The DRAM has high density, relatively simple structure using capacitor, low delay, high efficiency, near infinite access endurance and low power consumption. Since the SRAM has a very fast read/write speed, data can be sent to the CPU for processing in the shortest time and can be quickly output to the outside, the SRAM is widely used in various applications.
The contradiction between low power consumption and high speed of a chip is always considered to be the most critical solution for not avoiding the contradiction. In low power SRAM design, reducing the supply voltage is most effective. In low voltage design, the performance constraint of SRAM is bound to be more severe in pursuit of lower operating voltage and power consumption. The access time of the SRAM is one of the main time parameters of performance, and usually the adverse effect of external probing on high-performance circuits, and the magnitude of parameters and errors that need to be considered, the measurement using external equipment becomes very difficult. Therefore, on-chip solutions with built-in measurements are often needed for testers or external devices to measure accurate access times. Many test schemes are used for measuring the time parameter of the SRAM, but at present, the occupation ratio of the SRAM part on a chip is larger and larger, the types of the SRAMs with different specifications are more and more, especially the requirement on low power consumption is more strict for the performance requirement of the time parameter of the low-voltage SRAM, the traditional scheme can not meet the requirement on the current time parameter measurement, and the exploration of a method which can be large-scale, large-batch, accurate and convenient is extremely important.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide an on-chip measuring circuit and a measuring method of low-voltage SRAM time parameters.
The invention provides an on-chip measuring circuit of low-voltage SRAM time parameters, which comprises a measuring control module and a time measuring module, wherein the time measuring module is connected with a measuring control module, the time measuring module is controlled by the measuring control module, the measuring control module is based on a memory built-in self-test module, the measuring control module comprises a BIST control logic, a BIST test vector generation logic and a time measuring control module, and the time measuring module comprises a delay unit, a comparator and an accumulator.
The further improvement lies in that: the time measurement control module is a multiplexer for selecting or shielding signals, and is connected with an input SRAM test vector generated by built-in self test of the memory and a result output from the SRAM to be tested to the time measurement module.
The further improvement lies in that: the time measurement module comprises 15 stages of delay units D0-D14 which are connected in series, a system clock CLK is connected with D0, and a signal CLK generates signals CLK _1-CLK _15 after passing through D0-D14, wherein the delay units are composed of two stages of inverters, the delay of the first stage of delay unit D0 is 1ns, and the delays of the other delay units D1-D14 are all 20 ps.
The further improvement lies in that: the clock ends of the comparators C0-C15 are connected with an SRAM output signal Q _0 to be tested, the data ends of the comparators C0 are connected with a system clock signal, the data ends of the comparators C1 are connected with a system clock signal CLK _1 through a D0 delay unit, the data ends of the comparators C2 are connected with a system clock signal CLK _2 through a D0 delay unit and a D1 delay unit, and so on, the CLK and the CLK _1-CLK _15 are respectively connected with the data ends of the comparators C0-C15, the result Z0-Z15 obtained by the comparators is input into an Accumulator (ACC), and the result OUT of the accumulator is output finally.
The invention also provides a measuring method of the on-chip measuring circuit of the time parameter of the low-voltage SRAM, which comprises the following steps:
the method comprises the following steps: MBIST and time measurement are started, and bist _ en and bitmap _ en are set to be 1;
step two: capturing an SRAM output data signal Q _0 to be tested and a system clock CLK;
step three: CLK generates CLK _1-CLK _15 through delay cells D0-D14, respectively;
step four: the comparator samples the data end signal until the 16-level comparator finishes sampling;
step five: the accumulator counts the number of level '1' in the sampling signal and codes, and finally outputs the result to the outside of the chip for calculation.
The further improvement lies in that: and the measuring formula in the step five is Δ T =1+ (N-1) 0.02, wherein N is the final output result (N < 15) of the accumulator, and the time unit is nanosecond.
On the basis of an MBIST (memory built-in self test) circuit, a measurement control module and a time measurement module are added, wherein the measurement control module comprises a BIST controller, a BIST test vector generator and a time measurement control circuit. The time measurement control circuit is used for controlling signal gating between the memory test circuit and the time measurement module, and can measure the access time of the SRAM while carrying out the BIST test.
The MBIST is a technical scheme mature in the industry for testing the memory, the test vectors required by the time parameter measurement are write 0 read 0 and write 1 read 1, and such test vectors are commonly existed in the MBIST algorithm, so that the MBIST test vector set is enough to meet the test vectors required by the time parameter measurement. Aiming at integrating SRAMs with different specifications and large batches of SRAMs in a chip, the area overhead is increased by selecting a plurality of SRAMs to independently design a control module, and the logic sharing with the MBIST is more suitable. In summary, the design of SRAM time parameter measurement based on the MBIST test scheme is definitely simpler and the cost is least.
The time measurement control module is a multiplexer for selecting or shielding signals, and is connected with an input SRAM test vector generated by built-in self test of the memory and a result output from the SRAM to be tested to the time measurement module. The external world carries out control through communication with the BIST controller (BIST _ en =1, bitmap _ en = 1), the starting controller enters a time parameter measuring mode, the BIST controller starts the BIST test vector generator, a series of pre-designed test excitation is generated according to an algorithm and is applied to a circuit to be tested, meanwhile, the time measuring control circuit controls signal gating between the memory test circuit and the time measuring module, and the response (Q _ 0) of the SRAM to be tested is input to the time measuring module.
The invention has the beneficial effects that: by adding the measurement control module and the time measurement module, the access time of each storage unit of the SRAM can be measured while MBIST test is carried out on a large batch of SRAM in a large-scale chip, the access time can be measured simultaneously aiming at one or more SRAMs, full-speed self-measurement is realized, the measurement result is more accurate, the dependence on ATE is reduced, and the test cost is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of the overall measurement circuit of the present invention.
FIG. 2 is a schematic view of a measurement control module of the present invention.
FIG. 3 is a schematic diagram of a time measurement module of the present invention.
Fig. 4 is a schematic diagram of the comparator of the present invention.
Fig. 5 is a schematic view of the measurement process of the present invention.
FIG. 6 is a schematic diagram of an example access time parameter measurement circuit of the present invention.
FIG. 7 is a schematic diagram of an example circuit measurement waveform of the present invention.
Detailed Description
In order to further understand the present invention, the following detailed description will be made with reference to the following examples, which are only used for explaining the present invention and are not to be construed as limiting the scope of the present invention.
As shown in fig. 1, the embodiment provides an on-chip measurement circuit for a time parameter of a low voltage SRAM, including a measurement control module and a time measurement module, where the time measurement module is connected to a measurement control module, the measurement control module controls the time measurement module through the measurement control module, the measurement control module is based on a memory built-in self-test module, the measurement control module includes a BIST control logic, a BIST test vector generation logic, and a time measurement control module, and the time measurement module includes a delay unit, a comparator, and an accumulator.
The MBIST is a technical scheme mature in the industry for testing the memory, the test vectors required by the time parameter measurement are write 0 read 0 and write 1 read 1, and such test vectors are commonly existed in the MBIST algorithm, so that the MBIST test vector set is enough to meet the test vectors required by the time parameter measurement. Aiming at integrating SRAMs with different specifications and large batches of SRAMs in a chip, the area overhead is increased by selecting a plurality of SRAMs to independently design a control module, and the logic sharing with the MBIST is more suitable. In summary, the design of SRAM time parameter measurement based on the MBIST test scheme is definitely simpler and the cost is least.
As shown in fig. 2, the time measurement control module is a multiplexer that selects or masks signals, and connects the input SRAM test vector to be tested generated by the memory built-in self test and the output result from the SRAM to be tested to the time measurement module. The external world carries out control through communication with the BIST controller (BIST _ en =1, bitmap _ en = 1), the starting controller enters a time parameter measuring mode, the BIST controller starts the BIST test vector generator, a series of pre-designed test excitation is generated according to an algorithm and is applied to a circuit to be tested, meanwhile, the time measuring control circuit controls signal gating between the memory test circuit and the time measuring module, and the response (Q _ 0) of the SRAM to be tested is input to the time measuring module.
As shown in FIG. 3, the time measurement module comprises 15 stages of delay units D0-D14 connected in series, the system clock CLK connected to the D0 delay unit, the signal CLK passing through D0-D14 generates signals CLK _1-CLK _15, wherein the delay units are composed of two stages of inverters, the delay of the first stage of delay unit D0 is 1ns, and the delays of the other delay units D1-D14 are 20 ps. More delay units can be added in the design according to the requirements of precision and area, the parameter of the measurement object access time selected by the patent is slightly larger than 1ns, so that the combination of 1ns (D0) and 20ps (D1-D14) is finally selected. The delayed cells may be modified according to the actual measurement object.
The comparators C0-C15 and C0-C15 are connected with the output signal Q _0 of the SRAM to be tested in a clock termination mode, the data of the C0 is connected with the system clock signal CLK, the data of the C1 is connected with the system clock and delays the unit signal CLK _1 through D0, the data of the C2 is connected with the system clock and delays the unit signal CLK _2 through D0 and D1, and the like, the CLK and the CLK _1-CLK _15 are respectively connected with the data ends of the comparators C0-C15. The specific comparator operating waveform is shown in fig. 4, and after the clock pulse is ended, the flip-flop can record how many time units are delayed, that is, the time after which the signal at the clock end of the flip-flop lags the signal at the data end of the flip-flop. The result Z0-Z15 from the comparator is input to an Accumulator (ACC) which is realized by a counter, the accumulator counts the number of level '1' in the sampling signal, then the output result is encoded, and the access time (T) of the SRAM can be determined very intuitively according to the designed delay unit informationaccess）。
The measurement steps are shown in the flow chart of fig. 5:
in the first step, MBIST and time measurement are started, and bist _ en and bim _ en are set to "1".
And secondly, capturing an output data signal Q _0 of the SRAM to be tested and a system clock CLK.
In the third step, CLK is delayed by delay cells D0-D14 to generate CLK _1-CLK _15, respectively.
And fourthly, the comparator samples the data end signal until the 16-stage comparator finishes sampling.
And fifthly, counting the number of the level '1' in the sampling signal by the accumulator, coding, and finally outputting the result to the outside of the chip for calculation. Measurement calculation formula: Δ T =1+ (N-1) 0.02, where N is the final output of the accumulator (N < 15), the time unit being nanoseconds.
To verify the validity of the measurement circuit, a low voltage 6T SRAM (capacity: 32x 16) with a row address of 4 and a column address of 8 was chosen as the verification target. FIG. 6 is a circuit for verifying access time parameter measurement for an example of the method. FIG. 7 is a waveform diagram of actual measurements of the first bit memory cell at the first address, according to the measurement calculation method of step 5, listing the following equations and obtaining the results: Δ T =1+ (10-1) 0.02=1.180 ns.
Claims (6)
1. An on-chip measurement circuit of a low voltage SRAM time parameter, characterized in that: including measurement control module and time measurement module, time measurement module is connected with measurement control module, through measurement control module control time measurement module, measurement control module is based on memory built-in self test module, and measurement control module contains BIST control logic, BIST test vector generation logic and time measurement control module in order, time measurement module contains delay unit, comparator and accumulator.
2. The on-chip measurement circuit of a low voltage SRAM time parameter of claim 1, wherein: the time measurement control module is a multiplexer for selecting or shielding signals, and is connected with an input SRAM test vector generated by built-in self test of the memory and a result output from the SRAM to be tested to the time measurement module.
3. The on-chip measurement circuit of a low voltage SRAM time parameter of claim 1, wherein: the time measurement module comprises 15 stages of delay units D0-D14 which are connected in series, a system clock CLK is connected with D0, and a signal CLK generates signals CLK _1-CLK _15 after passing through D0-D14, wherein the delay units are composed of two stages of inverters, the delay of the first stage of delay unit D0 is 1ns, and the delays of the other delay units D1-D14 are all 20 ps.
4. The on-chip measurement circuit of a low voltage SRAM time parameter of claim 3, wherein: the clock ends of the comparators C0-C15 are connected with the output signal Q _0 of the SRAM to be tested, the data ends of the comparators C0 are connected with the system clock signal, the data ends of the comparators C1 are connected with the system clock signal CLK _1 through a D0 delay unit, the data ends of the comparators C2 are connected with the system clock signal CLK _2 through a D0 delay unit and a D1 delay unit, and so on, the CLK and the CLK _1-CLK _15 are respectively connected with the data ends of the comparators C0-C15, the result Z0-Z15 obtained by the comparators is input into the accumulator, and the result OUT of the accumulator is finally output.
5. A method for measuring the on-chip measurement circuit of the low voltage SRAM time parameter as claimed in any one of claims 1-4, characterized in that: the method comprises the following steps:
the method comprises the following steps: MBIST and time measurement are started, and bist _ en and bitmap _ en are set to be 1;
step two: capturing an SRAM output data signal Q _0 to be tested and a system clock CLK;
step three: CLK generates CLK _1-CLK _15 through delay cells D0-D14, respectively;
step four: the comparator samples the data end signal until the 16-level comparator finishes sampling;
step five: the accumulator counts the number of level '1' in the sampling signal and codes, and finally outputs the result to the outside of the chip for calculation.
6. The method of claim 5, wherein the method comprises the steps of: and the measuring formula in the step five is Δ T =1+ (N-1) 0.02, wherein N is the final output result (N < 15) of the accumulator, and the time unit is nanosecond.
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| CN202010311269.7A CN111210865B (en) | 2020-04-20 | 2020-04-20 | On-chip measuring circuit and measuring method for low-voltage SRAM time parameter |
| PCT/CN2021/076791 WO2021212984A1 (en) | 2020-04-20 | 2021-02-19 | On-chip measurement circuit and measurement method for low-voltage sram time parameters |
| DE202021102005.9U DE202021102005U1 (en) | 2020-04-20 | 2021-04-14 | On-chip measuring circuit for timing parameters of low voltage SRAM |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111752794A (en) * | 2020-06-04 | 2020-10-09 | Oppo广东移动通信有限公司 | Power supply information acquisition method, system and chip |
| WO2021212984A1 (en) * | 2020-04-20 | 2021-10-28 | 南京邮电大学 | On-chip measurement circuit and measurement method for low-voltage sram time parameters |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001266595A (en) * | 2000-03-24 | 2001-09-28 | Nec Microsystems Ltd | Semiconductor integrated circuit device |
| US20020075740A1 (en) * | 2000-11-30 | 2002-06-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | System for measuring access time of embedded memories |
| CN103886913A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | SRAM (Static Random Access Memory) reading time self-testing circuit and method |
| CN109192239A (en) * | 2018-07-25 | 2019-01-11 | 上海交通大学 | The on-chip test circuit and test method of SRAM memory |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001208804A (en) * | 2000-01-25 | 2001-08-03 | Hitachi Ltd | Semiconductor integrated circuit device |
| JP2010040092A (en) * | 2008-08-04 | 2010-02-18 | Nec Electronics Corp | Semiconductor integrated circuit |
| KR102088221B1 (en) * | 2016-11-23 | 2020-03-12 | 주식회사 디비하이텍 | System for measuring an access time of a memory |
| CN111210865B (en) * | 2020-04-20 | 2020-09-01 | 南京邮电大学 | On-chip measuring circuit and measuring method for low-voltage SRAM time parameter |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001266595A (en) * | 2000-03-24 | 2001-09-28 | Nec Microsystems Ltd | Semiconductor integrated circuit device |
| US20020075740A1 (en) * | 2000-11-30 | 2002-06-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | System for measuring access time of embedded memories |
| CN103886913A (en) * | 2014-03-31 | 2014-06-25 | 西安华芯半导体有限公司 | SRAM (Static Random Access Memory) reading time self-testing circuit and method |
| CN109192239A (en) * | 2018-07-25 | 2019-01-11 | 上海交通大学 | The on-chip test circuit and test method of SRAM memory |
Non-Patent Citations (1)
| Title |
|---|
| L.J.ZHANG等: "A Precise Implementation of Random Access Time Measurement", 《THE INSTITUTION OF ENGINEERS(INDIA)》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021212984A1 (en) * | 2020-04-20 | 2021-10-28 | 南京邮电大学 | On-chip measurement circuit and measurement method for low-voltage sram time parameters |
| CN111752794A (en) * | 2020-06-04 | 2020-10-09 | Oppo广东移动通信有限公司 | Power supply information acquisition method, system and chip |
| CN111752794B (en) * | 2020-06-04 | 2022-08-12 | Oppo广东移动通信有限公司 | Power supply information acquisition method, system and chip |
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| WO2021212984A1 (en) | 2021-10-28 |
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