JP2001208804A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device with a test circuit capable of measuring a memory access time precisely while using a clock signal formed insides. SOLUTION: In this semiconductor integrated circuit device including a clock generating circuit for forming the internal clock signal synchronized with a clock signal supplied from an external terminal, and a memory circuit actuated by the internal clock signal formed in the clock generating circuit, the internal clock signal is supplied to a variable delay circuit, a phase difference between a delayed signal thereof and the internal clock signal is compared to form a control loop so as to comform the both, plural delayed signals are formed by selecting delay stages of the variable delay circuit to start the memory access with respect to the memory circuit by the internal clock signal, and an output signal of the memory circuit is held by the selected delayed signal of the variable delay circuit to prpovide the test circuit for conducting the measurement of the access time of the memory circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique effective for use in a test circuit for measuring an access time of a built-in memory circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device in which a logic circuit and a RAM are mixed, a two-phase clock signal is prepared as a method of measuring the access time of the built-in RAM. In some cases, the internal clock is supplied to a logic circuit to form an internal clock having a pulse width based on the phase difference, and is used for measuring an access time of a memory circuit. A D-type latch circuit is provided at an output portion of the memory circuit, and the D-type latch circuit becomes through during a period in which the internal clock signal is at a high level to take in an output signal of the memory circuit. In other words, it utilizes the fact that the output signal of the memory circuit is not transmitted to the D-type latch circuit if the phase difference between the two clock signals is shorter than the memory access time.

[0003]

SUMMARY OF THE INVENTION In a semiconductor integrated circuit device provided with a clock generation circuit for receiving a clock signal supplied from an external terminal and internally forming a clock signal synchronized with the clock signal, the internal clock signal is Since it is generated by the generation circuit, it is difficult to accurately control the pulse width of the internal clock signal even if a clock signal having a phase difference with the clock signal is supplied. In such a method of measuring the memory access time, the accuracy is reduced.

An object of the present invention is to provide a semiconductor integrated circuit device having a test circuit capable of measuring a memory access time with high accuracy while using a clock signal formed inside. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a semiconductor integrated circuit device including a clock generation circuit that forms an internal clock signal synchronized with a clock signal supplied from an external terminal, and a memory circuit that operates with the internal clock signal formed by the clock generation circuit, An internal clock signal is supplied to a variable delay circuit, a phase difference between the delayed signal and the internal clock signal is compared, and a control loop is formed so as to match the two. By selecting a delay stage of the variable delay circuit, A plurality of types of delay signals are formed, memory access to the memory circuit is started by the internal clock signal, an output signal of the memory circuit is held by a selected delay signal of the variable delay circuit, and access to the memory circuit is performed. A test circuit for measuring time is provided.

[0006]

FIG. 1 is a block diagram showing one embodiment of a memory circuit and a test circuit provided in a semiconductor integrated circuit device (hereinafter simply referred to as an LSI) according to the present invention. FIG. 1 shows only a portion related to the memory circuit among LSIs having a plurality of functional blocks. Such an LSI is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In this embodiment, a variable delay circuit for measuring a memory access time of a memory circuit is provided inside an LSI,
By comparing the delay time of this variable delay stage with the access time of a RAM (random access memory), RA
The access time of M is measured. In this case, in order to set the delay time of the delay circuit formed in the semiconductor integrated circuit device with high precision, a variable delay stage embedded in each RAM macro is used by using the cycle time of the internal clock ICK formed by the PLL circuit. Self-correct. That is, PLL
The frequency of the circuit depends on the frequency of the external clock signal CK and is determined accurately. For this reason, if the variable delay stage is corrected using the cycle time, the delay time of the variable delay stage is also determined accurately. By using this to measure the memory access time, a highly accurate measurement result can be obtained.

The PLL circuit forms an internal clock signal ICK synchronized with a clock signal CK supplied from an external terminal, as is well known. Therefore, the internal clock signal IC
The cycle time (one cycle) of K is formed so as to correctly match the clock signal CK supplied from the external terminal. Although not particularly limited, the internal clock signal ICK is delayed through a first variable delay circuit VDL1 and a second variable delay circuit VDL2 to be a delayed signal ICK '. The phase comparison circuit PD is connected to the internal clock signal IC
K is compared with the delay signal ICK ', and a control voltage VC is generated to match the phases of the two signals ICK and ICK' to control the delay times of the first and second variable delay circuits.

The first and second variable delay circuits VDL1 and VDL2 are constituted by delay stages such as inverter circuits, and the delay time in each stage is reduced by the above-described phase comparison operation. One cycle of the clock signal ICK is equally divided. In this embodiment, the delay stage of the first variable delay circuit VDL1 is selected, and the first variable delay circuit VDL1 is supplied to the internal clock signal ICK.
A test clock signal TLCK having a phase difference corresponding to the delay time at 1 is generated.

The memory circuit RAM includes a flip-flop circuit FFin which receives an input signal such as an address signal, and a decoder DEC which decodes the address signal which is received by the flip-flop circuit FFin, and a memory array in which memory cells are arranged in a matrix. The memory cell designated by the address signal is selected from MARY, sensed by the sense amplifier SA, and output to the output flip-flop circuit FFout.

In order to measure the memory access time tca of the memory circuit RAM, the internal clock signal I
CK is supplied to an input flip-flop circuit FFin, and the clock signal ICK and the test clock signal TLCK are supplied via a multiplexer MX to a flip-flop circuit FF provided at an output portion of a memory circuit RAM.
supply to out. The multiplexer MX selects the internal clock signal ICK in the normal operation, and selects the test clock signal TLCK in the test operation and transmits the same to the flip-flop circuit FFout.

When the variable delay circuit VDL1 is composed of m delay stages and the variable delay circuit VDL2 is composed of n delay stages, the delay time in one delay stage is equal to the internal clock signal ICK. Assuming that one cycle is T, the delay time is made equal to T / m + n. Therefore, the internal clock ICK is applied to the delayed signal ICK 'delayed by one cycle.
And the test clock signal TLCK is supplied to the first variable delay circuit VDL1
, And the memory access time tca of the memory circuit RAM can be measured based on the delay time.

Although not particularly limited, the flip-flop circuit FFout is reset to logic 0, memory access is performed such that information of logic 1 is read from a memory cell by the internal clock signal ICK, and the number of delay stages is sequentially increased. Thus, the memory access time tca can be measured from the delay time corresponding to the number of delay stages when the output signal of the flip-flop circuit FFout changes from the reset state of logic 0 to the logic 1 corresponding to the read signal. Conversely, the delay time may be increased to measure the memory access time tca from the delay time immediately before the logic 0 is maintained, or read out different storage information from the initial value of the flip-flop circuit FFout. What should I do?

FIG. 2 is a circuit diagram showing one embodiment of a RAM macro mounted on a semiconductor integrated circuit device according to the present invention. The memory circuit is a static RAM (S
RAM). This SRAM includes an address latch circuit AL, an address decoder AD, a memory array MARY, a sense amplifier SA, and an output latch circuit O.
L and a decision output circuit FBA. The clock signal ICK formed by the PLL circuit is delayed by the timing generation circuit of the SRAM, and the clock ICK1 for the address latch AL and the clock ICK2 for the address decoder are delayed.
And a sense amplifier clock ICK3 are formed.
The operation of the internal circuit of the AM is performed sequentially.

The variable delay circuit is composed of first and second variable delay circuits VDL1 and VDL2 as in the embodiment of FIG. Among them, the first variable delay circuit VDL1 is
In order to form a delay signal with high accuracy, delay stages DA0
It comprises a low-speed delay stage consisting of DA8 and a high-speed delay stage consisting of DB0 to DB8. The low-speed delay stages DA0
DA8 is fixedly connected in cascade. The high-speed delay stage DB
0 to DB8 are delay circuits DB except for the first stage circuit DB0.
Changeover switches S0 to S6 are provided at the respective inputs of 1 to DB8, and corresponding to the control signal signals cd0 to cd7, the output signal of the low speed stage or the high speed stage is switched for each corresponding number of stages, and the high speed stage The output section of the last stage DB8 is provided with a dummy switch S8, which is constantly connected to the high-speed last stage.

In this embodiment, the first variable delay circuit VDL1 is not particularly limited in the mode for automatically setting the delay time of each delay stage, but the switches S0 to S0 correspond to the cycle of the internal clock signal ICK. One of S7 is selected and cascade-connected to the low-speed delay stage and the second variable delay circuit VDL2 to be supplied to one input of a phase comparator PCMP constituting the phase comparison circuit PD. The clock signal ICLK1 is supplied to the other input of the phase comparator PD. The phase comparator PD forms an up-up or down-down comparison output corresponding to the phase difference between the two. The comparison outputs up and down are supplied to an up / down counter circuit CTR. The output signal of this counter CTR is MOSFE having a binary weight.
It is supplied to TM1 to M4, and performs a digital / analog conversion operation corresponding to the count value of the counter CTR.

The control current circuit DCC forms a control current corresponding to the MOSFETs M1 to M4 operating as the D / A conversion elements, and the current mirror circuit controls the operation current flowing to the inverter circuit constituting the delay stage. As a result, one cycle of the clock signal ICK1 is delayed by the variable delay circuits VDL1 and VDL2.
A phase control loop that matches s2 is formed, and the automatic adjustment of the variable delay circuits VDL1 and VDL2 is performed. A plurality of cycles of the clock signal ICK1 (15
When a training period for about 0 cycle) is provided and the automatic adjustment of the delay time of the delay stage is completed, the signal ADJL
OCK causes the counter circuit UDCTR to hold the phase coincident. Thereby, the variable delay circuit VD
The delay time of L1 and VDL2 is maintained.

Thereafter, by turning on the switches S0 to S7 through the selection decoder CDEC by the control signals C0 to C2, the delay signal obtained from the output of the first variable delay circuit VDL1 is changed to the switches S0 to S7. A test clock signal TLCK set to a delay time corresponding to the number of stages selected by S7 is formed. In the test mode, the above-described test operation is performed by switching the multiplexer MX to the test clock TLCK generated as described above by the signal TCA.

FIG. 3 shows the variable delay circuits VDL1 and VDL1.
A circuit diagram of one embodiment of DL2 is shown. Each delay stage includes a P-channel MOSFET and an N-channel MOSFET for forming an operating current between a power supply voltage and a ground potential of the circuit.
An ET is provided, and is constituted by a CMOS inverter circuit to which an operating current is supplied via the two MOSFETs. P-channel type MOSFET for passing the above operating current
Is connected to a diode-connected P-channel MOSFET P2 through which a control current ci, which is a digital / analog conversion output formed based on the phase comparison output, flows and a current mirror form, so that a current corresponding to the control current ci is generated. Let it flow. The control current ci flows through a P-channel MOSFET P3 to an N-channel MOSFET N4 in which a delay stage operating current flows and an N-channel MOSFET N4 in a current mirror form, so that the same control current ci flows. You.

Each of the switches S0 to S8 is composed of two CMOS switches and an inverter circuit for generating a control signal therefor. The switch S8 is a dummy switch to which a high level (VDD) is constantly input and selects an output signal on the high-speed side. The other switches S0 to S7 are
A control signal formed by decoding a 3-bit binary signal including the control signals C0 to C2 by the gate circuits NA0 to NA7 causes one of the signals to go to a low level, and transmits the output signal of the low speed stage to the high speed stage.

FIG. 4 shows the variable delay circuit V shown in FIGS.
An equivalent circuit diagram for explaining the operation of DLY1 is shown. In this embodiment, each of the delay stages DA0 to DA8 and DB0 to DB8 is constituted by an inverter circuit in order to measure the memory access time with high accuracy. When an inverter circuit is used in this way, the input signal is inverted, so that it is usually necessary to use two inverter circuits as a unit delay stage in order to operate as a delay circuit. The time resolution decreases and the test accuracy deteriorates.

In this embodiment, a variable delay circuit is constituted by the low-speed delay stages DA0 to DA8 and the high-speed delay stages DB0 to DB8 as described above. And connect the low-speed side in tandem,
By changing the high-speed side to the preceding stage or the corresponding high-speed side by a switch except for the first stage circuit, the total number of delay stages of the variable delay circuit VDL1 becomes the same nine stages regardless of which switch S0 to S8 is selected. Thus, a constant output signal (an inverted signal in the example of FIG. 1) with respect to the input signal is obtained. Therefore, the delay time of the unit delay stage can be determined by one inverter circuit, and
By utilizing the time difference, a higher time resolution can be realized as described below. In addition,
This inversion signal can be adjusted at the phase comparison stage including the inverter circuit row to which the variable delay circuit VDL2 is added, so that there is no problem.

For example, in order to form an internal clock signal ICK of 1 GHz by a PLL circuit, set the delay time of the low-speed inverter circuits DA0 to DA8 to 75 ps, and set the delay time of the high-speed inverter circuits DB0 to DB8 to 50 ps. The delay time in the inverter circuits DB9 to DB12 of the second variable delay circuit VDLY2 is set to 87.5 ps, and a total delay time of 350 ps is allocated.

In this case, the first variable delay circuit VDL
The low-speed stage and the high-speed stage are connected by the switch S5 to make the delay time of 650 ps by Y1.
× 6) A delay time of 450 ps is obtained, and (50 × 4) 200 ps is obtained in the high-speed delay stage, whereby one cycle can be synchronized with the internal clock signal ICK of 1 μs. The delay time of the delay stage as described above is designed by setting the size ratio of the MOSFET for flowing the operation current to the inverter circuit so as to be inversely proportional to the delay time. In the above switch state, the clock signal I
By matching the phases of CK1 and the delay signal ns2, the delay times of the delay stages of the variable delay circuits VDLY1 to VDLY3 are 75 ps, 50 ps and 8 ps, respectively.
Automatically adjusted to 7.5 ps.

After the above automatic adjustment is performed, the minimum unit is 25 ps by the combination of the switches S0 to S7.
Thus, the test clock signal TLCK can be obtained with high accuracy. For example, if the switch S6 is connected to the low-speed side instead of the switch S5, the delay time increases by one stage at the low-speed side and increases by 75 ps, and the delay time decreases by one stage at the high-speed side and decreases by 50 ps. As a whole, the difference is increased by 25 ps. Conversely, when the switch S4 is switched to the low speed side instead of the switch S5, the low speed side decreases by 75 ps and the high speed side increases by 50 ps, so that the difference is reduced by 25 ps as a whole. In this way, the 1
In a unit delay stage composed of two inverter circuits, a short delay time of 25 ps, which cannot be formed at all, can be formed by circuit means.

In this configuration, a delay time of 50 × 9 = 450 ps can be obtained by using only the delay stage on the high-speed side, and 75 × 9 by using only the delay stage on the low-speed side.
8 = 600 ps delay time can be obtained. Therefore, the measurement range of the memory access time of the memory circuit RAM is 450 to 600 ps, and it is possible to determine the memory access time with a time resolution of 25 ps.

FIG. 5 is a block diagram showing another embodiment of the memory circuit and the test circuit provided in the LSI according to the present invention. In this embodiment, a test clock DCK is input with a phase difference Tsk to a clock signal CK supplied from the outside. The external clock signal CK and the test clock CDK are compared by a phase comparison circuit PD, and control a variable delay circuit DL1 that delays the clock signal CK so that they match.
A delay circuit DL2 composed of the same circuit as the delay circuit
And the delay time is controlled by the output signal of the phase comparison circuit PD. Thereby, the delay circuits DL1 and DL2 have the same delay time. This delay time is
The signal corresponds to the phase difference Tsk between the clock signals CK and DCK.

The clock signal CK supplied from the external terminal forms an internal clock signal ICK by a PLL circuit. In this embodiment, the internal clock signal IC
K is delayed (Tsk) by the delay circuit DL2 to generate a delayed signal DCK ′, and the internal clock signal ICK is generated.
To form a clock signal having a pulse width corresponding to the phase difference (Tsk). A pulse signal having such a pulse width and a clock signal ICK formed by the PLL are transferred to a memory circuit R through a multiplexer MX.
By supplying the clock to the AM, the clock CLK having a pulse width corresponding to the phase difference (Tsk) can operate the memory circuit in the test operation, and the pulse width, that is, the external clock signal CK and the test clock DCK can be used.
The memory access time can be measured by the phase difference (Tsk) from the above. In this configuration, there is no need to embed a delay stage in each RAM macro. It is necessary to embed a circuit for generating a clock signal in the PLL circuit or the first stage clock driver.

FIG. 6 shows a system L to which the present invention is applied.
An overall circuit block diagram of one embodiment of the SI is shown. The semiconductor integrated circuit device CHIP of this embodiment has a plurality of circuit blocks as shown in FIG.
O, substrate bias control circuit VBBC, control circuit ULC,
Read only memory ROM, D / A converter DAC, A /
D converter ADC, interrupt control circuit IVC, system power management circuit SPMC having clock generation circuit CGC, central processing unit CPU, static memory SR
AM, DMA controller DMAC, and dynamic memory DRAM.

The circuit blocks are composed of an internal bus BU
S, which is coupled to the control bus CBUS. They are mounted on a semiconductor substrate (not shown) that forms a semiconductor integrated circuit device. The above system power management circuit SPM
C has a function of controlling power consumed in each module mounted on the system LSI.

The semiconductor integrated circuit device has an input / output circuit I / O
Input / output external terminals Tio1 to Tion connected to
An external terminal T1 to which a reset signal resb such as a negative logic level is supplied, a control external terminal T2, and a first operation control external terminal T3 to which a first operation control signal cmq is supplied.
A second operation control external terminal T4 to which the second operation control signal cpmq is supplied, a clock external terminal T5 to which the external clock signal clk is supplied, and a plurality of power supply voltages (vd
d, vccdr, vss) are supplied to the power supply external terminals T6, T7, T8.

Although not particularly limited, the power supply voltage vdd is
The power supply voltage is used for the operation of the internal circuit block.
Take a value like 8 volts ± 0.15 volts. The power supply voltage vccdr is a power supply voltage mainly set for the input / output circuit I / O according to the input / output level required for the semiconductor integrated circuit device, and is 3.3 volts ± 0.3 volts. It is made to take one of the values such as 5 volts ± 0.25 volts, and 1.8 volts ± 0.15 volts. The potential vss is a reference potential of a circuit which is called a so-called ground potential.

The semiconductor integrated circuit device shown in FIG.
An SIC (Application Specific Integrated Circuits), that is, a special purpose IC is constituted. That is, most of the illustrated circuit blocks form so-called modules or macro cells as independent circuit functional units so as to facilitate the ASIC configuration. The size and configuration of each functional unit can be changed. AS
As the IC, circuit blocks that are not required by the electronic system to be realized among the illustrated circuit blocks can be prevented from being mounted on the semiconductor substrate. Conversely, a circuit block of a functional unit (not shown) can be added.

The semiconductor integrated circuit device is not particularly limited, but has a CMOS structure capable of a low power supply voltage so as to exhibit sufficient operation characteristics even under a low power supply voltage vdd such as 1.8 volts ± 0.15 volts. This is a semiconductor integrated circuit device.

The dynamic memory mounted on the semiconductor integrated circuit device may be operated by the power supply voltage vdd. However, in the semiconductor integrated circuit device of this embodiment, the power supply voltage vd
Along with d, a high power supply voltage generated from a voltage generation circuit operated by the power supply voltage vdd is used. In the dynamic memory, a circuit such as a row decoder for selecting a dynamic memory cell is operated at such a high power supply voltage, and the internal bus B of the semiconductor integrated circuit device is operated.
A circuit that inputs and outputs a signal to and from the US is operated by a power supply voltage such as a low power supply voltage vdd. This configuration increases the amount of charge as information provided to the dynamic memory cell. As a result, the information retention time characteristics of the dynamic memory can be improved. Similarly,
By driving the sense amplifier by the overdrive method using the boosted voltage vbs as described above, a high-speed read operation can be performed.

Although not particularly limited, the central processing unit CPU has a configuration similar to a so-called microprocessor. That is, although not shown in detail, the central processing unit CPU internally decodes an instruction register, an instruction written in the instruction register, a micro instruction ROM for forming various micro instructions or control signals, an arithmetic circuit, a general-purpose circuit, and the like. It has input / output circuits such as a register (RG6, etc.), a bus driver connected to the internal bus BUS, and a bus receiver.

The central processing unit CPU reads an instruction stored in a read only memory ROM or the like and performs an operation corresponding to the instruction. The central processing unit CPU captures external data input via the input / output circuit I / O,
Input / output of data to / from the control circuit ULC, reading of data such as fixed data required for executing instructions and instructions from the read-only memory ROM, D / A converter D
Supply of data to be subjected to D / A conversion to AC, reading of A / D converted data by A / D converter, static memory SRAM, dynamic memory DRAM
Read / write data to / from DMA controller D
It performs MAC operation control and the like. The control bus CBUS is used by the central processing unit CPU to control the operation of the illustrated circuit block, and is used to transmit a state instruction signal from a circuit block such as the DMA controller DMAC to the central processing unit CPU.

The central processing unit CPU performs necessary processing by referring to the operation control signal set in the instruction register RG5 or the like in the interrupt control circuit IVC via the internal bus BUS. The central processing unit CPU receives a system clock signal C2 generated from the clock generation circuit CGC, and operates at an operation timing and a period determined by the system clock signal C2.

The central processing unit CPU includes a clock generation circuit C
When the supply of the system clock signal C2 from the GC is stopped, the operation is stopped accordingly. In the stop state, the output signal of the dynamic circuit is undesirably changed by an undesired leak current generated in the circuit. A circuit such as a register circuit having a static flip-flop circuit configuration retains previous data even during a non-supply period of a system clock signal.

The interrupt control circuit IVC has an external terminal T1
Receives a reset signal such as a negative logic level, receives a first operation signal cmq via an external terminal T3, and receives an external terminal T4
And outputs a state instruction signal to the external terminal T2 to indicate the operation state of the semiconductor integrated circuit device. The interrupt control circuit IVC
The reset signal resb and the operation control signals cmq and c
It has a register RG5 in which bits at respective positions are set corresponding to the pmq and the state instruction signal.

The state indicating signal in the register RG5 is
It is updated by the central processing unit CPU via the internal bus BUS. The operation control signals cmq and cpmq set in the register RG5 via the external terminals T3 and T4 are referred to by the central processing unit CPU via the internal bus BUS as described above.

Although not particularly limited, the interrupt control circuit I
The VC has a refresh address counter (not shown) therein for a refresh operation of the dynamic memory. The refresh address counter in the interrupt control circuit IVC operates in the first or third mode by the first and second operation control signals cmq and cpmq, that is, in the operation mode or the operation standby mode for the semiconductor integrated circuit device. If the mode is designated, the refresh address information is incremented and periodically updated based on the system clock signal from the clock generation circuit CGC.

The clock generation circuit CGC has an external terminal T5
, And forms a system clock signal C2 having a cycle corresponding to the external clock signal clk. Although the signal lines between the clock generation circuit CGC and the central control unit CPU are represented in a simplified manner, the system clock signal C2 is generated because of the orderly operation of a circuit (not shown) in the central control unit CPU. It should be understood that the clock signal comprises a multi-phase signal, as well as a clock signal for a general processor.

The generation of the system clock signal C2 by the clock generation circuit CGC is performed when the mode signal MODE2 or the initial operation instruction signal IN responding to the first and second operation control signals cmq and cpmq from the interrupt control circuit IVC.
It is controlled by a control signal C1 such as TL and a control signal C3 from the central processing unit CPU. Operation control signal cmq
When the complete standby operation is instructed by the CPU, the central processing unit CPU performs necessary processing operations for shifting to the complete standby operation, including the operation of writing data to be statically stored in the static memory SRAM. Then, a control signal C3 for stopping the system clock generation operation is generated from the central processing unit CPU to the clock generation circuit CGC.

When the operation standby signal is instructed by the operation control signal cpmq, the central processing unit CPU includes a process of writing data to be held statically into the static memory SRAM, similarly to the complete standby operation. Such processing operations necessary for shifting to the operation standby operation are performed. The subsequent operation in this case is different from the case of the complete standby operation described above, in that the control signal C3 for selectively outputting the system clock signal from the central processing unit CPU to the clock generation circuit CGC is provided.
Is generated.

The input / output circuit I / O receives a signal supplied from the outside through a desired external terminal among the external terminals TiO1 to Tion.
signal to be output to a desired terminal of the internal bus BU
Receive via S. The input / output circuit I / O has therein a control register RG4 such as a CMOS static circuit and a data register (not shown).

The control register RG4 is a central processing unit CPU
And the central processing unit CPU provides control data for the input / output circuit I / O, for example, control data such as a data input / output instruction and a high output impedance state instruction. The data register is used for transferring data between the external terminals Tio1 to Tion and the internal bus BUS. Bit width of external terminals Tio1 to Tion, that is, the number of terminals, and internal bus B
When the bit width of the US is different, the data register is made to have a bit number corresponding to the large bit width, and performs the bit number conversion according to the operation control by the central processing unit CPU.

The circuit for signal input and the circuit for signal output of the input / output circuit I / O have their input and output operations controlled by a system clock signal. Therefore, when the system clock signal is no longer supplied, the input / output circuit I / O outputs the central processing unit CP.
As in the case of U, a low power consumption state is set.

The control circuit ULC is a control circuit provided appropriately as required by the electronic system. The control circuit ULC includes, for example, an electronic system to be realized such as a motor servo control in a hard disk device, a head tracking control, an error correction process, and a compression / expansion process of image and audio data in image and audio processing. It is provided appropriately according to. UL of control circuit
The operation of C is controlled by a system clock signal similarly to the central processing unit CPU.

As described above, the read only memory ROM stores commands and fixed data to be read and executed by the central processing unit CPU.

The D / A converter DAC has a register RG2 for receiving digital data to be converted into an analog signal supplied via the internal bus BUS, and forms an analog signal based on the digital data. The register RG2 is connected to the control circuit ULC or the central processing unit CP.
U sets digital data. The D / A conversion operation such as the D / A conversion start timing of the D / A converter DAC and the output timing of the D / A conversion result is controlled by the system clock signal. D / A converter DAC
Is supplied to desired terminals of the external terminals T1 to Tn via the internal bus BUS and the input / output circuit I / O, although not particularly limited. Although the external terminals T1 to Tn are used as input / output terminals (pins) here, they may be provided separately for input terminals and output terminals.

Although the details of the D / A converter DAC are not shown, if high-precision DA conversion is required,
A reference voltage source or a reference current source is used as a reference for an analog quantity to be obtained. Such a reference voltage source or a reference current source is considered to constitute a kind of analog circuit, and there is a danger of consuming a non-negligible current in the second mode and the third mode, that is, the complete standby mode and the operation standby. Have. Therefore, in order to reduce the current consumption in such a case, the second reference
In the mode and the third mode, a MOSFET switch which is turned off is set.

The A / D converter ADC receives a desired one of the external terminals T1 to Tn, an analog signal supplied via the input / output circuit I / O, and the internal bus BUS, and receives a control circuit ULC or The start of the A / D conversion is controlled by the central processing unit CPU, the analog signal is converted into a digital signal under clock control according to the system clock signal C2, and the obtained digital signal is set in the register RG1. .

Similarly to the D / A converter DAC, the A / D converter ADC also has a reference such as a reference for a quantization level to be digitally converted when high-precision AD conversion is required. It has a voltage source or a reference current source. Such a reference voltage source or reference current source in the A / D converter ADC also has the risk of consuming considerable current in the full standby mode and the operation standby mode. Therefore, in that case, the MO
An SFET switch is applied to such a reference voltage or current source.

Although not shown in detail, the static type memory SRAM is a CMOS static type memory cell, that is, a CMOS latch circuit and a pair of transmission dates M for inputting and outputting data to and from the CMOS latch circuit.
It has a memory cell configured to be composed of an OSFET.
The CMOS static memory cell has a feature that it stores information in a static manner and requires a remarkably small operating current to hold the information.

Such a static memory SRAM is
Practically, it constitutes a CMOS static random access memory. That is, the static memory SRAM includes a plurality of CMs arranged in a matrix.
A memory array comprising OS static memory cells;
A row address decode / drive circuit for decoding a row address signal supplied through the internal bus BUS and thereby selecting a word line in the memory array; and decoding a column address signal and thereby a column decode signal. A column address decode circuit to be formed, a column switch circuit operated by such a column decode signal to select a data line in the memory array and couple it to a common data line, and an input / output circuit coupled to the common data line; And a read / write control circuit.

Such addresses associated with the memory array
A circuit such as a decode drive circuit, that is, a memory array peripheral circuit is constituted by a CMOS static circuit. Therefore, the static memory cell SRAM is placed in a relatively low power consumption state if only the information holding operation in which the reading and writing operations are not performed. Note that the CMOS static memory has a feature to be considered that the memory cell size is relatively large and the overall size is relatively large with respect to the storage capacity, and it is relatively difficult to increase the storage capacity. is there.

The operation of the DMA controller, that is, the direct memory access controller DMAC, is controlled by the central processing unit CPU.
Internal bus BU between circuit blocks designated by PU
The data transfer via S is controlled on behalf of the central processing unit CPU. For details of the DMA controller DMAC,
Since the configuration can be substantially the same as that of the DMA controller configured as an independent semiconductor integrated circuit device, further detailed description will not be given. However, the transfer source information set by the central processing unit CPU in a register RG7 or the like thereof , Data transfer control based on setting information such as transfer destination information and data transfer amount information.

A dynamic memory DRAM has a small number of elements such that its memory cell, that is, a dynamic memory cell, typically includes an information storage capacitor for storing information in the form of electric charges and a selection MOSFET. And can be made relatively small in memory cell size. Therefore, the dynamic memory can have a relatively small overall size even with a large storage capacity.

In the above-described system LSI, for example, in the SRAM operating at high speed, the delay circuit V
A test circuit using a DL or the like is built in. Other memory D
A similar test circuit may be provided in the RAM or the ROM if necessary.

FIG. 7 is an overall block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.
The semiconductor integrated circuit device of this embodiment is a semiconductor integrated circuit device including a logic unit for performing digital signal processing, an analog unit for performing analog signal processing, and a memory circuit RAM used for the digital signal processing. The following circuits are added.

The memory test circuit mBIST tests the memory circuit RAM as described above. The memory circuit RAM is provided with a test circuit including the delay circuit and the phase comparison circuit as described above, and the memory test circuit mB
The IST is provided with a circuit for generating various signals to be supplied to a test circuit built in the memory circuit RAM. Further, for testing the logic section, a test signal is input to the logic test circuit BIST and the flip-flop of the logic section, and a boundary scan cell section for outputting the state of the flip-flop is provided. A test input / output circuit JTAG for inputting / outputting a test signal from an external terminal and input / output of a judgment output and the like to these built-in test circuits is provided.

The test input / output circuit has a total of five external terminals. TDO is a test data output terminal, TDI is a test data input terminal, TMS is a test mode setting terminal, TRSTN is a terminal for instructing reset of the test circuit, and TCK is an input of each of the above signals. Or, a test clock terminal used for output. The test input / output circuit JTAG outputs an output signal such as a test input signal necessary for the operation of the built-in test circuit and an output signal such as a test result in synchronization with the clock signal TCK through five terminals as described above. This is to input or output serially.

The operation and effect obtained from the above embodiment are as follows. That is, (1) a semiconductor integrated circuit device including a clock generation circuit that forms an internal clock signal synchronized with a clock signal supplied from an external terminal, and a memory circuit that operates using the internal clock signal formed by the clock generation circuit In the above, the internal clock signal is supplied to a variable delay circuit, the phase difference between the delayed signal and the internal clock signal is compared, and a control loop is formed so as to make the two coincide with each other to automatically adjust the delay time. A plurality of delay signals are formed by selecting the delay stage of the variable delay circuit, a memory access to the memory circuit is started by the internal clock signal, and an output of the memory circuit is selected by the selected delay signal of the variable delay circuit. The effect that the access time of the memory circuit can be measured by holding the signal can get.

(2) In addition to the above, the variable delay circuit has a first delay circuit composed of a plurality of inverter circuits, and an inverter circuit having a delay time smaller than the delay time of the inverter circuit of the first delay circuit. And a second delay circuit comprising a plurality of second delay circuits. An input signal of the inverter circuit of the preceding stage except for the first stage circuit or a corresponding signal of the first delay circuit is provided at an input portion of the inverter circuit of the second delay circuit. A switch for switching between the output signal of the inverter circuit in the preceding stage and a switch for controlling the switch to set a desired delay time by a combination of the number of delay stages of the first delay circuit and the second delay circuit. Accordingly, an effect that a delayed signal with high time resolution can be obtained is obtained.

(3) In addition to the above, the first delay circuit and the second delay circuit have a predetermined ratio of the element size of the current source MOSFET for setting the operating current of the inverter circuit constituting the first and second delay circuits. By setting the difference between the delay times, it is possible to obtain an effect that a time difference can be obtained with high accuracy without being affected by process variations.

(4) In addition to the above, the effect that the memory access time can be measured with a simple configuration and with high accuracy can be obtained by incorporating the test circuit into a memory circuit which is formed into a macro cell. .

(5) A semiconductor integrated circuit including a clock generation circuit for forming an internal clock signal synchronized with a clock signal supplied from an external terminal, and a memory circuit operated by the internal clock signal formed by the clock generation circuit In the apparatus, the output signal of the first variable delay circuit receiving the clock signal is compared with a test clock signal supplied from a test clock input terminal by a phase comparator, and a control signal such that both input signals have the same phase. To control the delay time of the first variable delay circuit, a second variable delay circuit that is configured by a circuit equivalent to the first variable delay circuit, and whose delay time is controlled by the control signal. Wherein the internal clock signal formed by the clock generation circuit and the internal clock signal are delayed by the second variable delay circuit. By forming a test pulse corresponding to the phase difference with the delay signal, supplying the test pulse to the memory circuit at the time of the test, performing memory access during the active level, and holding the output signal in the latch circuit,
The effect is obtained that the access time of the memory circuit can be measured.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. The memory circuit may be various RAMs or ROMs as described above, or a variable delay circuit for automatically setting the delay time is provided, and the delay time of the unit delay stage is always formed by the internal clock generation circuit by the phase comparison loop. In addition, a delay circuit of a similar delay circuit is provided, and the number of delay stages is selected by a switch to generate a clock signal having a certain time difference with respect to the internal clock. It may be something to do.
The present invention can be widely used for a semiconductor integrated circuit device having a built-in memory circuit.

[0070]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device including a clock generation circuit that forms an internal clock signal synchronized with a clock signal supplied from an external terminal, and a memory circuit that operates with the internal clock signal formed by the clock generation circuit, The internal clock signal is supplied to a variable delay circuit, a phase difference between the delayed signal and the internal clock signal is compared, and a control loop is formed so as to make the two coincide with each other. A plurality of delay signals are formed by selecting a delay stage of the delay circuit, a memory access to the memory circuit is started by the internal clock signal, and an output signal of the memory circuit is held by the selected delay signal of the variable delay circuit. By doing so, the access time of the memory circuit can be measured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory circuit and a test circuit provided in a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a RAM macro mounted on the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a circuit diagram showing one embodiment of the variable delay circuits VDL1 and VDL2 of FIG. 2;

FIG. 4 is an equivalent circuit diagram for explaining an operation of the variable delay circuit VDLY1 of FIGS. 2 and 3;

FIG. 5 is a block diagram showing another embodiment of a memory circuit and a test circuit provided in the semiconductor integrated circuit device according to the present invention.

FIG. 6 is an overall circuit block diagram showing an embodiment of a system LSI to which the present invention is applied.

FIG. 7 is an overall block diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

VDL1 first variable delay circuit, VDL2 second variable delay circuit, DA0 to DD8, DB0 to DB12 delay stage, DEC decoder, MARY memory array, PL
L: clock generation circuit, PD: phase comparison circuit, AL: address latch, AD: address decoder, SA: sense amplifier, FBA: determination circuit, MX: multiplexer, C
TR: counter, DCC: current control circuit, CDEC: selection decoder, S0 to S8: switch, IO: input / output circuit, VBBC: substrate bias control circuit, ULC: control circuit, ROM: read-only memory, DAC: D / A Converter, ADC: A / D converter, IVC: Interrupt control circuit, CGC: Clock generation circuit, CPU: Central processing unit, SRAM: Static memory, DMAC: DMA
Controller, DRAM… Dynamic memory, BUS
... internal bus, mBIST ... built-in memory test circuit, RA
M: memory circuit, JTAG: test input / output circuit.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keiichi Kunishoda 3-16, Shinmachi, Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. 2G032 AA07 AB01 AC10 AD06 AG02 AG07 AH04 AK16

Claims (5)

[Claims] A clock generation circuit that forms an internal clock signal synchronized with a clock signal supplied from an external terminal; and a memory circuit that operates on the internal clock signal formed by the clock generation circuit. A variable delay circuit that receives the signal, a control loop that compares the phase difference between the delay signal of the variable delay circuit and the internal clock signal to match them,
A control circuit for forming a plurality of types of delay signals by selecting a delay stage of the variable delay circuit, wherein a memory access to the memory circuit is started by the internal clock signal, and a selected delay signal of the variable delay circuit A semiconductor integrated circuit device comprising a test circuit for holding an output signal of a memory circuit and measuring an access time of the memory circuit. 2. The inverter circuit according to claim 1, wherein the variable delay circuit has a first delay circuit including a plurality of inverter circuits, and an inverter circuit having a delay time smaller than a delay time of the inverter circuit of the first delay circuit. And a second delay circuit comprising a plurality of second delay circuits. An input signal of the inverter circuit of the second delay circuit includes an output signal of an inverter circuit of a preceding stage except for a first-stage circuit or a corresponding signal of the first delay circuit. A switch for switching between the output signal of the inverter circuit of the preceding stage and
The semiconductor integrated circuit device, wherein the control circuit controls the switch to set a desired delay time by a combination of the number of delay stages of the first delay circuit and the second delay circuit. 3. The current source MOS according to claim 2, wherein the first delay circuit and the second delay circuit are configured to set an operation current of an inverter circuit constituting the first delay circuit and the second delay circuit.
A semiconductor integrated circuit device wherein the difference in the delay time is set by setting the element size of the FET to a predetermined ratio. 4. The memory circuit according to claim 1, wherein the memory circuit is configured as a macro cell, and the test circuit is built in the macro cell. Semiconductor integrated circuit device. 5. A clock signal generator comprising: a clock generation circuit for forming an internal clock signal synchronized with a clock signal supplied from an external terminal; and a memory circuit operated by the internal clock signal formed by the clock generation circuit. A first variable delay circuit, a test clock input terminal for inputting a test clock having a predetermined phase difference with respect to the clock signal, a delay signal of the first variable delay circuit, and the test clock input A phase comparator for receiving a test clock signal supplied from a terminal; and a control signal for forming a control signal such that the phases of both input signals coincide with each other based on an output signal of the phase comparator. And a phase control loop for controlling the delay time, and a circuit equivalent to the first variable delay circuit, and the delay time is controlled by the control signal. Second but controlled
And a test pulse for forming a pulse corresponding to the phase difference between the internal clock signal formed by the clock generation circuit and the delay signal obtained by delaying the internal clock signal by the second variable delay circuit A test circuit for supplying the test pulse to the memory circuit, performing memory access during an active level thereof, holding an output signal in a latch circuit, and measuring an access time of the memory circuit. A semiconductor integrated circuit device comprising: