JP2005222574A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which enables a self refresh period to be properly controlled thereby is low in power consumption and excellent in productivity, and also has high reliability for operation. <P>SOLUTION: In a bias voltage control circuit 34, an N channel MOS transistor 71 receives reference voltage VREF of a constant level which does not depend on temperature, and an N channel MOS transistor 73 receives reference voltage VREFT having a positive temperature property. Also, current drive capability of N channel MOS transistors 75, 77 are same. Hence, a method in which a refresh period corresponding to temperature is set by a mode register and a method in which a refresh period is adjusted in a self-control manner based on temperature of the semiconductor memory device can be shared without any trouble and productivity is improved. Also, the self refresh period can be appropriately controlled in accordance with temperature of the device. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a mode register for setting an operation mode and performing refresh for holding stored data.

  DRAM (Dynamic Random Access Memory), which is one of the typical semiconductor memory devices, has a memory cell composed of one transistor and one capacitor, and the structure of the memory cell itself is simple. It is used in various systems as the optimum for integration and large capacity. Data in the DRAM is held by charges accumulated in the capacitor, but this charge is gradually lost due to a leakage current, and the data is lost after a certain time. Therefore, in the DRAM, the memory cell data needs to be refreshed before the retained data disappears. Various types of DRAM have been developed so far depending on the performance, application, scale, etc. of the system in which the DRAM is used.

  A pseudo static random access memory (SRAM) has a memory cell structure the same as that of a DRAM to reduce power consumption and an external interface same as that of an SRAM to increase the speed. This pseudo SRAM incorporates an auxiliary circuit for refresh.

  An SDRAM (Synchronous Dynamic Random Access Memory) inputs and outputs data in synchronization with an external clock. This SDRAM is capable of high-speed operation by a burst operation that continuously outputs serial data.

  For refreshing stored data, there is a method called self-refresh, in which a timer is built in the chip, refresh timing is periodically generated, and refresh is performed automatically. By this self-refresh, the power consumption of the memory can be kept low in a standby state where data is only retained.

  During self-refreshing, the smaller the number of refresh operations per unit time, the smaller the current consumption. In general, the lower the temperature, the better the refresh characteristics of the device and the fewer the number of refresh operations. Therefore, there is a method called TCSR (Temperature Compensated Self Refresh) that adjusts the refresh cycle according to the temperature of the device. In this TCSR, the current consumption during self-refreshing is reduced by extending the refresh cycle as the temperature decreases.

  In TCSR, there is a method of setting a refresh cycle corresponding to temperature by a mode register. In this case, the user can set a refresh cycle suitable for the temperature of the device. There is also a method in which a refresh cycle corresponding to temperature is adjusted in a self-control manner by causing the oscillation circuit to oscillate with a bias voltage depending on temperature.

  Patent Document 1 below discloses a semiconductor memory device such as an SDRAM that can optimize a refresh cycle according to a use frequency.

  Patent Document 2 below discloses a semiconductor memory device that uses a fuse to adjust the self-refresh cycle.

  Patent Document 3 below discloses a semiconductor memory device that adjusts an operating current of an oscillation circuit that defines a refresh interval by a bias voltage having a positive temperature characteristic. In this case, current consumption in the self-refresh mode under room temperature conditions can be reduced.

Patent Document 4 below discloses a semiconductor memory device that specifies a refresh mode executed in the self-refresh mode in accordance with data stored in a mode register.
JP-A-11-31383 Japanese Patent Laid-Open No. 9-282871 JP 2003-132676 A JP 2002-373489 A

  However, in the conventional semiconductor memory device, the method of setting the refresh cycle corresponding to the temperature by the mode register and the method of adjusting in a self-control manner cannot be shared well, and the productivity is poor. In addition, when these methods are shared, the self-refresh cycle cannot be appropriately controlled according to the temperature of the device, and the power consumption cannot be sufficiently reduced.

  Also, the refresh characteristics are different between the single cell mode in which 1-bit data is stored in one memory cell and the twin cell mode in which 1-bit data is stored in two memory cells. However, conventionally, when the mode switching between the single cell mode and the twin cell mode is performed by wire bonding, the self-refresh cycle cannot be appropriately adjusted in accordance with each mode. For this reason, productivity was poor and low power consumption could not be sufficiently achieved.

  In addition, since switching from the normal operation mode to the test mode is conventionally performed only by an external signal, there is a case where the test mode is erroneously switched when noise is mixed in the external signal. .

  Therefore, a main object of the present invention is to provide a semiconductor memory device with low power consumption and excellent productivity that can appropriately control the self-refresh cycle.

  Another object of the present invention is to provide a semiconductor memory device having high operation reliability.

  A semiconductor memory device according to the present invention includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a mode register storing data indicating temperature conditions, and data stored in the mode register specified by an external signal When the temperature condition is in the first range, the refresh cycle is set based on the data stored in the mode register, and the temperature condition indicated by the data specified by the external signal and stored in the mode register is in the second range. In some cases, a refresh cycle is set by self-control based on the temperature of the semiconductor memory device, a signal generation circuit that generates a refresh request signal of the set refresh cycle, and a plurality of memory cells sequentially in synchronization with the refresh request signal A refresh execution circuit for selecting and refreshing data stored in the selected memory cell. It is intended.

  Another semiconductor memory device according to the present invention includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a single cell mode in which 1-bit data is stored in one memory cell, and 1-bit data. A selection circuit for selecting one of the twin cell modes stored in two memory cells, a first fuse circuit for storing a signal indicating a refresh cycle in the single cell mode, and a refresh in the twin cell mode When the single-cell mode is selected by the second fuse circuit that stores a signal indicating the cycle and the selection circuit, a refresh request signal having a refresh cycle corresponding to the signal stored in the first fuse circuit is generated, When the twin cell mode is selected by the selection circuit, it corresponds to the signal stored in the second fuse circuit. A signal generation circuit for generating a refresh request signal having a fresh cycle, and a refresh execution for sequentially selecting a plurality of memory cells in synchronization with the refresh request signal generated by the signal generation circuit and refreshing the data stored in the selected memory cells And a circuit.

  Still another semiconductor memory device according to the present invention includes a mode register that outputs an activation signal in response to the logic levels of a plurality of external signals being set to a first predetermined combination, and a mode register A test for instructing a test mode in response to an activation signal being input from and a logic level of a plurality of external signals being input for a predetermined number of clocks in a predetermined second combination And a test mode circuit for outputting a mode entry signal.

  In the semiconductor memory device according to the present invention, a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a mode register in which data indicating temperature conditions are stored, and data stored in the mode register specified by an external signal are indicated. When the temperature condition is in the first range, the refresh cycle is set based on the data stored in the mode register, and the temperature condition indicated by the data specified by the external signal and stored in the mode register is in the second range. In some cases, a refresh cycle is set by self-control based on the temperature of the semiconductor memory device, a signal generation circuit that generates a refresh request signal of the set refresh cycle, and a plurality of memory cells sequentially in synchronization with the refresh request signal A refresh execution circuit for selecting and refreshing the stored data of the selected memory cell is provided. It is. Therefore, the method for setting the refresh cycle corresponding to the temperature by the mode register and the method for adjusting the refresh cycle in a self-control manner based on the temperature of the semiconductor memory device can be shared without problems, and productivity is improved. . Further, since the self-refresh period can be appropriately controlled according to the temperature of the device, low power consumption can be realized.

  In another semiconductor memory device according to the present invention, a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a single cell mode in which 1-bit data is stored in one memory cell, and 1-bit data are stored. A selection circuit for selecting one of the twin cell modes stored in two memory cells, a first fuse circuit for storing a signal indicating a refresh cycle in the single cell mode, and a refresh in the twin cell mode When the single-cell mode is selected by the second fuse circuit that stores a signal indicating the cycle and the selection circuit, a refresh request signal having a refresh cycle corresponding to the signal stored in the first fuse circuit is generated, When the twin cell mode is selected by the selection circuit, according to the signal stored in the second fuse circuit A signal generation circuit for generating a refresh request signal for a refresh cycle, and a refresh execution for sequentially selecting a plurality of memory cells in synchronization with the refresh request signal generated by the signal generation circuit and refreshing the data stored in the selected memory cells A circuit is provided. Therefore, by providing the first fuse circuit for the single cell mode and the second fuse circuit for the twin cell mode, an appropriate self-refresh cycle can be set for each of the single cell mode and the twin cell mode. . Therefore, productivity can be improved, and a low power consumption semiconductor device capable of appropriately controlling the self-refresh cycle can be realized.

  Still another semiconductor memory device according to the present invention includes a mode register that outputs an activation signal in response to the logic levels of a plurality of external signals being set to a first predetermined combination, and a mode register A test for instructing a test mode in response to an activation signal being input from and a logic level of a plurality of external signals being input for a predetermined number of clocks in a predetermined second combination A test mode circuit for outputting a mode entry signal. Therefore, the test mode circuit does not perform test mode control unless it is activated by the mode register. Therefore, in the normal operation mode, even when noise is mixed in an external signal, the test mode is not entered. Thereby, the reliability of the operation of the semiconductor memory device is improved.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing the overall configuration of a pseudo SRAM according to Embodiment 1 of the present invention. In FIG. 1, the pseudo SRAM includes an address buffer 1, a control signal buffer 2, a control circuit 3, a mode register 4, a memory array 5, and an IO buffer 6.

  The address buffer 1 latches external address signals A0 to Ai (where i is an integer equal to or greater than 0) and supplies the latched signal to the control circuit 3. The control signal buffer 2 latches external control signals / CE, / WE, / OE, CLK, / ADV, CRE, / LB, / UB and supplies them to the control circuit 3. Memory array 5 includes a plurality of memory cells arranged in a matrix. Each memory cell is arranged at a predetermined address determined by a row address and a column address.

  The control circuit 3 generates various internal signals according to signals from the address buffer 1 and the control signal buffer 2 and controls the entire pseudo SRAM. A memory cell in memory array 5 is selected in accordance with external address signals A0-Ai. The selected memory cell is activated and coupled to IO buffer 6. A mode register 4 is provided adjacent to the control circuit 3. The mode register 4 stores data for setting various operation modes. The control circuit 3 controls various operation modes according to the data stored in the mode register 4.

  The memory cells of the memory array 5 need to periodically refresh the stored data. The mode register 4 also stores temperature condition data indicating a temperature condition for operating the pseudo SRAM. As will be described in detail later, a refresh control circuit that performs self-refresh control is provided in the control circuit 3.

  IO buffer 6 outputs read data Q0 to Qj from memory array 5 to the outside during a read operation, and applies data D0 to Dj input from the outside to memory array 5 during a write operation.

  FIG. 2 is a circuit block diagram showing a configuration of the memory array 5 shown in FIG. 1 and parts related thereto. Referring to FIG. 2, row decoder 11 and column decoder 12 are provided in control circuit 3 shown in FIG. 1, and column select gate 21, sense amplifier 22, equalizer 23, and memory cell MC are shown in FIG. Provided in the memory array 5.

  Row decoder 11 designates the row address of memory array 5 in accordance with row address signals RA0-RAi generated from external address signals A0-Ai. Column decoder 12 designates a column address of memory array 5 in accordance with column address signals CA0 to CAi generated from external address signals A0 to Ai.

  Memory array 5 includes a column selection gate 21, a sense amplifier 22 and an equalizer 23 provided corresponding to each column. Column select gate 21 includes two N-channel MOS transistors connected between bit lines BL, / BL and data input / output lines IO, / IO, respectively. The gates of the two N-channel MOS transistors are both connected to the column decoder 12 via the column selection line CSL. When column decoder 12 raises column selection line CSL to the selection level “H” level, two N-channel MOS transistors are turned on, and bit line pair BL, / BL and data input / output line pair IO, / IO are connected. Combined.

  The sense amplifier 22 amplifies a minute potential difference between the bit lines BL and / BL to the power supply voltage VCC in response to the sense amplifier activation signals SAP and SAN becoming “H” level and “L” level, respectively. The equalizer 23 equalizes the potentials of the bit lines BL and / BL to the bit line potential VBN in response to the bit line equalize signal BLEQ becoming the activation level “H” level.

  Memory array 5 further includes a plurality of memory cells MC arranged in a matrix. Each memory cell MC is connected to the word line WL of the corresponding row. The plurality of memory cells MC in the odd-numbered columns are alternately connected to the bit lines BL or / BL, respectively. A plurality of memory cells MC in even-numbered columns are alternately connected to bit lines / BL or BL, respectively.

  Each memory cell MC is a well-known one including an N channel MOS transistor for access and a capacitor for information storage. Word line WL transmits the output of row decoder 11 and activates memory cells MC in the selected row. Bit line pair BL, / BL inputs / outputs a data signal to / from selected memory cell MC.

  Next, the operation of the pseudo SRAM will be described with reference to FIGS. In the write mode, the column decoder 12 raises the column selection line CSL of the column corresponding to the column address signals CA0 to CAi to the “H” level of the activation level, and the column selection gate 21 of that column becomes conductive. . IO buffer 6 supplies externally applied write data to selected bit line pair BL, / BL via data input / output line pair IO, / IO. Write data is given as a potential difference between bit lines BL and / BL. Next, the row decoder 11 raises the word line WL in the row corresponding to the row address signals RA0 to RAi to the “H” level of the selection level, and the MOS transistor of the memory cell MC in that row is turned on. Charges corresponding to the potential of the bit line BL or / BL are stored in the capacitor of the selected memory cell MC.

  In the read mode, first, the bit line equalize signal BLEQ falls to the “L” level of the inactivation level, and equalization of the bit lines BL and / BL by the equalizer 23 is stopped. Next, the row decoder 11 raises the word line WL of the row corresponding to the row address signals RA0 to RAi to the “H” level of the selection level. In response to this, the potentials of the bit lines BL and / BL change by a minute amount according to the charge amount of the capacitor of the activated memory cell MC.

  Next, the sense amplifier activation signals SAN and SAP are sequentially set to the “L” level and the “H” level, respectively, and the sense amplifier 22 is activated. Accordingly, a minute potential difference between bit lines BL and / BL is amplified to power supply voltage VCC. Next, the column selection line CSL of the column corresponding to the column address signals CA0 to CAi is raised to the “H” level of the selection level by the column decoder 12, and the selection gate 21 of that column is turned on. Data of the bit line pair BL, / BL of the selected column is applied to the IO buffer 6 via the column selection gate 21 and the data input / output line pair IO, / IO. IO buffer 6 outputs read data applied from memory array 5 to the outside.

  The pseudo SRAM is configured such that a normal write / read cycle and a refresh cycle are continuously performed within a memory access cycle. As a result, refresh is executed during the access cycle, the refresh can be hidden from external access, and the DRAM can be apparently operated as an SRAM. In the refresh mode, the word lines WL are sequentially raised to the “H” level of the selection level, and the memory cells MC in that row are selected. The data of the selected memory cell MC is amplified by the sense amplifier 22, and the data held in each memory cell MC is rewritten.

  Next, self-refresh control, which is a feature of the pseudo SRAM, will be described in detail. FIG. 3 is a block diagram showing the configuration of the refresh control circuit 31 for controlling the self-refresh and the mode register 4. The refresh control circuit 31 is provided in the control circuit 3 shown in FIG. In FIG. 3, the refresh control circuit 31 includes a reference voltage generation circuit 32, a positive temperature characteristic circuit 33, a bias voltage control circuit 34, and an oscillation circuit 35.

  The mode register 4 stores temperature condition data A3 and A4 indicating temperature conditions for operating the pseudo SRAM. The refresh control circuit 31 controls the refresh operation executed in the self-refresh mode according to the temperature condition data A3 and A4 stored in the mode register 4.

  The reference voltage generation circuit 32 generates a stable constant level reference voltage VREF. The positive temperature characteristic circuit 33 receives the reference voltage VREF and outputs a reference voltage VREFT having a positive temperature characteristic (the higher the temperature, the higher the voltage level). The reference voltage VREF has substantially no temperature dependence compared to the reference voltage VREFT.

  The bias voltage control circuit 34 receives the reference voltages VREF and VREFT, and generates a bias voltage VB having a voltage level corresponding to the temperature of the device according to the temperature condition data A3 and A4 from the mode register 4. The oscillation circuit 35 is activated in response to the self-refresh activation signal SRE being set to the activation level, and performs an oscillation operation in which an operation current is defined according to the bias voltage VB. The oscillation circuit 35 generates a refresh request signal PHY having an oscillation period corresponding to the voltage level of the bias voltage VB by an oscillation operation. The oscillation cycle of the refresh request signal PHY is controlled so that the cycle becomes longer as the device temperature is lower.

  FIG. 4 is a circuit diagram showing a configuration of the positive temperature characteristic circuit 33 shown in FIG. In FIG. 4, positive temperature characteristic circuit 33 includes N channel MOS transistors 41 and 42, P channel MOS transistors 43 and 44, and resistance element 45.

  Resistance element 45 and P-channel MOS transistor 43 are connected in series between power supply potential VDD line and node N1. The resistance element 45 has a positive temperature characteristic with a large resistance value. That is, the resistance value increases as the temperature increases, and the resistance value decreases as the temperature decreases. P-channel MOS transistor 44 is connected between a power supply potential VDD line and output node N2. The gates of P channel MOS transistors 43 and 44 are both connected to node N1. Here, the gate lengths of the P channel MOS transistors 43 and 44 are sufficiently large, and the short channel effect does not occur. Further, the gate width of P channel MOS transistor 43 is sufficiently larger than the gate width of P channel MOS transistor 44. These P channel MOS transistors 43 and 44 constitute a current mirror circuit.

  N-channel MOS transistor 41 is connected between node N 1 and the ground potential GND line, and has its gate receiving reference voltage VREF from reference voltage generating circuit 32. N channel MOS transistor 42 is connected between output node N2 and the line of ground potential GND, and has its gate connected to output node N2. A reference voltage VREFT having a positive temperature characteristic is applied to bias voltage control circuit 34 from output node N2.

  A stable constant level reference current Ir flows through the N-channel MOS transistor 41 in accordance with a reference voltage VREF at a constant level that does not depend on temperature. The same amount of current Ir flows through the resistance element 45. A current It of a magnitude corresponding to the potential of node N1 flows through P channel MOS transistor 44. Here, when the temperature rises, the resistance value of the resistance element 45 increases, and the potential of the node N1 decreases due to the voltage drop. In response, current It flowing in P channel MOS transistor 44 increases, and the potential (VREFT) of output node N2 increases. On the other hand, when the temperature decreases, the resistance value of the resistance element 45 decreases, and the potential (VREFT) of the output node N2 decreases.

  FIG. 5 is a circuit diagram showing a configuration of bias voltage control circuit 34 shown in FIG. In FIG. 5, bias voltage control circuit 34 includes a voltage selection unit 61, a voltage control unit 62, P channel MOS transistors 63 and 64, and a register input unit 65. Voltage selection unit 61 includes inverters 51 and 52 and N-channel MOS transistors 71 to 74. Voltage control unit 62 includes inverters 53-56, logic circuits 57-60, and N-channel MOS transistors 75-82. Register input unit 65 includes an EX-OR gate 66 and an inverter 67.

  In the register input unit 65, the EX-OR gate 66 receives the temperature condition data A3 and A4 from the mode register 4 and outputs their exclusive OR signals. That is, when the temperature levels of the temperature condition data A3 and A4 are the same, an “L” level signal is output, and when the temperature levels of the temperature condition data A3 and A4 are different, an “H” level signal is output. Inverter 67 inverts the logic level of the output signal of EX-OR gate 66 and outputs refresh configuration instruction data SRT <1>. The temperature condition data A3 is output as refresh configuration instruction data SRT <0>.

  FIG. 6 shows a list of correspondence relationships between the temperature condition data A3 and A4 stored in the mode register 4 shown in FIG. 3, the refresh configuration instruction data SRT <0> and SRT <1>, and the temperature condition. FIG. In FIG. 6, the logic levels of the temperature condition data A3 and A4 and the refresh configuration instruction data SRT <0> and SRT <1> in the 85 ° C. mode, 70 ° C. mode, 45 ° C. mode and 15 ° C. mode corresponding to each temperature condition are shown. Show.

  In the 85 ° C. mode, the temperature condition data A3 and A4 are both set to the “H” level. In response to this, the register input unit 65 outputs “H” level refresh configuration instruction data SRT <0>, SRT <1>. In the 70 ° C. mode, the temperature condition data A3 and A4 are both set to the “L” level. In response to this, register input unit 65 outputs "L" level refresh configuration instruction data SRT <0> and "H" level refresh configuration instruction data SRT <1>. In the 45 ° C. mode, the temperature condition data A3 is set to the “H” level, and the temperature condition data A4 is set to the “L” level. In response, register input unit 65 outputs "H" level refresh configuration instruction data SRT <0> and "L" level refresh configuration instruction data SRT <1>. In the 15 ° C. mode, the temperature condition data A3 is set to the “L” level, and the temperature condition data A4 is set to the “H” level. In response to this, the register input unit 65 outputs “L” level refresh configuration instruction data SRT <0>, SRT <1>.

  Thus, the mode register 4 stores the temperature condition data A3 and A4 corresponding to the 85 ° C. mode, 70 ° C. mode, 45 ° C. mode, and 15 ° C. mode, respectively. When the mode register 4 is set from the outside by the user, a temperature condition (mode) corresponding to the temperature of the device is selected. In response to this, refresh configuration instruction data SRT <0>, SRT <1> are generated by the register input unit 65. The self-refresh cycle is controlled based on the refresh configuration instruction data SRT <0>, SRT <1>.

  In voltage selection unit 61, inverter 51 inverts the logic level of refresh configuration instruction data SRT <1> from register input unit 65 and outputs the result. The inverter 52 inverts the logic level of the signal from the inverter 51 and outputs it.

  N channel MOS transistors 71 and 72 are connected in series between node N11 and a line of ground potential GND. N channel MOS transistor 71 has its gate receiving reference voltage VREF from reference voltage generating circuit 32. N channel MOS transistor 72 has its gate receiving refresh configuration instruction data SRT <1> from register input unit 65 through inverter 51. N channel MOS transistors 73 and 74 are connected in series between node N11 and a line of ground potential GND. N channel MOS transistor 73 has its gate receiving reference voltage VREFT from positive temperature characteristic circuit 33. N channel MOS transistor 74 has its gate receiving refresh configuration instruction data SRT <1> from register input unit 65 through inverters 52 and 51.

  P-channel MOS transistor 63 is connected between a line of power supply potential VDD and node N11. P channel MOS transistor 64 is connected between a power supply potential VDD line and output node N12. The gates of P channel MOS transistors 63 and 64 are both connected to node N11. These P-channel MOS transistors 63 and 64 constitute a current mirror circuit.

  In voltage control unit 62, N-channel MOS transistors 75 and 76 are connected in series between output node N12 and a line of ground potential GND. N channel MOS transistor 75 has its gate connected to its drain. Logic circuit 57 receives refresh configuration instruction data SRT <0>, SRT <1> from register input unit 65. The output node of logic circuit 57 is connected to the gate of N channel MOS transistor 76 via inverter 53.

  N channel MOS transistors 77 and 78 are connected in series between output node N12 and a line of ground potential GND. N channel MOS transistor 77 has its gate connected to its drain. Logic circuit 58 receives refresh configuration instruction data SRT <0>, SRT <1> from register input unit 65. The output node of logic circuit 58 is connected to the gate of N channel MOS transistor 78 through inverter 54.

  N channel MOS transistors 79 and 80 are connected in series between output node N12 and a line of ground potential GND. N channel MOS transistor 79 has its gate connected to its drain. Logic circuit 59 receives refresh configuration instruction data SRT <0>, SRT <1> from register input unit 65. The output node of logic circuit 59 is connected to the gate of N channel MOS transistor 80 through inverter 55.

  N channel MOS transistors 81 and 82 are connected in series between output node N12 and a line of ground potential GND. N channel MOS transistor 81 has its gate connected to its drain. Logic circuit 60 receives refresh configuration instruction data SRT <0>, SRT <1> from register input unit 65. The output node of logic circuit 60 is connected to the gate of N channel MOS transistor 82 via inverter 56. Bias voltage VB from output node N12 is applied to oscillation circuit 35.

  N-channel MOS transistors 75 and 77 are both 16 N-channel MOS transistors having a predetermined gate width connected in parallel, and N-channel MOS transistor 79 is 10 N-channel MOS transistors having a predetermined gate width. The N-channel MOS transistor 81 is connected in parallel, and eight N-channel MOS transistors having a predetermined gate width are connected in parallel. That is, the current drive capability of N channel MOS transistors 75 and 77 is twice that of N channel MOS transistor 81, and the current drive capability of N channel MOS transistor 79 is equal to the current drive capability of N channel MOS transistor 81. 1.25 times.

  Thus, N channel MOS transistors 75, 77, 79, 81 function as resistance elements having predetermined resistance values, respectively. N-channel MOS transistors 76, 78, 80, and 82 function as switching transistors that switch the connection between the corresponding N-channel MOS transistors 75, 77, 79, and 81 and the reference potential line, respectively.

  Next, the operation of the bias voltage control circuit 34 will be described with reference to FIGS. First, the operation of the voltage selection unit 61 will be described. When mode register 4 is set to 85 ° C. mode or 70 ° C. mode (SRT <1> = “H” level), the output signal of inverter 51 is set to “L” level, and the output signal of inverter 52 is “H”. To the level. In response, N channel MOS transistor 72 is turned off and N channel MOS transistor 74 is turned on. In this case, the current flowing through N channel MOS transistor 73 varies with reference voltage VREFT having a positive temperature characteristic. That is, as the temperature rises, reference voltage VREFT rises, so that the current flowing through N channel MOS transistor 73 increases. In response, the potential at node N11 decreases, and the current flowing through P channel MOS transistor 64 increases. For this reason, the potential (VB) of the output node N12 rises. On the other hand, since the reference voltage VREFT decreases as the temperature decreases, the current flowing through the N-channel MOS transistor 73 decreases. In response, the potential of node N11 rises and the current flowing through P channel MOS transistor 64 decreases. For this reason, the potential (VB) of the output node N12 decreases.

  When the mode register 4 is set to the 45 ° C. mode or the 15 ° C. mode (SRT <1> = “L” level), the output signal of the inverter 51 is set to “H” level, and the output signal of the inverter 52 is “ L ”level. In response, N channel MOS transistor 72 is turned on and N channel MOS transistor 74 is turned off. In this case, the current flowing through the N-channel MOS transistor 71 is determined by a reference voltage VREF at a certain level independent of temperature. That is, even if the temperature fluctuates, the potential of the node N11 and the potential (VB) of the output node N12 are constant.

  Thus, when the mode register 4 is set to the 85 ° C. mode or the 70 ° C. mode, a current corresponding to the reference voltage VREFT having a positive temperature characteristic is supplied to the node N11. On the other hand, when the mode register 4 is set to the 45 ° C. mode or the 15 ° C. mode, a current corresponding to the reference voltage VREF at a certain level that does not depend on the temperature is supplied to the node N11.

  Next, the operation of the voltage control unit 62 will be described. The default setting of the mode register 4 at the time of product shipment is the 70 ° C. mode. When the mode register 4 is set to the 70 ° C. mode (SRT <0> = “L” level, SRT <1> = “H” level), the output signal of the logic circuit 58 is set to the “L” level. The output signals 57, 59 and 60 are set to the “H” level. For this reason, the output signal of inverter 54 is set to "H" level, and the output signals of inverters 53, 55, 56 are set to "L" level. In response, N channel MOS transistor 78 is turned on and N channel MOS transistors 76, 80, and 82 are turned off. Therefore, the potential (VB) of output node N12 is determined by N channel MOS transistors 77 and 78.

  When mode register 4 is set to the 85 ° C. mode (SRT <0> = SRT <1> = “H” level), the output signal of logic circuit 57 is set to “L” level and the outputs of logic circuits 58 to 60 are output. The signal is set to “H” level. Therefore, the output signal of inverter 53 is set to “H” level, and the output signals of inverters 54 to 56 are set to “L” level. In response, N channel MOS transistor 76 is turned on, and N channel MOS transistors 78, 80, and 82 are turned off. Therefore, the potential (VB) of output node N12 is determined by N channel MOS transistors 75 and 76.

  Here, since the N-channel MOS transistors 75 and 77 have the same current drive capability, even if the user switches the setting of the mode register 4 between the 70 ° C. mode and the 85 ° C. mode after product shipment, the output by the voltage control unit 62 The potential control of node N12 is not performed.

  When the mode register 4 is set to the 45 ° C. mode (SRT <0> = “H” level, SRT <1> = “L” level), the output signal of the logic circuit 59 is set to the “L” level. The output signals 57, 58 and 60 are set to the “H” level. Therefore, the output signal of inverter 55 is set to “H” level, and the output signals of inverters 53, 54 and 56 are set to “L” level. In response, N channel MOS transistor 80 is turned on, and N channel MOS transistors 76, 78, and 82 are turned off. Therefore, the potential (VB) of output node N12 is determined by N channel MOS transistors 79 and 80.

  When the mode register 4 is set to the 15 ° C. mode (SRT <0> = SRT <1> = “L” level), the output signal of the logic circuit 60 is set to the “L” level, and the outputs of the logic circuits 57 to 59 The signal is set to “H” level. Therefore, the output signal of inverter 56 is set to “H” level, and the output signals of inverters 53 to 55 are set to “L” level. In response, N channel MOS transistor 82 is turned on, and N channel MOS transistors 76, 78, and 80 are turned off. Therefore, the potential (VB) of output node N12 is determined by N channel MOS transistors 81 and 82.

  Here, since the current drive capability of N channel MOS transistors 75 and 77 are both twice the current drive capability of N channel MOS transistor 81, the mode register 4 is set to the 70 ° C. mode or the 85 ° C. mode. The potential (VB) of output node N12 is both halved when mode register 4 is set to the 15 ° C. mode. Since the current drive capability of N channel MOS transistor 79 is 1.25 times the current drive capability of N channel MOS transistor 81, the potential of output node N12 when mode register 4 is set to the 45 ° C. mode ( VB) is 1 / 1.25 times that when the mode register 4 is set to the 15 ° C. mode.

  Therefore, when the user switches the setting of the mode register 4 between the 70 ° C. mode (or 85 ° C. mode), the 45 ° C. mode, and the 15 ° C. mode after product shipment, the voltage control unit 62 controls the potential of the output node N12. It is.

  Here, as a method of invalidating the setting switching between the 70 ° C. mode and the 85 ° C. mode by the mode register 4, a method of making the current drive capacities of the N-channel MOS transistors 75 and 77 the same is shown. It is not limited. For example, N channel MOS transistors 75 and 76, inverter 53 and logic circuit 57 may be eliminated, and N channel MOS transistor 78 may be turned on in both the 70 ° C. mode and the 85 ° C. mode.

  FIG. 7 is a circuit diagram showing a configuration of oscillation circuit 35 shown in FIG. 7, oscillation circuit 35 includes P channel MOS transistors 91-100 and N channel MOS transistors 101-115.

  P-channel MOS transistor 91 is connected between power supply potential VDD line and node N21, and has its gate receiving self-refresh activation signal SRE. P-channel MOS transistor 92 is connected between power supply potential VDD line and node N21. N channel MOS transistors 101-103 are connected in series between node N21 and a line of ground potential GND. P-channel MOS transistor 92 and N-channel MOS transistor 101 have their gates connected to node N25, forming an inverter. N channel MOS transistor 102 has its gate receiving bias voltage VB. N channel MOS transistor 103 has its gate receiving self-refresh activation signal SRE.

  P-channel MOS transistor 93 is connected between power supply potential VDD line and node N22. N channel MOS transistors 104 and 105 are connected in series between node N22 and a line of ground potential GND. P channel MOS transistor 93 and N channel MOS transistor 104 have their gates connected to node N21 to form an inverter. N channel MOS transistor 105 has its gate receiving self-refresh activation signal SRE. P-channel MOS transistor 94 is connected between a line of power supply potential VDD and node N23. N channel MOS transistors 106 and 107 are connected in series between node N23 and a line of ground potential GND. P channel MOS transistor 94 and N channel MOS transistor 106 have their gates connected to node N22 to form an inverter. N channel MOS transistor 107 has its gate receiving self-refresh activation signal SRE. P-channel MOS transistor 95 is connected between a power supply potential VDD line and node N24. N channel MOS transistors 108 and 109 are connected in series between node N24 and a line of ground potential GND. The gates of P channel MOS transistor 95 and N channel MOS transistor 108 are both connected to node N23 to form an inverter. N channel MOS transistor 109 has its gate receiving self-refresh activation signal SRE. P-channel MOS transistor 96 is connected between power supply potential VDD line and node N25. N channel MOS transistors 110 and 111 are connected in series between node N25 and a line of ground potential GND. P channel MOS transistor 96 and N channel MOS transistor 110 have their gates connected to node N24 to form an inverter. N channel MOS transistor 111 has its gate receiving self-refresh activation signal SRE.

  P-channel MOS transistors 92 to 96 and N-channel MOS transistors 101, 104, 106, 108, 110 constitute a ring oscillator in which inverters are connected in a ring shape. N-channel MOS transistors 102, 105, 107, 109, and 111 all have their gates receiving bias voltage VB to form a current source of a ring oscillator, each having a magnitude corresponding to the voltage level of bias voltage VB. Supply operating current to the ring oscillator.

  P-channel MOS transistor 97 and N-channel MOS transistor 112 are connected in series between a line of power supply potential VDD and a line of ground potential GND, and their gates are both connected to node N25 to constitute an inverter. P-channel MOS transistor 98 is connected between a line of power supply potential VDD and node N27. N channel MOS transistors 113 and 114 are connected in series between node N27 and a line of ground potential GND. P channel MOS transistor 98 and N channel MOS transistor 113 have their gates connected to node N26 between P channel MOS transistor 97 and N channel MOS transistor 112, and constitute an inverter. N channel MOS transistor 114 has its gate receiving self-refresh activation signal SRE.

  P channel MOS transistor 99 is connected between a power supply potential VDD line and a node N27 between P channel MOS transistor 98 and N channel MOS transistor 113, and has a gate receiving self-refresh activation signal SRE. P-channel MOS transistor 100 and N-channel MOS transistor 115 are connected in series between a power supply potential VDD line and a ground potential GND line, and their gates are both connected to node N27 to constitute an inverter. Refresh request signal PHY is output from output node N28 between P channel MOS transistor 100 and N channel MOS transistor 115.

  Next, the operation of the oscillation circuit 35 will be described. First, the case where the self-refresh activation signal SRE is at the “L” level of the inactivation level will be described. In response to self refresh activation signal SRE being set to "L" level, P channel MOS transistor 91 is rendered conductive and N channel MOS transistor 103 is rendered non-conductive. As a result, the node N21 is at the “H” level. In response, node N22 is at "L" level, node N23 is at "H" level, node N24 is at "L" level, and node N25 is at "H" level. At this time, N channel MOS transistor 101 is turned on in response to node N25 being set to “H” level, but node N21 is set to “H” level because N channel MOS transistor 103 is turned off. Hold. Therefore, in this case, the oscillation operation by the ring oscillator is not performed.

  Further, in response to self refresh activation signal SRE being set to “H” level, P channel MOS transistor 99 is turned on and N channel MOS transistor 114 is turned off. Therefore, the node N27 becomes “H” level. In response, “L” level refresh request signal PHY is output from output node N28.

  Next, the case where the self-refresh activation signal SRE is at the “H” level of the activation level will be described. In response to self refresh activation signal SRE being set to “H” level, P channel MOS transistor 91 is turned off and N channel MOS transistor 103 is turned on. In this case, a ring oscillator composed of an odd number (here, 5) of inverters performs an oscillation operation, and the logic levels of the nodes N21 to N25 are alternately switched. Since the operating current of the ring oscillator is defined by the bias voltage VB, the oscillation period changes according to the voltage level of the bias voltage VB. That is, when the bias voltage VB increases, the operating current of the ring oscillator increases, so the oscillation cycle is shortened. On the other hand, when the bias voltage VB is reduced, the operating current of the ring oscillator is reduced, so that the oscillation period is extended.

  Further, in response to self refresh activation signal SRE being set to “H” level, P channel MOS transistor 99 is turned off and N channel MOS transistor 114 is turned on. Therefore, the logic levels of nodes N26 to N28 are alternately switched in response to the logic level of node N25 being switched alternately. Therefore, the refresh request signal PHY having a predetermined cycle is output from the output node N28.

  Therefore, when the temperature of the device is high, the bias voltage generation circuit 34 controls the bias voltage VB to increase so that the oscillation cycle of the refresh request signal PHY is shortened. On the other hand, when the device temperature is low, the bias voltage control circuit 34 lowers the bias voltage VB so that the oscillation cycle of the refresh request signal PHY is increased. The self-refresh cycle in the self-refresh mode is determined according to the oscillation cycle of the refresh request signal PHY. As a result, the lower the temperature, the longer the self-refresh cycle, so that the current consumption in the self-refresh mode is reduced.

  Conventionally, the method of setting the refresh cycle corresponding to the temperature by the mode register 4 and the method of adjusting the refresh cycle by the positive temperature characteristic circuit 33 in a self-control manner have not been shared. For this reason, it is necessary to configure the circuit according to the user's request, and the productivity is poor.

  Referring to bias voltage control circuit 34 shown in FIG. 5, in the conventional bias voltage control circuit, N channel MOS transistor 77 is constituted by 12 N channel MOS transistors having a predetermined gate width connected in parallel. It was. Therefore, the current drive capability of N channel MOS transistor 77 is 1.5 times the current drive capability of N channel MOS transistor 81. Here, when the refresh control by the mode register 4 and the refresh control by the positive temperature characteristic circuit 33 are simply combined without providing the N-channel MOS transistors 71 and 72, the self-refresh cycle is controlled twice. Therefore, there is a possibility that appropriate control is not performed. For example, when the refresh control at a high temperature is guaranteed, the self-refresh cycle at a low temperature becomes longer than an appropriate value, and the refresh may be over. In this case, the data to be held is lost without being refreshed properly.

  Therefore, in the first embodiment, when the mode register 4 is set to the 85 ° C. mode or the 70 ° C. mode, the refresh control using the reference voltage VREFT from the positive temperature characteristic circuit 33 is performed. On the other hand, when the mode register 4 is set to the 45 ° C. mode or the 15 ° C. mode, refresh control using the reference voltage VREF from the reference voltage generating circuit 32 is performed. In addition, setting switching between the 70 ° C. mode and the 85 ° C. mode of the mode register 4 is invalidated, and setting switching between the 70 ° C. mode (or 85 ° C. mode), the 45 ° C. mode, and the 15 ° C. mode is enabled.

  For example, if the temperature of the device is higher than 70 ° C., even if the user switches the mode register 4 setting from the default 70 ° C. mode to the 85 ° C. mode after product shipment, the setting switching is invalidated and the refresh cycle depends on the temperature And is adjusted in a self-controlling manner. When the device temperature is lower than 70 ° C., the refresh cycle is set in the mode register 4 when the user switches the setting of the mode register 4 from the default 70 ° C. mode to the 45 ° C. mode or the 15 ° C. mode after product shipment. The period corresponding to the temperature is set. Therefore, the method of setting the refresh cycle corresponding to the temperature by the mode register and the method of adjusting the refresh cycle by the positive temperature characteristic circuit in a self-control manner can be shared without problems, and the productivity is improved. Further, since the self-refresh period can be appropriately controlled according to the temperature of the device, low power consumption can be realized.

  Here, the pseudo SRAM has been described as an example, but the same effect can be obtained in other semiconductor memory devices such as SDRAM.

Embodiment 2. FIG.
FIG. 8 is a block diagram showing a configuration of a portion related to refresh control according to the second embodiment of the present invention. In FIG. 8, the fuse units for singles 121 and 123, the news units for twins 122 and 124, the mode selection circuit 125, the refresh control circuit 126, the counter circuit 127 and the inverters 131 to 150 are provided in the control circuit 3 shown in FIG. It is done.

  Single fuse sections 121 and 123 include a plurality of (for example, three) fuse circuits 121a to 121c and 123a to 123c, respectively. Twin fuse sections 122 and 124 include a plurality of (for example, three) fuse circuits 122a to 122c and 124a to 124c, respectively.

  The output signal of the fuse circuit 121a is supplied to the refresh control circuit 126 as the control signal VR1 through the inverters 132 and 138. The output signal of the fuse circuit 121b is given to the refresh control circuit 126 as the control signal VR2 through the inverters 134 and 139. The output signal of fuse circuit 121c is applied to refresh control circuit 126 as control signal VR3 via inverters 136 and 140.

  The output signal of fuse circuit 122a is applied to refresh control circuit 126 as control signal VR1 through inverters 133 and 138. The output signal of the fuse circuit 122b is supplied to the refresh control circuit 126 as the control signal VR2 through the inverters 135 and 139. An output signal of the fuse circuit 122c is supplied to the refresh control circuit 126 as a control signal VR3 through inverters 137 and 140.

  The mode selection circuit 125 generates a selection signal STS for selecting either one of a single cell mode in which one bit is realized by one memory cell and a twin cell mode in which one bit is realized by two memory cells. Generate. In the inverters 132, 134, and 136, the high-side control terminal receives the selection signal STS via the inverter 131, and the low-side control terminal directly receives the selection signal STS. In the inverters 133, 135, and 137, the high-side control terminal directly receives the selection signal STS, and the low-side control terminal receives the selection signal STS via the inverter 131. Inverters 132 to 137 are tri-state inverters, and are activated when the input signals of the high-side control terminal and the low-side control terminal are a combination of “L” level and “H” level, respectively. And deactivated in combination with “L” level.

  The refresh control circuit 126 oscillates at a period corresponding to the control signals VR1, VR2, and VR3 from the inverters 138, 139, and 140, and generates a refresh request signal PHY with a predetermined period.

  The output signal of the fuse circuit 123a is supplied to the counter circuit 127 as the control signal VC1 through the inverters 142 and 148. The output signal of the fuse circuit 123b is supplied to the counter circuit 127 as the control signal VC2 through the inverters 144 and 149. The output signal of the fuse circuit 123c is supplied to the counter circuit 127 as the control signal VC3 through the inverters 146 and 150.

  The output signal of the fuse circuit 124a is given to the counter circuit 127 as the control signal VC1 through the inverters 143 and 148. The output signal of the fuse circuit 124b is supplied to the counter circuit 127 as the control signal VC2 through the inverters 145 and 149. The output signal of the fuse circuit 124c is supplied to the counter circuit 127 as the control signal VC3 through the inverters 147 and 150.

  In the inverters 142, 144, and 146, the high-side control terminal receives the selection signal STS via the inverter 141, and the low-side control terminal directly receives the selection signal STS. In the inverters 143, 145, and 147, the high-side control terminals directly receive the selection signal STS, and the low-side control terminals receive the selection signal STS via the inverter 141. Inverters 142 to 147 are tri-state inverters, and are activated when the input signals of the High side control terminal and the Low side control terminal are a combination of “L” level and “H” level, respectively, and “H” level. And deactivated in combination with “L” level.

  The counter circuit 127 divides the refresh request signal PHY from the refresh control circuit 126 at a frequency division ratio according to the control signals VC1, VC2, and VC3 from the inverters 148, 149, and 150 to generate the refresh request signal PHYC. .

  FIG. 9 is a circuit diagram showing a configuration of fuse circuit 121a shown in FIG. In FIG. 8, fuse circuit 121a includes a P channel MOS transistor 161, N channel MOS transistors 162 to 164, fuses 165 and 166, and inverters 167 and 168.

  P channel MOS transistor 161 and fuse 165 are connected in series between power supply potential VDD line and node N31. N channel MOS transistor 162 is connected between node N31 and a line of ground potential GND. The gates of P-channel MOS transistor 161 and N-channel MOS transistor 162 are both connected to the ground potential GND line.

  Fuse 166 and N channel MOS transistor 163 are connected in series between node N31 and a line of ground potential GND. N channel MOS transistor 163 has its gate receiving reference voltage VREF from reference voltage generating circuit 32 shown in FIG. 11 later. This reference voltage VREF is a constant level voltage slightly higher than the threshold voltage of N channel MOS transistor 163.

  Inverters 167 and 168 are connected in series between node N31 and the output node of fuse circuit 121a. N channel MOS transistor 164 is connected between node N31 and a line of ground potential GND. N channel MOS transistor 164 has its gate connected to a node between inverter 167 and inverter 168.

  During the wafer test, one of the fuses 165 and 166 is blown. First, a case where the fuse 165 is blown will be described. P-channel MOS transistor 161 is turned on when its gate receives ground potential GND, and N-channel MOS transistor 162 is turned off when its gate receives ground potential GND. Node N31 does not receive power supply potential VDD via P channel MOS transistor 161 because fuse 165 is blown. Since fuse 166 is not blown, node N31 receives ground potential GND through N-channel MOS transistor 163, and is set to "L" level. The logic level of the “L” level signal from node N31 is inverted twice by inverters 167 and 168, and the output signal of fuse circuit 121a is set to “L” level. N channel MOS transistor 164 is rendered conductive when its gate receives a signal at “H” level from inverter 167. Therefore, node N31 receives ground potential GND via N channel MOS transistor 164 and is fixed at "L" level.

  On the other hand, when fuse 166 is blown, node N31 does not receive ground potential GND via N channel MOS transistor 163. Since the fuse 165 is not blown, the node N31 receives the power supply potential VDD via the P-channel MOS transistor 161 and is set to the “H” level. The logic level of the “H” level signal from node N31 is inverted twice by inverters 167 and 168, and the output signal of fuse circuit 121a is set to “H” level. At this time, N-channel MOS transistor 164 becomes non-conductive when its gate receives a signal of “L” level from inverter 167. Therefore, node N31 does not receive ground potential GND via N channel MOS transistor 164, and is fixed at "H" level.

  As described above, the output signal of the fuse circuit 121a is set to the “H” level or the “L” level by the fuse blow during the wafer test. The fuse circuits 121a to 121c, 122a to 122c, 123a to 123c, and 124a to 124c have the same configuration and perform the same operation.

  FIG. 10 is a circuit diagram showing a configuration of mode selection circuit 125 shown in FIG. In FIG. 8, mode selection circuit 125 includes a bonding pad 171, P channel MOS transistors 172 to 175, and inverters 176 and 177.

  Bonding pad 171 brings its output node N41 to the floating state or “L” level by wire bonding. Output node N41 is set to a floating state in the single cell mode, and is set to "L" level in the twin cell mode.

  P channel MOS transistors 172 to 174 are connected in series between power supply potential VDD line and node N41, and their gates are both connected to ground potential GND line. Inverters 176 and 177 are connected in series between node N41 and the output node of mode selection circuit 125. P-channel MOS transistor 175 is connected between a power supply potential VDD line and node N41. P channel MOS transistor 175 has its gate connected to a node between inverter 176 and inverter 177.

  In the single mode, output node N41 is brought into a floating state. Node N41 receives power supply potential VDD via P channel MOS transistors 172 to 174, and is set to "H" level. The logic level of the “H” level signal from node N41 is inverted twice by inverters 167 and 168, and output selection signal STS of mode selection circuit 125 is set to “H” level. At this time, P-channel MOS transistor 175 has its gate turned on in response to an “L” level signal from inverter 176. Therefore, node N41 receives power supply potential VDD via P channel MOS transistor 175, and is fixed at "H" level.

  On the other hand, in the twin cell mode, output node N41 is set to the “L” level. The logic level of the “L” level signal from node N41 is inverted twice by inverters 167 and 168, and output selection signal STS of mode selection circuit 125 is set to “L” level. At this time, P channel MOS transistor 175 has its gate turned off in response to an “H” level signal from inverter 176. Therefore, node N41 does not receive power supply potential VDD via P channel MOS transistor 175, and is fixed at "L" level.

  Returning to FIG. 8, the output selection signal STS of the mode selection circuit 125 is set to the “H” level in the single cell mode and is set to the “L” level in the twin cell mode. In the single cell mode, in response to selection signal STS being set to “H” level, inverters 132, 134, 136 are activated, and inverters 133, 135, 137 are deactivated. Therefore, the output signals of fuse circuits 121a, 121b, and 121c are applied to refresh control circuit 126 as control signals VR1, VR2, and VR3 through inverters 132, 134, and 136 and inverters 138, 139, and 140, respectively.

  On the other hand, in the twin cell mode, in response to selection signal STS being set to “L” level, inverters 133, 135, 137 are activated and inverters 132, 134, 136 are deactivated. Therefore, the output signals of fuse circuits 122a, 122b, 122c are applied to refresh control circuit 126 as control signals VR1, VR2, VR3 through inverters 133, 135, 137 and inverters 138, 139, 140, respectively.

  FIG. 11 is a block diagram showing the configuration of the refresh control circuit 126 shown in FIG. 8, and is compared with FIG. Referring to the refresh control circuit 126 in FIG. 8, the difference from the refresh control circuit 31 in FIG. 3 is that the bias voltage control circuit 34 is replaced with a bias voltage control circuit 181. This bias voltage control circuit 181 receives control signals VR1, VR2 and VR3 from inverters 138, 139 and 140. In FIG. 11, portions corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 12 is a circuit diagram showing a configuration of the bias voltage control circuit 181 shown in FIG. 11, and is a diagram to be compared with FIG. Referring to bias voltage control circuit 181 in FIG. 12, difference from bias voltage control circuit 34 in FIG. 5 is that N channel MOS transistors 191 to 193 and P channel MOS transistors 194 to 196 are added. In FIG. 12, portions corresponding to those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.

  N channel MOS transistor 191 and P channel MOS transistor 194 are connected in series between a line of power supply potential VDD and node N11. N channel MOS transistor 192 and P channel MOS transistor 195 are connected in series between a line of power supply potential VDD and node N11. N channel MOS transistor 193 and P channel MOS transistor 196 are connected in series between a line of power supply potential VDD and node N11. The gate of N channel MOS transistor 191 receives control signal VR1, the gate of N channel MOS transistor 192 receives control signal VR2, and the gate of N channel MOS transistor 193 receives control signal VR3. The gates of P channel MOS transistors 194 to 196 are all connected to node N11.

  When all of control signals VR1, VR2, and VR3 are at "L" level, N channel MOS transistors 191 to 193 are rendered non-conductive, and therefore operation of bias voltage control circuit 181 is performed by bias voltage control circuit 34 shown in FIG. The operation is the same.

  When at least one of control signals VR1, VR2 and VR3 is at "H" level, an N channel MOS transistor whose gate receives an "H" level control signal among N channel MOS transistors 191 to 193 is turned on. In response, the potential of node N11 rises and the current flowing through P channel MOS transistor 64 decreases. For this reason, the potential (VB) of the output node N12 decreases. Further, when all of control signals VR1, VR2, and VR3 are at “H” level, the potential (VB) of output node N12 greatly decreases.

  As described above, the potential (VB) of the output node N12 is finely adjusted according to the combination of the logic levels of the control signals VR1, VR2, and VR3. In response to this, the oscillation cycle of the oscillation circuit 35 is controlled, and the cycle of the refresh request signal PHY is finely adjusted.

  Referring back to FIG. 8, in the single cell mode, in response to selection signal STS being set to “H” level, inverters 142, 144, 146 are activated and inverters 143, 145, 147 are deactivated. . Therefore, the output signals of fuse circuits 123a, 123b, 123c are applied to counter circuit 127 as control signals VC1, VC2, VC3 via inverters 142, 144, 146 and inverters 148, 149, 150, respectively.

  On the other hand, in the twin cell mode, inverters 143, 145, 147 are activated and inverters 142, 144, 146 are deactivated in response to selection signal STS being set to "L" level. Therefore, the output signals of fuse circuits 124a, 124b, 124c are applied to counter circuit 127 as control signals VC1, VC2, VC3 via inverters 143, 145, 147 and inverters 148, 149, 150, respectively.

  FIG. 13 is a block diagram showing a configuration of counter circuit 127 shown in FIG. In FIG. 13, the counter circuit 127 includes a counter input circuit 201, counters 202 to 204, a logic circuit 205, and a counter output circuit 206.

  Counter input circuit 201 generates clock signals CLKT and CLKL in response to refresh request signal PHY from refresh control circuit 126. The counter 202 generates a signal CY1 obtained by dividing the clock signal CLKT when the control signal VC1 is at “H” level. On the other hand, when the control signal VC1 is at “L” level, the reset operation is performed in response to the reset signal RST from the output circuit 206, and the clock signal CLKT is not divided. The counter 203 generates a signal CY2 obtained by dividing the output signal CY1 of the counter 202 when the control signal VC2 is at the “H” level. On the other hand, when the control signal VC2 is at the “L” level, the reset operation is performed in response to the reset signal RST from the output circuit 206, and the output signal CY1 of the counter 202 is not divided. The counter 204 generates a signal CY3 obtained by dividing the output signal CY2 of the counter 203 when the control signal VC3 is at the “H” level. On the other hand, when the control signal VC3 is at “L” level, the reset operation is performed in response to the reset signal RST from the output circuit 206, and the output signal CY2 of the counter 203 is not divided.

  The logic circuit 205 outputs an “L” level signal only when the output signals CY1 to CY3 of the counters 202 to 204 are all “H” level, and outputs an “H” level signal in other cases.

  The counter output circuit 206 generates a refresh request signal PHYC and a reset signal RST based on the output signal of the logic circuit 205 and the clock signal CLKL from the counter input circuit 201. Refresh request signal PHYC and reset signal RST are set to “H” level for a predetermined period in response to the output signal of logic circuit 205 being set to “L” level.

  FIG. 14 is a time chart showing the operation of the counter circuit 127 when all of the control signals VC1 to VC3 are at the “H” level. In FIG. 14, the refresh request signal PHY is a pulse signal train having a predetermined cycle. The counter input circuit 201 generates clock signals CLKT and CLKL having a predetermined cycle in response to the refresh request signal PHY.

  Counter 202 raises output signal CY1 to “H” level in response to clock signal CLKT being raised to “H” level at time t1, and clock signal CLKT is again brought to “H” level at time t3. The output signal CY1 is lowered to the “L” level in response to the rise. Thus, when the control signal VC1 is at “H” level, the counter 202 outputs a signal obtained by dividing the input clock signal CLKT as the signal CY1.

  Counter 203 raises output signal CY2 to "H" level in response to signal CY1 being raised to "H" level at time t1, and signal CY1 rises to "H" level again at time t4. In response to the increase, output signal CY2 falls to "L" level. Thus, when the control signal VC2 is at “H” level, the counter 203 outputs a signal obtained by dividing the input signal CY1 as the signal CY2.

  Counter 204 raises output signal CY3 to "H" level in response to signal CY2 being raised to "H" level at time t1, and signal CY2 rises to "H" level again at time t5. In response to the increase, output signal CY3 falls to "L" level. Thus, when the control signal VC3 is at “H” level, the counter 204 outputs a signal obtained by dividing the input signal CY2 as the signal CY3. Thus, counters 202, 203, and 204 do not perform a reset operation based on reset signal RST from counter output circuit 206 when control signals CY1 to CY3 are at "H" level, respectively.

  The counter output circuit 206 is refreshed in response to the clock signal CLKL falling to the “L” level with the output signals CY1 to CY3 of the counters 202 to 204 being set to the “H” level at time t2. Request signal PHYC and reset signal RST are raised to “H” level for a predetermined period. The counter circuit 127 generates a refresh request signal PHYC having a predetermined cycle by periodically repeating such an operation.

  FIG. 15 is a time chart showing the operation of the counter circuit 127 when the control signals VC1 and VC2 are at the “H” level and the control signal VC3 is at the “L” level, and is compared with FIG. Referring to the time chart of FIG. 15, the difference from the time chart of FIG. 14 is the waveforms of the signal CY3, the reset signal RST, and the refresh request signal PHYC. In FIG. 15, detailed description of portions corresponding to those in FIG. 14 is omitted.

  Counters 202 and 203 output signals obtained by dividing input signals CLKT and CY1 as signals CY1 and CY2, respectively, in response to control signals VC1 and VC2 being at “H” level. Counter 204 performs a reset operation based on reset signal RST from counter output circuit 206 in response to control signal CY3 being at "L" level. That is, at time t2, in response to the reset signal RST being raised to “H” level, the output signal CY3 is lowered to “L” level.

  The counter output circuit 206 is refreshed in response to the clock signal CLKL falling to the “L” level with the output signals CY1 to CY3 of the counters 202 to 204 being set to the “H” level at time t11. Request signal PHYC and reset signal RST are raised to “H” level for a predetermined period.

  At time t11, the counter 204 performs a reset operation again. That is, in response to the reset signal RST being raised to the “H” level, the output signal CY3 is lowered to the “L” level. The counter circuit 127 generates a refresh request signal PHYC having a predetermined cycle by periodically repeating such an operation. As described above, when the control signals VC1 and VC2 are at “H” level and the control signal VC3 is at “L” level, the control signals VC1 to VC3 are all at “H” level as shown in FIG. In comparison, the cycle of the generated refresh request signal PHYC is shortened.

  Although not shown, when one of the control signals VC1 to VC3 is at “H” level and the other two are at “L” level, the cycle of the refresh request signal PHYC is further shortened. As described above, the cycle of the refresh request signal PHYC becomes shorter as the “L” level of the control signals VC1 to VC3 increases.

  As described above, the frequency division ratio of the counter circuit 127 is controlled according to the combination of the logic levels of the control signals VC1, VC2, and VC3. Thereby, the cycle of the refresh request signal PHYC is adjusted. The self refresh cycle in the self refresh mode is determined according to the cycle of the refresh request signal PHYC. That is, the self-refresh cycle is adjusted by the control signals VC1, VC2, VC3.

  Returning to FIG. 8, the cycle of the refresh request signal PHY from the refresh control circuit 126 is finely adjusted by the control signals VR1 to VR3 generated by the single fuse unit 121 and the twin fuse unit 122. Therefore, the cycle of the refresh request signal PHY can be finely adjusted individually in the single cell mode and the twin cell mode. The cycle of the refresh request signal PHYC from the counter circuit 127 is adjusted by the control signals VC1 to VC3 generated by the single fuse unit 123 and the twin fuse unit 124. Therefore, the cycle of the refresh request signal PHYC can be individually adjusted in the single cell mode and the twin cell mode.

  Conventionally, since the same fuse circuit is provided in the single cell mode and the twin cell mode, when the mode switching between the single cell mode and the twin cell mode is performed by wire bonding, the self-refresh cycle is adjusted corresponding to each mode. I couldn't.

  Therefore, in the second embodiment, the single cell fuse portions 121 and 123 and the twin cell fuse portions 122 and 124 are provided and used by switching them by wire bonding. Thereby, the refresh control circuit 126 and the counter circuit 127 can be shared, and an appropriate self-refresh period can be set for each of the single cell mode and the twin cell mode. Therefore, productivity can be improved, and a low power consumption semiconductor device capable of appropriately controlling the self-refresh cycle can be realized.

  Here, the pseudo SRAM has been described as an example, but the same effect can be obtained in other semiconductor memory devices such as SDRAM.

Embodiment 3 FIG.
FIG. 16 is a block diagram showing a configuration of a part related to the test mode control according to the third embodiment of the present invention. In FIG. 16, a test mode circuit 211 is provided in the control circuit 3 shown in FIG.

  The mode register 4 generates a test mode enable signal TME according to external signals / CE, CLK, / ADV, CRE, / WE, ADD <20: 0>. The test mode circuit 211 is activated in response to the test mode enable signal TME from the mode register 4 being set to the activation level, and external signals / OE, / CE, CLK, / ADV, CRE, / WE. , ADD <20: 0>, the test mode entry signal TMENT is generated. The test mode circuit 211 switches the operation of the pseudo SRAM from the normal operation mode to the test mode by setting the test mode entry signal TMENT to the activation level. Although the address signal ADD <20: 0> is described as a 21-bit signal here, the number of bits of the address signal ADD is arbitrary.

  FIG. 17 is a circuit block diagram showing a configuration of mode register 4 shown in FIG. 17, this mode register 4 includes inverters 221, 222, and 224, logic circuits 223 and 225, flip-flops (FF) 231 to 233, data latch units 234 and 236, and a delay circuit 235.

  The flip-flop 231 operates in synchronization with the clock signal CLK, takes in the address valid signal / ADV through the inverter 221, holds the taken-in signal, and outputs it. The flip-flop 232 operates in synchronization with the clock signal CLK, takes in the register enable signal CRE, holds the taken-in signal, and outputs it. Flip-flop 233 operates in synchronization with clock signal CLK, captures write enable signal / WE via inverter 222, holds the captured signal, and outputs it.

  The logic circuit 223 outputs an “L” level signal only when the signals from the flip-flops 231 to 233 are all “H” level, and outputs an “H” level signal in other cases. The delay circuit 235 delays the output signal of the logic circuit 223 by a predetermined time and outputs it. One input terminal of the logic circuit 225 receives the output signal of the logic circuit 223 via the inverter 224, and the other input terminal receives the output signal of the logic circuit 223 via the delay circuit 235. Logic circuit 225 outputs clock signal CLKTM at “L” level when both signals from inverter 224 and delay circuit 235 are at “H” level, and at least one of signals from inverter 224 and delay circuit 235 is at least one of the signals. In the case of “L” level, an “H” level clock signal CLKTM is output.

  The data latch unit 234 performs a latch operation in response to the clock signal CLK, takes in the address signal ADD <20: 0>, and generates a signal DLO. The data latch unit 235 performs a latch operation in response to the clock signal CLKTM, takes in the output signal DLO of the data latch unit 234, and generates a test mode enable signal TME.

  18 is a circuit diagram showing a configuration of flip-flop 231 shown in FIG. In FIG. 18, flip-flop 231 includes inverters 241 to 245, P channel MOS transistors QP1 to QP4, and N channel MOS transistors QN1 to QN4.

  Inverter 241 inverts the logic level of clock signal CKL and outputs clock signal / CLK. P channel MOS transistor QP1 and N channel MOS transistor QN1 are both connected between input node N51 and node N52. P channel MOS transistor QP1 has its gate receiving clock signal CLK, and N channel MOS transistor QN1 has its gate receiving clock signal / CLK.

  Inverters 242, 243 are connected in series between nodes N52 and N53. P channel MOS transistor QP2 and N channel MOS transistor QN2 are both connected between nodes N53 and N52. P channel MOS transistor QP2 has its gate receiving clock signal / CLK, and N channel MOS transistor QN2 has its gate receiving clock signal CLK.

  P channel MOS transistor QP3 and N channel MOS transistor QN3 are both connected between nodes N53 and N54. P channel MOS transistor QP3 has its gate receiving clock signal / CLK, and N channel MOS transistor QN3 has its gate receiving clock signal CLK.

  Inverters 244 and 245 are connected in series between node N54 and output node N55. P channel MOS transistor QP4 and N channel MOS transistor QN4 are both connected between output node N55 and node N54. P channel MOS transistor QP4 has its gate receiving clock signal CLK, and N channel MOS transistor QN4 has its gate receiving clock signal / CLK.

  FIG. 19 is a time chart showing the operation of the flip-flop 231 shown in FIG. Referring to FIG. 19, flip-flop 231 is supplied with a clock signal CLK having a predetermined period. At time t21, clock signal CLK is at “L” level and clock signal / CLK is at “H” level. In response, P channel MOS transistor QP1 and N channel MOS transistor QN1 are turned on, and P channel MOS transistor QP2 and N channel MOS transistor QN2 are turned off. Therefore, at time t21, node N53 is raised to “H” level in response to input node N51 being raised to “H” level. In response to clock signal / CLK being at “H” level and clock signal CLK being at “L” level, P channel MOS transistor QP3 and N channel MOS transistor QN3 are rendered non-conductive, and P channel MOS transistor QP4 and N channel MOS transistor QN4 are conductive. Therefore, the potential change at node N53 is not transmitted to node N54, and output node N55 maintains the “L” level.

  At time t22, clock signal CLK is raised to “H” level, and clock signal / CLK is lowered to “L” level. In response, P channel MOS transistor QP1 and N channel MOS transistor QN1 are turned off, and P channel MOS transistor QP2 and N channel MOS transistor QN2 are turned on. Therefore, the potential change of input node N51 is not transmitted to node N52, and node N53 maintains the “H” level until time t23 when clock signal CLK is subsequently lowered to the “L” level. In response to clock signal / CLK falling to "L" level and clock signal CLK rising to "H" level, P channel MOS transistor QP3 and N channel MOS transistor QN3 conduct, Channel MOS transistor QP4 and N channel MOS transistor QN4 are rendered non-conductive. Therefore, the potential of node N53 ("H" level) is transmitted to node N54, and output node N55 is raised to "H" level.

  At a certain time between time t22 and time t23, input node N51 falls to "L" level. At time t23, clock signal CLK is lowered to "L" level, and clock signal / CLK is raised to "H" level. In response, P channel MOS transistor QP1 and N channel MOS transistor QN1 are turned on, and P channel MOS transistor QP2 and N channel MOS transistor QN2 are turned off. Therefore, the potential (“L” level) of input node N51 is transmitted to node N52, and node N53 falls to “L” level. In response to clock signal / CLK rising to "H" level and clock signal CLK falling to "L" level, P channel MOS transistor QP3 and N channel MOS transistor QN3 are rendered non-conductive. P channel MOS transistor QP4 and N channel MOS transistor QN4 are rendered conductive. Therefore, the potential change at node N53 is not transmitted to node N54, and remains at "H" level until output node N55 and then at time t24 when clock signal CLK is raised to "H" level.

  At time t24, clock signal CLK is raised to “H” level, and clock signal / CLK is lowered to “L” level. In response, P channel MOS transistor QP1 and N channel MOS transistor QN1 are turned off, and P channel MOS transistor QP2 and N channel MOS transistor QN2 are turned on. Therefore, the node N53 holds the “L” level. In response to clock signal / CLK falling to "L" level and clock signal CLK rising to "H" level, P channel MOS transistor QP3 and N channel MOS transistor QN3 conduct, Channel MOS transistor QP4 and N channel MOS transistor QN4 are rendered non-conductive. Therefore, the potential of node N53 ("L" level) is transmitted to node N54, and output node N55 is lowered to "L" level.

  As described above, the flip-flop 231 holds the output signal of the inverter 221 in synchronization with the clock signal CLK, and supplies the held signal to the logic circuit 223. Note that the flip-flops 232 and 233 illustrated in FIG. 17 have the same configuration as the flip-flop 231 and perform the same operation.

  FIG. 20 is a circuit block diagram showing a configuration of data latch unit 234 shown in FIG. In FIG. 20, data latch unit 234 includes a plurality of latch circuits (DL) 251 corresponding to address signals ADD <20> to ADD <0>, respectively.

  Latch circuit 251 includes inverters 261 to 263, P channel MOS transistors QP11 and QP12, and N channel MOS transistors QN11 and QN12.

  Inverter 261 inverts the logic level of clock signal CKL and outputs clock signal / CLK. Input node N61 receives address signal ADD <20>. P channel MOS transistor QP11 and N channel MOS transistor QN11 are both connected between input node N61 and node N62. P channel MOS transistor QP11 has its gate receiving clock signal CLK, and N channel MOS transistor QN11 has its gate receiving clock signal / CLK.

  Inverters 262 and 263 are connected in series between node N62 and output node N63. P channel MOS transistor QP12 and N channel MOS transistor QN12 are both connected between output node N63 and node N62. P channel MOS transistor QP12 has its gate receiving clock signal / CLK, and N channel MOS transistor QN12 has its gate receiving clock signal CLK. Signal DLO <20> is output from output node N63.

  FIG. 21 is a time chart showing the operation of the latch circuit 251 shown in FIG. Referring to FIG. 21, the latch circuit 251 is supplied with a clock signal CLK having a predetermined cycle. At time t31, clock signal CLK is at “L” level and clock signal / CLK is at “H” level. In response, P channel MOS transistor QP11 and N channel MOS transistor QN11 are turned on, and P channel MOS transistor QP12 and N channel MOS transistor QN12 are turned off. Therefore, at time t31, in response to input address signal ADD <20> being raised to “H” level, output signal DLO <20> is raised to “H” level.

  At time t32, clock signal CLK is raised to “H” level, and clock signal / CLK is lowered to “L” level. In response, P channel MOS transistor QP11 and N channel MOS transistor QN11 are rendered non-conductive, and P channel MOS transistor QP12 and N channel MOS transistor QN12 are rendered conductive. Therefore, the potential change of input address signal ADD <20> is not transmitted to node N62, and output signal DLO <20> remains at “H” level until time t33 when clock signal CLK is subsequently lowered to “L” level. Hold.

  At a certain time between time t32 and time t33, input address signal ADD <20> falls to "L" level. At time t33, clock signal CLK is lowered to "L" level, and clock signal / CLK is raised to "H" level. In response, P channel MOS transistor QP11 and N channel MOS transistor QN11 are turned on, and P channel MOS transistor QP12 and N channel MOS transistor QN12 are turned off. Therefore, the potential (“L” level) of input address signal ADD <20> is transmitted to node N62, and output signal DLO <20> is lowered to “L” level.

  Thus, the latch circuit 251 latches the input address signal ADD <20> in response to the rising edge of the clock signal CLK, and outputs the signal DLO <20> to the data latch unit 236. Note that the plurality of latch circuits 251 shown in FIG. 20 have the same configuration and perform the same operation.

  FIG. 22 is a time chart showing the operation of the mode register 4 shown in FIG. Referring to FIG. 22, at time t41, address valid signal / ADV and write enable signal / WE are lowered to "L" level, and register enable signal CRE is raised to "H" level. That is, all the input signals of flip-flops 231 to 233 are raised to “H” level.

  At time t42, all the output signals of flip-flops 231 to 233 are raised to “H” level in response to clock signal CLK being raised to “H” level. In response, the output signal of logic circuit 223 falls to “L” level for a predetermined period. Since the output signal of logic circuit 223 is applied to logic circuit 225 via inverter 224 and delay circuit 235, output clock signal CLKTM of logic circuit 225 has a one-shot pulse that is lowered to "L" level at time t43. Signal. The output clock signal CLKTM of the logic circuit 225 indicates that the address valid signal / ADV and the write enable signal / WE are raised to “H” level and the register enable signal CRE is lowered to “L” level at time t45. Accordingly, it is raised to “H” level.

  The data latch unit 234 takes in the data X of the input address signal ADD <20: 0> at time 41 and outputs it as a signal DLO <20: 0>. At time t42, data X is latched in response to the rising edge of clock signal CLK, and data X is held for a period until clock signal CLK falls to “L” level at time t46.

  Next, the operation of the data latch unit 236 will be described. FIG. 23 is a circuit block diagram showing a configuration of data latch unit 236 shown in FIG. In FIG. 23, data latch unit 236 includes a plurality of latch circuits (DL) 271, inverters 281, 282, 284, 286 and logic circuits 283, 285 corresponding to signals DLO <20> to DLO <0>, respectively. .

  Each of the plurality of latch circuits 271 has the same configuration as the latch circuit 251 shown in FIG. 20, and performs the same operation. That is, the plurality of latch circuits 271 corresponding to the signals DLO <20> to DLO <0> respectively latch the signals DLO <20> to DLO <0> in response to the rising edge of the clock signal CLKTM.

  The first input terminal of the logic circuit 283 receives the signal DLO <20> via the latch circuit 271 and the inverter 281, the second input terminal receives the signal DLO <19> via the latch circuit 271, and the third input terminal Signal DLO <18> is received through latch circuit 271 and inverter 282. The logic circuit 283 outputs an “L” level signal only when the signals of the first to third input terminals are all at the “H” level, and outputs an “H” level signal in the other cases.

  One input terminal of the logic circuit 285 receives the output signal of the logic circuit 283 via the inverter 284, and the other input terminal receives the signal DLO <0> via the latch circuit 271. The logic circuit 285 sets the output signal to the “L” level when the signals at the two input terminals are both “H” level, and outputs the output signal when at least one of the signals at the two input terminals is at the “L” level. Set to “H” level. Inverter 286 inverts the logic level of the output signal of logic circuit 285 and outputs test mode enable signal TME.

  A portion corresponding to signals DLO <17> to DLO <1> is used for setting a normal internal operation mode. Therefore, signals DLO <20> to DLO <18>, DLO <0> that are not used in the normal internal operation mode are used for the test mode control.

  Referring to FIGS. 17 and 22, data latch unit 236 takes in and takes in signal DLO <20: 0> in response to clock signal CLKTM falling to “L” level at time t43. In response to signal DLO <20: 0>, output test mode enable signal TME is raised to the activation level “H” level. At time t45, latch operation is performed in response to clock signal CLKTM being raised to "H" level, and output test mode enable signal TME is fixed to "H" level of the activation level.

  Returning to FIG. 16, the test mode circuit 211 is activated in response to the test mode enable signal TME from the mode register 4 being set to the “H” level of the activation level. FIG. 24 is a circuit block diagram showing a configuration of test mode circuit 211 shown in FIG. 24, test mode circuit 211 includes inverters 291 to 293, 295, 297, logic circuits 294 and 297, and flip-flops 301 to 303 and 304. Here, the flip-flops 301 to 303 and 304 have the same configuration as the flip-flop 231 shown in FIG. 18 and perform the same operation.

  Inverters 291 to 293 invert the logic levels of signals / ADV, / WE, / OE, respectively, and output them. Logic circuit 294 outputs an “L” level signal only when test mode enable signal TME and the output signals of inverters 291 and 292 are all at “H” level, and outputs an “H” level signal in other cases. To do. Inverter 295 inverts the logic level of the signal from logic circuit 294 and outputs the result.

  Flip-flop 301 holds the output signal of inverter 295 in synchronization with clock signal CLK, and supplies the held signal to flip-flop 302 and logic circuit 296. The flip-flop 302 holds the output signal of the flip-flop 301 in synchronization with the clock signal CLK, and supplies the held signal to the flip-flop 303 and the logic circuit 296. The flip-flop 303 holds the output signal of the flip-flop 302 in synchronization with the clock signal CLK, and supplies the held signal to the logic circuit 296.

  Logic circuit 296 outputs an “L” level signal only when the output signals of flip-flops 301 to 303 are all at “H” level, and outputs an “H” level signal in other cases. The inverter 297 inverts the logic level of the signal from the logic circuit 296 and outputs the inverted signal.

  The flip-flop 304 holds the output signal of the inverter 293 in synchronization with the output signal of the inverter 297, and outputs the held signal as the test mode entry signal TMENT.

  FIG. 25 is a time chart showing the operation of the test mode circuit 211 shown in FIG. Referring to FIG. 25, the signal waveform in the period up to time t51 (including times t41 and t44) corresponds to the signal waveform shown in FIG.

  At time t44, test mode circuit 211 is activated in response to test mode enable signal TME from mode register 4 being raised to the “H” level of the activation level.

  At times t51, t52, and t53, signals / ADV and / WE are lowered to “L” level three times in succession. In response to this, all the output signals of flip-flops 301 to 303 are set to “H” level, and inverter 297 outputs a clock signal of a one-shot pulse. Flip-flop 304 takes in the output signal of inverter 293 (inverted signal of signal / OE) in response to the one-shot pulse clock signal from inverter 297, and at time t54, output test mode entry signal TMENT is activated. Raise to “H” level. In response to this, the pseudo SRAM shown in FIG. 1 is set to the test mode.

  In FIG. 23, when the test mode control is performed, the signals DLO <20> and DLO <18> are set to the “L” level, and the signals DLO <19> and DLO <0> are set to the “H” level. For the following reasons. Since the plurality of latch circuits 271 corresponding to the signals DLO <20> to DLO <0> all have the same circuit configuration, all the latch circuits 271 may be initialized to “H” level when the power is turned on. . Therefore, the signals DLO <17> to DLO <1> used in the internal operation mode are set to the “L” level, and the signals DLO <20> to DLO <18> and DLO <0> used in the test mode control are set to “H”. When the test mode control is performed by setting the level, if all the latch circuits 271 are initially set to the “H” level when the power is turned on, the test mode may be erroneously set. However, in the third embodiment, when the signals DLO <20> and DLO <18> are “L” level and the signals DLO <19> and DLO <0> are “H” level, the test mode enable signal TME is set. The activation level is raised to “H” level. Therefore, even when all the latch circuits 271 are initially set to “H” level when the power is turned on, the test mode is not erroneously entered.

  The conventional test mode circuit performs test mode control using only external signals / OE, / CE, CLK, / ADV, CRE, / WE, and ADD <20: 0>. For this reason, in the normal operation mode, when noise is mixed in the external signals / OE, / CE, CLK, / ADV, CRE, / WE, ADD <20: 0>, the test mode is erroneously entered. There was a case. Further, in order to prevent the test mode from being erroneously set in this way, a high voltage that is not used in the normal operation mode is applied to the external terminal in the test mode. For this reason, a problem has arisen in the reliability of the transistor due to the influence of the high voltage.

  However, in the third embodiment, when the test mode circuit 211 is activated by the mode register 4, the signal / OE, / CE, CLK, / ADV, CRE, / WE, ADD <20: 0> is set. In response, test mode entry signal TMENT is generated. That is, test mode circuit 211 does not perform test mode control unless it is activated by mode register 4. Therefore, in the normal operation mode, even when noise is mixed in an external signal, the test mode is not entered. Therefore, the reliability of the operation of the semiconductor memory device is improved.

  Here, the pseudo SRAM has been described as an example, but the same effect can be obtained in other semiconductor memory devices such as SDRAM.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing an overall configuration of a pseudo SRAM according to a first embodiment of the present invention. FIG. 2 is a circuit block diagram showing a configuration of a memory array and related parts shown in FIG. 1. FIG. 3 is a block diagram showing a configuration of a refresh control circuit that performs self-refresh control and a mode register. FIG. 4 is a circuit diagram showing a configuration of a positive temperature characteristic circuit shown in FIG. 3. FIG. 4 is a circuit diagram showing a configuration of a bias voltage control circuit shown in FIG. 3. FIG. 4 is a diagram showing a list of correspondence relationships between temperature condition data A3 and A4, refresh configuration instruction data SRT <0> and SRT <1> stored in a mode register 4 shown in FIG. 3, and temperatures. FIG. 4 is a circuit diagram illustrating a configuration of the oscillation circuit illustrated in FIG. 3. It is a block diagram which shows the structure of the part relevant to the refresh control by Embodiment 2 of this invention. FIG. 9 is a circuit diagram showing a configuration of a fuse circuit shown in FIG. 8. FIG. 9 is a circuit diagram showing a configuration of a mode selection circuit shown in FIG. 8. FIG. 9 is a block diagram showing a configuration of a refresh control circuit shown in FIG. 8. FIG. 12 is a circuit diagram showing a configuration of a bias voltage control circuit shown in FIG. 11. It is a block diagram which shows the structure of the counter circuit shown in FIG. 6 is a time chart showing the operation of the counter circuit when all of control signals VC1 to VC3 are at “H” level. 7 is a time chart showing the operation of the counter circuit when the control signals VC1 and VC2 are at “H” level and the control signal VC3 is at “L” level. It is a block diagram which shows the structure of the part relevant to the test mode control by Embodiment 3 of this invention. FIG. 17 is a circuit block diagram showing a configuration of a mode register shown in FIG. 16. FIG. 18 is a circuit diagram illustrating a configuration of a flip-flop 231 illustrated in FIG. 17. 19 is a time chart illustrating an operation of the flip-flop 231 illustrated in FIG. 18. FIG. 18 is a circuit block diagram illustrating a configuration of a data latch unit 234 illustrated in FIG. 17. 21 is a time chart illustrating an operation of the latch circuit illustrated in FIG. 20. 18 is a time chart showing an operation of the mode register shown in FIG. FIG. 18 is a circuit block diagram illustrating a configuration of a data latch unit 236 illustrated in FIG. 17. FIG. 17 is a circuit block diagram showing a configuration of a test mode circuit shown in FIG. 16. 25 is a time chart showing an operation of the test mode circuit shown in FIG. 24.

Explanation of symbols

  1 address buffer, 2 control signal buffer, 3 control circuit, 4 mode register, 5 memory array, 6 IO buffer, 11 row decoder, 12 column decoder, 21 column selection gate, 22 sense amplifier, 23 equalizer, 31, 126 refresh control Circuit, 32,181 reference voltage generation circuit, 33 positive temperature characteristic circuit, 34 bias voltage control circuit, 35 oscillation circuit, 41, 42, 71-82, 101-115, 162-164 N-channel MOS transistor, 43, 44, 63, 64, 91 to 100, 161, 172 to 175, 191 to 196 P-channel MOS transistor, 45 resistance element, 51 to 56, 67, 167, 168, 176, 177, 221, 222, 224, 241-245 261 to 263, 281, 282, 28 , 286, 291-293, 295, 297 Inverter, 57-60, 205, 223, 225, 283, 285, 294, 297 Logic circuit, 61 Voltage selection unit, 62 Voltage control unit, 65 Register input unit, 66 EX- OR gate, 121,123 single fuse part, 121a-121c, 122a-122c, 123a-123c, 124a-124c fuse circuit, 122,124 twin news part, 125 mode selection circuit, 127 counter circuit, 165,166 fuse 171 Bonding pad 201 Counter input circuit 202-204 Counter 206 Counter output circuit 211 Test mode circuit 231-233 301-303 Flip-flop 234 236 Data latch unit 2 5 delay circuit, 251,271 latch circuit, QP1~QP4, QP11, QP12 P-channel MOS transistor, Qn1 to Qn4, QN11, QN12 N-channel MOS transistor.

Claims (10)

A semiconductor memory device,
Multiple memory cells arranged in multiple rows and multiple columns,
A mode register that stores data indicating temperature conditions,
When the temperature condition indicated by the data specified by the external signal and stored in the mode register is within the first range, the refresh cycle is set based on the data stored in the mode register and specified by the external signal. When the temperature condition indicated by the data stored in the mode register is in the second range, a refresh cycle is set by self-control based on the temperature of the semiconductor memory device, and a refresh request signal of the set refresh cycle is generated And a refresh execution circuit for sequentially selecting the plurality of memory cells in synchronization with the refresh request signal and refreshing data stored in the selected memory cells. The signal generation circuit includes:
When the temperature condition indicated by the data stored in the mode register is in the first range, a bias voltage corresponding to the data stored in the mode register is generated, and the data stored in the mode register indicates When the temperature condition is in the second range, a bias voltage generation circuit that generates a bias voltage corresponding to the temperature of the semiconductor memory device, and a cycle corresponding to the bias voltage generated by the bias voltage generation circuit The semiconductor memory device according to claim 1, further comprising an oscillation circuit that generates a refresh request signal. The bias voltage generation circuit includes:
A first reference voltage generating circuit for generating a first reference voltage having temperature dependence;
A second reference voltage generating circuit for generating a second reference voltage having substantially no temperature dependence as compared with the first reference voltage, and a temperature condition indicated by data stored in the mode register is the first reference voltage When the temperature condition indicated by the data stored in the mode register is within the second range, a current corresponding to the second reference voltage is applied to the predetermined node. A selection circuit for supplying a current corresponding to the reference voltage of the predetermined node to the predetermined node;
A plurality of resistance elements each provided corresponding to a plurality of temperature conditions, each having a resistance value corresponding to the corresponding temperature condition, and a temperature indicated by data stored in the mode register among the plurality of resistance elements A switching circuit for connecting a resistance element corresponding to a condition between the predetermined node and a reference potential line;
The semiconductor memory device according to claim 2, wherein the bias voltage is output from the predetermined node.   Among the plurality of resistance elements, the plurality of resistance elements corresponding to the temperature condition in the first range have different resistance values, and the plurality of resistance elements corresponding to the temperature condition in the second range are the same. The semiconductor memory device according to claim 3, having a resistance value.   5. The semiconductor memory device according to claim 1, wherein when the external signal is not input, a temperature condition indicated by data stored in the mode register is in the second range. 6. A semiconductor memory device,
Multiple memory cells arranged in multiple rows and multiple columns,
A selection circuit for selecting one of a single cell mode for storing 1-bit data in one memory cell and a twin-cell mode for storing 1-bit data in two memory cells;
A first fuse circuit for storing a signal indicating a refresh cycle in the single cell mode;
A second fuse circuit for storing a signal indicating a refresh cycle in the twin cell mode;
When the single cell mode is selected by the selection circuit, a refresh request signal having a refresh period corresponding to the signal stored in the first fuse circuit is generated, and the twin cell mode is selected by the selection circuit. A signal generation circuit for generating a refresh request signal having a refresh period corresponding to the signal stored in the second fuse circuit, and the plurality of the synchronization signals generated in synchronization with the refresh request signal generated by the signal generation circuit. A semiconductor memory device comprising a refresh execution circuit that sequentially selects memory cells and refreshes storage data of the selected memory cells. The first fuse circuit includes:
A first sub-fuse circuit for storing a signal indicating an oscillation period, and a second sub-fuse circuit for storing a signal indicating a frequency division ratio;
The second fuse circuit includes:
A third sub-fuse circuit for storing a signal indicating an oscillation period, and a fourth sub-fuse circuit for storing a signal indicating a frequency division ratio;
The signal generation circuit includes:
When the single cell mode is selected by the selection circuit, it oscillates in a cycle according to the signal stored in the first sub-fuse circuit, and when the twin cell mode is selected by the selection circuit, An oscillation circuit that oscillates at a period corresponding to a signal stored in the third sub-fuse circuit; and when the single-cell mode is selected by the selection circuit, a signal stored in the second sub-fuse circuit When the twin cell mode is selected by the selection circuit, the frequency division ratio according to the signal stored in the fourth fuse circuit is divided by the frequency division ratio according to Including a counter circuit that divides the output signal of the oscillation circuit.
The semiconductor memory device according to claim 6, wherein an output signal of the counter circuit is the refresh request signal.   The selection circuit includes a pad, and selects the single cell mode when the pad is in a floating state, and selects the twin cell mode when the potential of the pad is set to a reference level by wire bonding. The semiconductor memory device according to claim 6 or 7. A semiconductor memory device,
A mode register for outputting an activation signal in response to the logic levels of a plurality of external signals being set to a first predetermined combination;
In response to the activation signal being input from the mode register and the logic levels of the plurality of external signals being input for a predetermined number of clocks in a predetermined second combination. A semiconductor memory device comprising a test mode circuit for outputting a test mode entry signal indicating a mode.   The semiconductor memory device according to claim 9, wherein logic levels of the plurality of external signals in the predetermined first combination are not the same.

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