JP2008004249A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which power consumption can be further reduced in a standby mode. <P>SOLUTION: When a control signal STBY is input to a power source managing part 40 and asserted, upon receiving it, the power source managing part 40 asserts control signals PD, /PD instructing power reduction. Thereby, supply of the power source for an I/O part 20 is cut off. Also, a control part 30 executes intensive refresh for a memory cell array 15 by assert of a refresh instruction signal/SREF. After refresh operation of a whole memory space is completed, the refresh instruction signal/SREF is negated. After the refresh instruction signal/SREF is negated, a control signal ALIVE is negated, and supply of external power source voltage VDD and ground voltage GND for a power source control circuit 35 is cut off. Before refresh operation, power source supply for the power source control circuit 35 is executed again, and refresh operation is executed. These operations are repeated for each refresh period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a dynamic random access memory (DRAM; DRAM core; memory core) integrated in a system LSI. More specifically, the present invention relates to a configuration for reducing current consumption during standby of a DRAM core.

In recent years, attention has been drawn to a system LSI in which a logic circuit such as a processor and a memory circuit are integrated on the same semiconductor chip in order to process data at high speed in the image data processing field. In this system LSI, since the logic circuit and the memory circuit are interconnected by on-chip wiring, the following effects can be obtained:
(1) The load of the signal wiring is smaller than the wiring on the board, and it is possible to transmit data or signals at high speed.
(2) Since the number of pins is not restricted, the data bus width can be increased, and the data transfer bandwidth can be increased.
(3) Since each component is integrated on the same semiconductor chip, it is possible to realize a small and lightweight system, and (4) a macro that is made into a library as a component formed on the semiconductor chip. The design efficiency can be improved.

  For these reasons, system LSIs are now widely used in various fields as SOC (system on chip) and the like.

  Examples of the memory circuit used in the system LSI include memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Examples of the logic circuit include a processor for performing control and data processing, an analog processing circuit such as an A / D (analog / digital) conversion circuit, and a logic circuit for performing dedicated logic processing.

In a DRAM used as a memory circuit, data is stored by storing electric charge in a capacitor of a memory cell. Therefore, a so-called refresh operation is required to hold data. However, since the structure of the memory cell is relatively simple, a memory circuit having a large storage capacity can be manufactured at low cost. For this reason, DRAMs are used as indispensable embedded memories in system LSIs where the amount of information processing will increase in the future, and will become increasingly important in the future. Non-Patent Document 1 shows a case where a DRAM is used as a mixed memory.
N. Watanabe et al., "An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester", IEICE Trans. Electron., Vol. E86-C, No. 4 APRIL 2003, pp. 624-632

  As described above, the DRAM is a system in which data is stored by storing electric charges in a capacitor in a memory cell. Accordingly, the accumulated charge is lost over time due to various leakage currents, for example, junction leakage current at the storage node, channel leakage current of the transistor in the memory cell, gate leakage current of the capacitor insulating film, and the like. .

  Therefore, it is necessary to repeat the refresh operation for holding data in the memory cells over the entire memory space in the DRAM within the refresh time tREF determined by the memory cell having the shortest data holding characteristic in the chip. There is. Here, the refresh time indicates a time interval in which one memory cell is focused and refreshed with respect to this focused memory cell.

  Therefore, in the DRAM, it is necessary to repeat a series of refresh operations even in a standby mode period in which data access is not performed. During this refresh operation, an AC consumption current for driving the DRAM memory array, and a DC consumption current due to an off-current (off-leakage current) of the transistors constituting the memory array and its peripheral circuits flow. . For this reason, a current of a level that cannot be ignored continues to flow even during standby.

  In particular, in recent years, there has been a demand for lower power consumption of devices, and there are many products with strict current consumption specification values in standby mode, and reducing power consumption in standby mode has become an important issue.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor integrated circuit device capable of further reducing power consumption in the standby mode.

  In summary, in the standby mode, the present invention intensively refreshes some memory cells in the memory array every refresh time, and after the refresh is completed, the supply of the power supply voltage to the internal voltage generation circuit is cut off. Then, the generation of the internal voltage is stopped. Preferably, the refresh time is adjusted according to the operating temperature (chip temperature).

  In one embodiment, a semiconductor integrated circuit device according to the present invention is synchronized with a refresh clock in accordance with a memory array having a plurality of memory cells and a refresh instruction signal based on a predetermined refresh time for the memory array. A control circuit for sequentially executing a refresh operation for each part of the memory cells of the memory array, an internal voltage generation circuit for receiving an external power supply voltage and generating an internal voltage for executing a predetermined operation of the memory array; A management unit for controlling power supply of the semiconductor integrated circuit. The internal voltage generation circuit includes a first power cut-off switch that cuts off the supply of the external power supply voltage in response to the instruction. In the standby mode, the control circuit executes a refresh operation in response to an input of a refresh instruction signal based on the refresh time. The management unit instructs the first power cut-off switch to cut off the supply of the external power supply voltage after completion of the refresh operation in the standby mode, and the external power supply to the first power cut-off switch before executing the refresh operation. Instruct the supply of voltage.

  In another embodiment, the semiconductor integrated circuit device according to the present invention detects the operating temperature (chip temperature) of the semiconductor integrated circuit device and adjusts the refresh time according to the detected temperature.

  In the present invention, in the standby mode, the supply of power to the internal circuit is stopped except during the period for performing the refresh operation. Therefore, AC and DC currents do not flow, and current consumption can be reduced.

The semiconductor integrated circuit device according to one embodiment of the present invention instructs the first power cut-off switch to cut off the supply of the external power supply voltage after completion of the refresh operation in the standby mode, and before executing the refresh operation. Is instructed to supply the external power supply voltage. Therefore, in the standby mode, the supply of the external power supply voltage is cut off during a period when the refresh operation is not performed, and the power consumption can be further reduced in the standby mode.

  In another embodiment, the refresh time is adjusted according to the operating temperature (chip temperature), so that a refresh time can be set according to the operating environment, and the current consumption required for refreshing is further reduced. can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic block diagram of a system LSI 1 according to the first embodiment of the present invention. Referring to FIG. 1, system LSI 1 according to the first embodiment of the present invention shows a configuration in which a logic circuit such as a processor and a memory circuit are integrated on the same semiconductor chip.

  FIG. 1 shows, as an example, a case where three types of memory circuits MEM1 to MEM3, logic circuits LGC1 and LGC2, and an analog circuit ANG are integrated on one semiconductor chip. Examples of the memory circuit include DRAM, SRAM, and nonvolatile RAM.

  Each circuit block receives a high-side and low-side external power supply voltage VDD and an external power supply voltage GND (hereinafter also referred to as a ground voltage) from the pad PAD, and executes a predetermined operation.

  In the following, the configuration of a DRAM integrated as a large-capacity memory circuit MEM1 will be described as an example.

  FIG. 2 is a diagram illustrating memory circuit MEM1 and its peripheral circuits according to the first embodiment of the present invention.

  Referring to FIG. 2, memory circuit MEM1 according to the first embodiment of the present invention includes a memory array 15 having memory cells MC arranged in a matrix, and an array drive control unit 25 for driving the memory array. And an I / O (input / output) 20 for transferring data to the memory array 15.

  The I / O unit 20 operates by receiving the power supply voltage VDD and the ground voltage GND directly from the outside. For example, when the input / output data for the memory array 15 is 64 bits, the I / O unit 20 is input / output to / from the memory array 15. Exchange of input data DIN [63: 0] and output data Q [63: 0].

  The memory circuit MEM1 further controls the memory array 15, the array drive control unit 25 and the I / O unit 20 as a whole, and the internal voltage which is an operating voltage for the array drive control unit 25 and the control unit 30. Power supply control circuit 35 to be supplied.

The power supply control circuit 35 is supplied with the external power supply voltage VDD and the ground voltage GND, and in response to the instruction, supplies the internal voltages VPP, VBB, VCP, VBL, VDDT to the memory array 15,
This is supplied to the array drive control unit 25 and the control unit 30. In this example, the case where the external power supply voltage VDD is mainly supplied as the high-side external power supply voltage will be described. However, the present invention is not particularly limited to this, and an external power supply voltage VDDH different from the high-side external power supply voltage VDD may be supplied.

  In addition, as a peripheral circuit, a power management unit 40 for managing power supply and the like for the memory circuit MEM1 is provided, for example, in a logic circuit. Note that, as an example, a configuration in which a power management unit is provided in a logic circuit or the like will be described. The power management unit 40 may be disposed around the DRAM core on the same semiconductor chip as the memory circuit (DRAM core).

  The power management unit 40 controls the power supply of the I / O unit 20 and the power control circuit 35 based on the control signal (standby mode instruction signal) STBY and the clock signal CLK, and controls the internal clock signal intCLK and the control unit 30. A refresh instruction signal / SREF for instructing the refresh operation to the memory array 15 is output. In this example, the power management unit 40 internally counts the input clock signal CLK and outputs a refresh instruction signal / SREF at a predetermined timing based on a predetermined refresh time set in advance. Configured as follows.

  As will be described in detail later, the power supply control circuit 35 controls the supply of the external power supply voltage in response to a control signal (wake-up signal) ALIVE (/ ALIVE) output from the power management unit 40. Control unit 30 instructs array drive control unit 25 to execute a refresh operation in response to refresh instruction signal / SREF output from power supply management unit 40. The I / O unit 20 receives control signals (power-down instruction signals) PD and / PD output from the power management unit 40. As will be described later, the supply of the external power supply voltage to the I / O unit 20 is controlled in response to these control signals PD and / PD.

  The power supply control circuit 35 includes a reference voltage level detection circuit 13 that detects whether the reference voltage for generating the internal voltage is at a predetermined voltage level, and a clock generation circuit 12 that issues a refresh clock PHY that defines the frequency of the refresh operation. Including.

  The reference voltage level detection circuit 13 outputs, as a control signal (power supply ready instruction signal) PWR_RDY, a signal indicating whether or not the reference voltage of the internal voltage generated upon receiving the supply of the external power supply voltage is equal to or higher than a predetermined voltage level. . For example, the reference voltage level detection circuit 13 sets the control signal PWR_RDY to “L” level as an example when the reference voltage level is equal to or lower than a predetermined voltage level. To “H” level. Based on this control signal PWR_RDY, it is possible to determine whether or not an internal voltage of an intended voltage level is output from the power supply control circuit 35.

  The refresh clock PHY defines a cycle in which a refresh operation is executed. In accordance with the refresh clock PHY, row-related circuits related to row selection operate in the memory circuit to refresh the memory cell data.

  Control unit 30 controls array drive control unit 25 and I / O unit 20 to execute a predetermined operation in synchronization with internal clock signal intCLK based on the input of command CMD, address ADD, and the like. The control unit 30 includes a refresh address counter 11. The refresh address counter 11 updates (increments) a refresh address that designates a memory cell that performs a refresh operation in synchronization with the internal clock signal intCLK supplied from the power management unit 40 to the array drive control unit 25. Output.

  The array drive control unit 25 performs a refresh operation on the memory cell at the corresponding address in the memory array based on the refresh address output from the control unit 30. Control unit 30 receives command CMD and address ADD and outputs instructions for data writing and data reading to array drive control unit 25 and I / O unit 20. The array drive control unit 25 and the I / O unit 20 execute a predetermined operation in response to a given instruction.

  In the present embodiment, a description will be given of a standby mode in which data writing and data reading are not mainly executed, but not in a normal mode in which data writing and data reading are executed. Therefore, a detailed description of data writing and data reading operations, which are general techniques, is omitted.

  FIG. 3 schematically shows a configuration of the memory array and a configuration of a peripheral circuit of the memory array according to the first embodiment of the present invention.

  Referring to FIG. 3A, a case where the memory array 15 is divided into a plurality of sub memory array blocks MA0 to MAk (where k is an integer equal to or greater than 0) is shown. Sense amplifier bands SA0 to SAk + 1 for performing a data read operation are provided corresponding to the plurality of sub memory array blocks MA0 to MAk. A sense amplifier band SA sandwiched between adjacent sub memory array blocks MA is shared by adjacent sub memory array blocks MA.

  The memory array 15 further includes a row decoder 4 that executes row selection operations of the plurality of sub memory array blocks MA0 to Mak based on the row addresses RA0 to RAi included in the input address ADD, and is included in the input address ADD. A column decoder 5 is provided for executing a column selection operation of a plurality of sub memory array blocks MA0 to MAk based on column addresses CA0 to CAi.

  Referring to FIG. 3B, a specific configuration of sub memory array block MA and sense amplifier band SA is shown.

  The sub memory array block MA includes a plurality of memory cells MC arranged in a matrix, word lines WL provided corresponding to each memory cell row, and bit line pairs provided corresponding to each memory cell column. BL, / BL. Although not shown, each memory cell MC has a DRAM cell configuration including an access transistor and an information storage capacitor, and has a well-known circuit configuration as an electrical equivalent circuit. This access transistor is formed of an N channel MOS transistor (insulated gate field effect transistor) or a P channel MOS transistor. As the memory cell capacitor, a three-dimensional capacitor such as a MOS capacitor or a stacked capacitor formed by an N-channel MOS transistor or a P-channel MOS transistor can be used.

  Row decoder 4 is provided in a peripheral region of sub memory array blocks MA0 to MAk, and corresponds to a designated row of a sub memory array designated based on row addresses RA0 to RAi included in input address ADD. The arranged word line WL is driven to a selected state. Accordingly, the access transistor is turned on in the memory cell MC of the selected row, and the corresponding bit line BL or / BL and the memory cell capacitor are electrically coupled, so that the data signal for the selected memory cell MC is transmitted. I / O is performed.

Column decoder 5 receives column addresses CA0 to CAi included in input address ADD.
Based on the above, the column selection line CSL corresponding to the addressed column is driven to the selected state.

  In sense amplifier band SA, column selection gate 6, sense amplifier 7, and equalizer 8 are provided corresponding to each column. Column select gate 6 includes a pair of N channel MOS transistors connected between bit lines BL, / BL and data input / output lines IO, / IO. The gates of a pair of N channel MOS transistors of each column selection gate 6 are connected to the column decoder 5 via a column selection line CSL. When column select line CSL is raised to the “H” level of the selection level in column decoder 5 (when driven to the selected state), a pair of N channel MOS transistors of the corresponding column selection gate become conductive, and the corresponding Bit lines BL, / BL and data input / output lines IO, / IO are coupled.

  Sense amplifier 7 is activated by sense amplifier activation signals SE and / SE during data reading or refresh operation. That is, for example, as the sense amplifier activation signals SE and / SE are set to the “H” level and the “L” level, respectively, data appearing as a small potential difference between the corresponding bit lines BL and / BL, that is, the memory cell MC In accordance with the data stored in (1), the potential of one bit line is amplified to the internal power supply voltage VDDT, and the potential of the other bit line is amplified to the ground voltage GND. The amplified bit line signal amplitude is transmitted to the subsequent I / O unit via the data input / output lines IO and / IO, and finally outputted as data Q to the outside.

  The equalizer 8 is activated when the bit line equalize signal BLEQ is activated and becomes, for example, “H” level, and the potentials of the corresponding bit lines BL and / BL are equalized to the level of the internal voltage VBL at the intermediate voltage level, for example. To do.

  Note that control signals for driving the data drive control unit, such as sense amplifier activation signals SE, / SE and bit line equalize signal BLEQ, are given as an example based on the input of command CMD, address ADD, etc. According to a master control signal (not shown) from 30, it is output from the array drive control unit 25.

Here, the refresh operation will be described.
The refresh operation is executed based on the address generated by the refresh address counter 11 of the control unit 30 as described above. For example, when the refresh address counter 11 counts up the row address RA in synchronization with the refresh clock, a refresh operation is sequentially performed on a part of a plurality of memory cells or on a plurality of word lines. Specifically, the word lines WL are sequentially selected one by one, and the memory cell capacitors in each row and the bit line BL or / BL are electrically coupled. Then, as described above, the sense amplifier activation signals SE, / SE are activated, and the sense amplifier is activated in accordance with data appearing as a small potential difference between the bit lines BL, / BL, that is, data stored in the memory cell MC. 7 causes the potential of one bit line to swing to the internal power supply voltage VDDT and the potential of the other bit line to the ground voltage GND. This sense amplifier operation charges or discharges the memory cell capacitor again via the bit line according to the data stored in the memory cell MC, so that the stored data can be refreshed.

  The row decoder 4 and the column decoder 5 described above constitute a part of the array drive control unit 25 for driving the memory array 15 described above.

  FIG. 4 is a schematic block diagram showing a configuration of the I / O unit (data path) 20 according to the first embodiment of the present invention.

  Referring to FIG. 4, I / O unit 20 according to the first embodiment of the present invention includes a data line control unit 51 including a buffer and the like for executing data exchange with the outside, A write driver 52 that transmits input data to the data lines IO and / IO as write data, a read amplifier 53 that amplifies the data read from the data lines IO and / IO and outputs the amplified data to the output unit 54, and a read And an output unit 54 that outputs the data output from the amplifier 54 to a signal wiring or the like used to exchange data with the outside by buffer processing or the like.

  These circuits operate by being supplied with power supply voltages from the local power supply line IVL1 and the local ground line IGL1.

  The power supply of the I / O unit 20 will be described. P channel MOS transistor PT1 (hereinafter also referred to as transistor PT1) is provided between a power supply node supplying external power supply voltage VDD and local power supply line IVL1. An N channel MOS transistor NT1 (hereinafter also referred to as transistor NT1) is provided between a node supplying ground voltage GND and local ground line IGL1. In response to control signals PD and / PD, electrical coupling between local power supply line IVL1 and local ground line IGL1, power supply voltage VDD and ground voltage GND is controlled. Specifically, transistors PT1 and NT1 are turned on / off (on / off) in response to control signals PD and / PD instructing power down, respectively. When control signals PD and / PD are at “L” level and “H” level, transistors PT 1 and NT 1 are turned on, external power supply voltage VDD is supplied to local power supply line IVL 1, and ground voltage GND is supplied to the local ground line. Supplied to IGL1. On the other hand, when control signals PD and / PD are at “H” level and “L” level, transistors PT 1 and NT 1 are turned off, and power supply voltage VDD and ground voltage GND for local power supply line IVL 1 and local ground line IGL 1 are set. Supply is stopped. That is, the power supply of the I / O unit 20 is cut off (power down), and the current flowing inside is cut off.

  Although not shown, the output unit 54 is connected to a signal wiring or the like used for data exchange with the outside, and when a control signal PD (“H” level) instructing power down is input, The wiring and the like and the ground voltage GND are electrically coupled to fix the potential of the signal wiring to the ground voltage GND.

  FIG. 5 schematically shows a configuration of an internal voltage generation circuit that generates an internal voltage of power supply control circuit 35.

  Referring to FIG. 5, power supply control circuit 35 according to the first embodiment of the present invention includes a VPP generation circuit 61 that generates internal voltage VPP that is a boosted voltage, and a VBB generation circuit that generates internal voltage VBB that is a negative voltage. 62, a VCP generation circuit 63 for generating an internal voltage VCP to be supplied to the cell plate electrode of the memory cell capacitor, and a VBL generation circuit 64 for generating an internal voltage VBL at an intermediate voltage level, which is a precharge voltage of the bit line, And a VDDT generating circuit 65 for generating an internal power supply voltage VDDT which is a driving voltage of each circuit.

  These internal voltage generation circuits receive power supply from local power supply line IVL2 and local ground line IGL2 to generate an internal voltage.

  Here, power supply of power supply control circuit 35 will be described. External power supply voltage VDD or external power supply voltage VDDH different from external power supply voltage VDD and P channel MOS transistor PT2 between local power supply line IVL2 and external power supply node (Hereinafter also referred to as transistor PT2). An N channel MOS transistor NT2 (hereinafter also referred to as transistor NT2) is provided between a ground node supplying ground voltage GND and local ground line IGL2.

  In response to control signals (wake-up signals) ALIVE, / ALIVE, the electrical coupling between local power supply line IVL2 and local ground line IGL2 and power supply voltage VDD and ground voltage GND is controlled. Specifically, transistors PT2 and NT2 are turned on / off (on / off) in response to inputs of control signals ALIVE and / ALIVE, respectively. When control signals ALIVE, / ALIVE are at "H" level and "L" level, transistors PT2 and NT2 are turned on, external power supply voltage VDD is supplied to local power supply line IVL2, and ground voltage GND is connected to local ground line. Supplied to IGL2. On the other hand, when control signals ALIVE, / ALIVE are at "L" level and "H" level, transistors PT2 and NT2 are turned off, and external power supply voltage VDD for local power supply line IVL2 and local ground line IGL2 or external power supply Supply of external power supply voltage VDDH and ground voltage GND different from voltage VDD is stopped. That is, the power supply of the power supply control circuit 35 is cut off (power down), and the current flowing inside is cut off.

  FIG. 6 is a timing chart of respective signals showing the operation in the standby mode of the memory circuit according to the first embodiment of the present invention.

  As shown in FIG. 6, each cycle of the external clock signal CLK is represented as cycles T1, T2, T3,. In addition, each cycle of the refresh clock PHY output from the clock signal generation circuit 12 is expressed as a cycle Ta1, Ta2, Ta3,.

  In cycle T2 of external clock signal CLK, a control signal (low consumption standby mode instruction signal) STBY instructing to shift to the low consumption standby mode is asserted. Accordingly, in cycle T3, power supply management unit 40 asserts control signals PD and / PD instructing power-down, and sets them to “H” level and “L” level, respectively. When the control signals PD and / PD are asserted, the transistors PT1 and NT1 are both turned off in the I / O unit 20 as described above with reference to FIG. Accordingly, electrical coupling between power supply voltage VDD and ground voltage GND, and local power supply line IVL1 and local ground line IGL1 is disconnected, and power supply to I / O unit 20 is cut off. During this low power consumption standby mode period, data reading and data writing are not executed. Therefore, it is not necessary to drive the I / O unit 20. By asserting the control signals PD and / PD, the power supply to the I / O unit 20 is cut off during the entire standby mode period (excluding the refresh period), and the current flowing inside is cut off to reduce power consumption. can do.

  When the control signal STBY is asserted, the power supply control circuit 40 switches the internal clock signal intCLK from the external clock signal CLK to the refresh clock PHY input from the power supply control circuit 35 and outputs it to the control unit 30. FIG. 6 shows a case where the clock is switched and the refresh clock PHY is output as the internal clock signal intCLK during the “L” level period of the cycle Ta1 of the refresh clock PHY. In this example, the case where the refresh instruction signal / SREF is asserted in the cycle Ta3 of the refresh clock PHY is shown. Central refresh is performed on the memory array 15 by the assertion of the refresh instruction signal / SREF. In this centralized refresh, data of memory cells in a memory space of a predetermined size (for example, the entire memory space) is refreshed.

Specifically, as described above, in the refresh address counter 11 of the control unit 30, the row address is counted up in synchronization with the internal clock signal intCLK, that is, the refresh clock PHY, and the above-described refresh is performed on the memory cell of the corresponding address. The action is executed. When the refresh operation is repeated for the number of refresh cycles NREF, the refresh operation for all memory spaces is completed.

  Here, when the refresh cycle number NREF is executed by activating the word lines WL one by one with respect to all the word line numbers NWL arranged in the memory array 15, the refresh cycle number NREF is: It becomes equal to the total number of word lines NWL. That is, the refresh cycle number NREF = total word line number NWL. Further, when the memory array 15 is divided into, for example, two independent memory blocks, the refresh cycle is performed by activating the word lines WL by two, whereby the refresh cycle number NERF = NWL / 2. It becomes. An independent memory block refers to a memory block that can execute at least a row selection operation individually.

  Further, when the memory array is divided into four independent memory blocks, the refresh operation is executed by activating the word lines WL four by four, so that the refresh cycle number NERF = NWL / 4. Become.

  After the refresh operation of all the memory spaces is completed and the refresh cycle number NREF has elapsed, the refresh instruction signal / SREF is negated to the cycle Tn of the clock signal CLK. After the negation of the refresh instruction signal / SREF, the control signal ALIVE is negated and set to the “L” level in the cycle Tn + 1 of the next clock signal CLK. As described above, in response to the negation of control signal ALIVE, supply of external power supply voltage VDD or external power supply voltage VDDH and ground voltage GND to power supply control circuit 35 is cut off. Thereby, the generation of the internal voltage of the internal voltage generation circuit of the power supply control circuit 35 is stopped. That is, the operating current of the internal voltage generation circuit is cut off, and the reference voltage level detection circuit 13 negates the control signal PWR_RDY and sets it to the “L” level. Further, the supply of the refresh clock PHY from the clock signal generation circuit 12 is also stopped. That is, after the refresh operation is completed, the power supply to the power supply control circuit 35 is cut off (power down), that is, the operating current flowing inside is cut off to reduce the power consumption.

  The power management unit 40 counts up the clock signal CLK and asserts the control signal ALIVE again in the Tm + 1 cycle after a predetermined period has elapsed. In response to the assertion of the control signal ALIVE, the external power supply voltage VDD or the external power supply voltage VDDH and the ground voltage GND are supplied again to the power supply control circuit 35 to generate an internal voltage. When the reference voltage for generating the internal voltage recovers to a stable voltage level, the reference voltage level detection circuit 13 asserts the control signal PWR_RDY and sets it to the “H” level. Then, the refresh clock PHY is generated again from the clock signal generation circuit 12 and output to the power management unit 40. At this time, since the control signal STBY is asserted, the refresh clock PHY is output to the control unit 30 as the internal clock signal intCLK.

  The refresh instruction signal / SREF is asserted again in the cycle T1 of the clock signal CLK immediately after the control signal PWR_RDY is asserted, and the concentrated refresh is started again. As described above, the refresh operation is performed for the refresh cycle number NREF. When repeated, the refresh operation of the entire memory space is completed.

  That is, in the standby mode of the memory circuit according to the first embodiment of the present invention, after executing the refresh operation, the power supply of power supply control circuit 35 is shut off (powered down), and again before power supply control circuit 35 before the refresh operation. The operation of supplying power and executing the refresh operation is repeated every refresh time.

Here, since it is necessary to repeat the refresh operation within the refresh time tREF determined by the memory cell having the shortest data retention characteristic, it is necessary to satisfy the following relational expression:
Period PA + period PB + period PC + period PD ≦ refresh time tREF,
PA: refresh clock PHY cycle × NREF,
PB: the time from when the refresh operation is completed until the control signal ALIVE is supplied to the power supply control circuit and the power supply is shut off,
PC: Time from when the control signal ALIVE is negated until it is asserted next,
PD: Time from when the control signal ALIVE is asserted until the internal voltage of the power supply control circuit returns to a predetermined voltage level and the next refresh is executed.

  Here, the period PC ends when the external clock signal CLK is counted and the count value reaches the count-up value. That is, a count-up value for counting the external clock signal CLK is set based on the refresh time tREF. The length (count-up value) of this period PC may be fixed according to the refresh time tREF at the maximum guaranteed operating temperature at which the refresh time is the shortest.

  Alternatively, a plurality of stages of refresh time tREF adjusted in accordance with the temperature is set in advance, a temperature sensor is provided outside or inside the chip to detect the operating temperature, and the actual operating temperature It is also possible to adjust the period PC in accordance with the temperature according to the range (this configuration will be specifically described later as an embodiment in detail). Alternatively, when the actual operating temperature is known in advance, the period PC can be set by setting a register value of a register (not shown) that defines the period PC.

  By incorporating these temperature-dependent refresh time mechanisms and adjusting the timing of outputting the refresh instruction signal / SREF in consideration of the period, for example, when the actual operating temperature is lower than the intended temperature Since the refresh time becomes longer, the current consumption in the standby mode can be further reduced by increasing the power supply cutoff period.

  Here, for example, in a memory array capable of refresh time tREF = 10 ms, if the number of refresh cycles NREF = 512 and the cycle of the reflex clock PHY = 15 ns, the period PA = 7.68 μs.

  Therefore, the refresh operation is executed for 7.68 μs during the refresh time tREF = 10 ms, and the power supply control circuit 35 is powered down during the remaining 9.99 ms− (α1 + α2). In this case, since the power supply to the I / O unit 20 is also cut off, the supply of the power supply voltage to the memory circuit is completely cut off.

  The above parameters α1 and α2 correspond to the periods PB and PD. As described above, the period PB is a period from the completion of the refresh operation to the negation of the control signal ALIVE before the power supply control circuit 35 enters the power down mode. The period PD is a period from when the control signal ALIVE is asserted to when the power supply control circuit 35 returns to perform refresh. These periods can be realized in ns order.

  Therefore, during the refresh time tREF, the period during which the memory circuit is operating for the refresh operation can be approximated as 9.99 ms− (α1 + α2) ≈9.99 ms. That is, each block of the memory array and its peripheral circuits performs a refresh operation for a period of 0.08% of the refresh time tREF, but the power supply is cut off during the remaining 99.92%, that is, a current path Is cut off. The ratio of the period during which the current path is interrupted depends on the refresh cycle number NREF, and the ratio increases as the refresh cycle number decreases.

  Further, as described above, in response to the assertion of the control signal STBY, the control signals PD and / PD are asserted and output to the I / O unit 20. Accordingly, the power supply to the circuit blocks constituting the I / O unit 20 is interrupted and all current paths are also interrupted, so that the current consumption in the standby mode can be significantly reduced.

  As described above, in the configuration according to the first embodiment of the present invention, the current path can be cut off in almost all the data holding periods in the standby mode. Therefore, power consumption can be reduced, and a data holding standby current equivalent to a so-called low power consumption SRAM can be realized.

(Embodiment 2)
In the above-described first embodiment, the case of performing refresh for the entire space of the memory array has been described. In the second embodiment of the present invention, the case of specifying a memory space to be refreshed in the standby mode will be described.

  FIG. 7 schematically shows structures of the memory array and its peripheral circuits according to the second embodiment of the present invention.

  Referring to FIG. 7, the memory array and its peripheral circuits according to the second embodiment of the present invention replace power supply management unit 40 with power management unit 41 and control unit 30 as compared with the configuration described in FIG. The difference is that the control unit 31 is replaced. Since other points are similar, detailed description thereof will not be repeated.

  The power management unit 41 receives and decodes the control data DR [1: 0], generates a control signal / PDARR [3: 0], and outputs it to the array drive control unit 25. The power management unit 41 outputs to the control unit 31 a refresh instruction signal / SREF [3: 0] instructing execution of refresh corresponding to each sub-array block described later. Note that the notation of signal [p: 0] indicates 0 to p signals. Further, in the case of indicating data or the like, the notation of data [p: 0] indicates p + 1 bit data from the 0th to the pth.

  FIG. 8 is a diagram for explaining the space of the memory array that is refreshed in response to input control data DR [1: 0].

  Here, as described in FIG. 3, it is assumed that the memory array is divided into a plurality of sub memory array blocks. As an example, the sub memory is divided into four groups and includes a plurality of sub memory array blocks. Array block groups SBK0 to SBK3 are shown.

  As described above, the memory array according to the second embodiment of the present invention is divided into four sub memory array block groups as an example. The array drive control circuit for driving the memory array is also divided and controlled by the array drive control unit so that it can be driven for each sub memory array block group. In this example, the sub memory array block group SBK and the array drive control unit that drives the sub memory array block group SBK are represented as a sub array block group SBKG. Here, since it is divided into four sub memory array block groups SBK, four sub array block groups SBKG0 to SBKG3 are shown corresponding to each.

As an example, when “11” is input from the upper bit side of the control data DR [1: 0], refresh is performed on all memory array sections of the memory array 15. Further, when “10” is input from the upper bit side of the control data DR [1: 0], specifically, the sub-array block group SBKG0, It is assumed that refresh is performed on SBKG1. When “01” is input from the upper bit side of the control data DR [1: 0], for a quarter of the entire memory array space, specifically, for the sub-array block group SBKG0. And refresh is executed.

  FIG. 9 is a diagram illustrating power supply to the subarray block group according to the second embodiment of the present invention.

  Referring to FIG. 9, as described above, internal power supply voltage VDDT and ground voltage GND are supplied as drive voltages to four subarray block groups SBKG0 to SBKG3. Local ground lines SGL0 to SGL3 are provided independently of each other corresponding to subarray block groups SBKG0 to SBKG3. Transistors NT2-NT5 are provided between local ground lines SGL0-SGL3 and ground voltage GND, respectively, and control signals / PDARR0- / PDARR3 are applied to the gates of transistors NT2-NT5, respectively. Although the internal power supply voltage VDDT will be mainly described here, the present invention can be similarly applied to other internal voltages VPP, VBB, VCP, and VBL.

  For example, when control signal / PDARRi is set to “H” level, ground voltage GND is supplied to corresponding local ground line SGLi (i = 0-3) and set to “L” level. In this case, the supply of the ground voltage GND to the local ground line SGLi is cut off. Here, a configuration in which the connection between the local ground line SGLi and the ground voltage GND is controlled by a transistor will be described. However, the present invention is not limited to this, but the local power line and the internal power supply that receive the supply of the internal power supply voltage VDDT are not limited thereto. Of course, a transistor may be provided between the voltage VDDT and the connection between them may be controlled. It is also possible to use a configuration in which switching transistors for power supply control are provided for both the high-side and low-side local power supply lines.

  For example, when “01” is input from the upper bit side of the control data DR [1: 0] described above in the standby mode, the sub memory array block group SBK0 of the sub array block group SBKG0 is selected, and the sub memory The refresh operation is executed only for the array block group SBK0, and the refresh operation is not executed for the other sub memory array block groups SBK1 to SBK3.

  Specifically, when “01” is input from the upper bit side of the control data DR [1: 0], the control signal / PDARR0 is set to the “H” level, and the other control signals / PDARR1 to // PDARR3 is set to the “L” level. As a result, for subarray block groups SBKG1 to SBKG3, the corresponding local ground line SGL and ground voltage GND are electrically disconnected, and the standby current that flows during standby is cut off for subarray block groups SBKG1 to SBKG3. be able to.

  Based on the input of “01” from the upper bit side of the control data DR [1: 0], the power management unit 41 performs a refresh operation that instructs a refresh operation output corresponding to each of the sub memory array block groups SBK0 to SBK3. For the instruction signals / SREF0 to / SREF3, only the refresh instruction signal / SREF0 is asserted and output, and the other refresh instruction signals / SREF1 to / SREF3 are set to the negated state.

Thus, control unit 31 controls the array drive control unit corresponding to sub memory array block group SBK0 to instruct execution of the refresh operation described above, and performs array drive corresponding to the remaining sub memory array block groups SBK1 to SBK3. The control unit does not perform a refresh operation. That is, the refresh operation is performed on the sub memory array block group SBK0 in the ¼ area of the entire memory space. The remaining area is in a state where power supply is cut off in the standby mode.

  According to the same method, for example, when “10” is input from the upper bit side of the control data DR [1: 0], the control signals / PDARR0 and / PDARR1 are set to the “H” level, and the remaining control signals / PDARR2 and / PDARR3 are set to "L" level. Further, the refresh instruction signals / SREF0 and / SREF1 are asserted, and the other refresh instruction signals / SREF2 and / SREF3 are negated. As a result, the refresh operation can be performed on the sub memory array block groups SBK0 and SBK1 which are ½ of the entire memory space. The remaining area is in a state where power supply is cut off in the standby mode.

  Further, according to the same method, for example, when “11” is input from the upper bit side of control data DR [1: 0], control signals / PDARR0 to / PDARR3 are set to “H” level and refresh instruction Control to assert all signals / SREF0 to / SREF3. As a result, the refresh operation can be performed on the entire memory space of the memory array.

  With the configuration according to the second embodiment of the present invention, the partial refresh can be executed only for a part of the memory array, and the power supply to the subarray block groups other than the subarray block group to be partially refreshed during the standby period is interrupted to By blocking the path, power consumption in the memory array can be further reduced.

  In this example, the method of inputting the 2-bit control data DR [1: 0] and dividing the entire memory space into four has been described. However, the memory space is divided into other divisions, for example, the control data DR is divided into 2 divisions or 3 divisions into 8 divisions or more, and refresh is performed on a part of the memory array. Of course it is also possible to do.

  In this example, for example, when “01” is input from the upper bit side of the control data DR [1: 0], it is assumed that refresh is performed on a quarter of the entire memory array space. However, the relationship between the value of the control data DR [1: 0] and the refreshed memory space can be set to an arbitrary condition without being limited to this condition.

  According to the configuration of the second embodiment of the present invention, when the memory space that needs to hold data in the standby mode is a part rather than the entire space, a partial refresh is executed only for a part of the memory space. In the other memory space, the power supply is cut off and the current path is always cut off. Thereby, lower power consumption can be realized than in the first embodiment.

In the above description, a method is described in which the control data DR [1: 0] is decoded by the power management unit 41 and the refresh operation is selectively performed on the subarray block group divided into four in accordance with the decoding result. is doing. However, the following configuration is also possible: the control data DR [1: 0] is input to the refresh address counter 11 of the control unit 30, and the sub memory array block specified based on the control data DR [1: 0] Only the internal address corresponding to SBK is generated from the refresh address counter 11. A 2-bit block address designating a sub memory array block group included in the refresh address is selectively set according to the value of the control data DR [1: 0]. For example, when the control data DR “1: 0” is “11”, “10” and “01”, the 2-bit refresh block address is set according to the count value of the refresh counter, the upper 1 bit is fixed, and 2 Fix both bits together. With this configuration, it is possible to designate a block address corresponding to the designated memory space in the refresh address generated from the refresh counter and supplied to the array driver.

(Embodiment 3)
In the third embodiment of the present invention, a description will be given of a case where the externally applied clock signal CLK is switched to a low-frequency clock signal before entering the standby mode.

  FIG. 10 schematically shows structures of the memory core (DRAM core) and its peripheral circuits according to the third embodiment of the present invention.

  Referring to FIG. 10, the configuration according to the third embodiment of the present invention replaces power management unit 40 with power management unit 40 # as compared with the configuration according to the first embodiment of the present invention described in FIG. In addition, power supply control circuit 35 is replaced with power supply control circuit 35 #.

  The power supply control circuit 35 # does not include the refresh clock generation circuit 12 that generates the refresh clock PHY, and the power supply management unit 40 # includes the refresh clock generation circuit 12 # that generates the refresh clock PHY. Different.

  In this embodiment, before entering the standby mode, in the normal mode, when a clock signal CLK having a frequency of 66 MHz, for example, is input, the clock signal CLK is switched to a clock signal CLK having a low frequency of 32 kHz, for example. Input to unit 40 #.

  In response to assertion of control signal STBY, refresh clock generation circuit 12 # of power management unit 40 # generates refresh clock PHY at an appropriate period, for example, a period of 15 ns, while clock signal CLK is at "H" level. Then, the power supply management unit 40 # outputs the internal clock signal intCLK to the control unit 30.

  FIG. 11 is a timing chart of signals showing operation in the standby mode of the memory circuit according to the third embodiment of the present invention. The notation of the cycle of the clock signal is the same as that shown in FIG.

  Referring to FIG. 11, in response to the rise of clock signal CLK in cycle T1, control signal STBY is asserted and control signals PD and / PD are negated. Accordingly, the power supply of the I / O unit 20 is cut off as described above. In addition, refresh mode instruction signal / SREF is asserted.

  When control signal STBY is asserted and refresh mode instruction signal / SREF is asserted, refresh clock PHY is generated during the H level period of external clock signal CLK in refresh clock generation circuit 12 #, and internal clock signal intCLK Is output to the control unit 30. When refresh mode instruction signal / SREF is asserted, control unit 30 executes centralized refresh on the memory array in accordance with the same method as described above in synchronization with control signal internal clock signal intCLK.

  Refresh instruction signal / SREF is negated after NREF cycles of internal clock signal intCLK after the refresh of all memory spaces is completed.

  Refresh clock generation circuit 12 # stops generating refresh clock PHY in response to refresh instruction signal / SREF being negated.

  In the same manner as described above, the control signal ALIVE is negated in response to the negation of the refresh instruction signal / SREF, the power supply of the power control circuit 35 # is cut off (power down), and the control signal (power ready signal) ) PWR_RDY is negated.

  Power supply management unit 40 # counts up clock signal CLK and asserts control signal ALIVE at a predetermined timing after the elapse of a predetermined period as described above, that is, before the start time of the next concentrated refresh according to the refresh time. . Thereby, power supply to power supply control circuit 35 # is started again. When the voltage level of the reference voltage for generating the internal voltage returns to the predetermined voltage level, the reference voltage level detection circuit 13 asserts the control signal PWR_RDY and sets it to the “H” level. In response, refresh instruction signal / SREF is asserted, and refresh clock PHY is generated again from clock signal generation circuit 12, and concentrated refresh is started again according to this refresh clock.

  Therefore, in the configuration according to the second embodiment of the present invention, as in the case described in the first embodiment, the current path can be cut off in almost all the data holding periods in the standby mode. Therefore, power consumption can be reduced, and a data holding standby current equivalent to a so-called low consumption SRAM can be realized.

  In addition, since low frequency clock signal CLK is input to power management unit 40 # in the standby mode, it is possible to reduce power consumption of an internal circuit operating in synchronization with clock signal CLK.

  In this embodiment, since refresh clock PHY is generated as refresh instruction signal / SREF is asserted, the oscillation circuit that generates the refresh clock does not oscillate when refresh is not executed, and the circuit Power consumption accompanying operation can be reduced.

  In this example, the case where refresh is executed for the entire memory array space is described. However, the present invention is not limited to this, and as described in the above-described second embodiment, it is naturally possible to adopt a configuration in which refresh is executed only for a space divided into 1/2 of the memory array space or 1/4 of the memory array space. Is possible.

  In this example, as in the first embodiment, the period PC set by counting up the external clock signal CLK is fixed according to the refresh time tREF at the maximum guaranteed operating temperature at which the refresh time is the shortest. May be. In addition, a temperature sensor is provided outside or inside the chip, and a plurality of stages of refresh time tREF adjusted in accordance with the temperature are prepared in advance, and the period PC corresponds to the temperature according to the actual operating temperature range. It is also possible to adjust. Alternatively, when the actual operating temperature is known in advance, the period PC can be set by setting a register value of a register (not shown) that defines the period PC.

  By incorporating these mechanisms, the timing at which the refresh instruction signal / SREF is asserted is adjusted in consideration of the temperature-dependent refresh time, for example, when the actual operating temperature is lower than the intended temperature. Since the refresh time becomes longer, the power supply cutoff period can be increased, and the current consumption in the standby mode can be further reduced.

(Embodiment 4)
Depending on the system LSI, during normal operation, a large amount of memory space may be required to accommodate multiple memory cores. There are cases where it is not necessary for data retention.

  In the fourth embodiment, as an example, a case where data is held for one memory array of one memory core in the standby mode will be described. It is assumed that a plurality of memory arrays are mounted on one memory core.

  FIG. 12 schematically shows structures of the memory core and its peripheral circuits according to the fourth embodiment of the present invention.

  Referring to FIG. 12, there is shown a case where a plurality of sets (plural) of memory arrays 15, array drive control unit 25, control unit 30, I / O unit 20 and power supply control circuit 35 are provided. The memory array 15, the array drive control unit 25, the control unit 30, the I / O unit 20, and the power supply control circuit 35 may constitute one memory core (DRAM core).

  Power supply management unit 40 # a is provided in common for a plurality of sets of memory cores and the like.

  Here, a case will be described in which the refresh operation is executed only for one memory array 15S of the plurality of sets of memory arrays 15 and the like in the standby mode.

  In response to the assertion of control signal STBY, power management unit 40 # a asserts control signals PD and / PD as described above to supply power to all I / O units 20 corresponding to a plurality of sets of memory arrays. Cut off. Further, power supply management unit 40 # a outputs refresh instruction signal / SREFs for power supply control circuit 35, control unit 30 and the like corresponding to memory array 15S in the same manner as described in the first embodiment. After executing the refresh operation, the control signal ALIVEs is negated to cut off the power supply of the power control circuit 35. Since the operation and the like at the time of refresh are the same as those described in the first embodiment, detailed description thereof will not be repeated.

  On the other hand, the power management unit 40 # a negates the control signal ALIVE in response to the assertion of the control signal STBY for the power control circuit 35 corresponding to the memory array 15 other than the memory array 15S. The power supply to 35 is cut off. Further, the refresh instruction signal / SREF is not asserted for the corresponding control unit 30. Thereby, in the standby mode, the circuits corresponding to the memory array 15 other than the memory array 15S can always maintain the power-down state, and the power consumption can be reduced.

  With this configuration, it is possible to reduce the power consumption of the entire system LSI by driving only at least a part of the plurality of memory arrays in the standby mode and powering down the remaining memory arrays.

  Although the case where only one memory core is driven has been described here, the present invention is not limited to this, and a configuration in which a larger number of memory cores are driven is also possible.

  Further, as described in the second embodiment, the memory array 15S is not limited to the case where the entire memory array space is refreshed, and is divided into 1/2 of the memory array space or 1/4 of the memory array space. Of course, it is possible to adopt a configuration in which refresh is executed only for a space.

(Embodiment 5)
In the second embodiment, the method of reducing the power consumption by executing the partial refresh for executing the refresh for a part of the sub-memory array blocks in the memory array in the standby mode has been described. In the fifth embodiment of the present invention, a method for further reducing power consumption when performing partial refresh will be described.

  The memory array generally has a redundant line (redundant row or redundant column) composed of redundant memory cells for relieving a memory cell defect. The memory cell or the line of the memory cell that has become defective in the wafer test after the completion of the wafer process is replaced with a redundant line and repaired. In general, a defect relief method is employed in which defective memory cells are relieved by such redundant replacement to improve yield. Specifically, a repair code indicating the address of the memory cell to be replaced is programmed in the fuse or the like. In actual use, the input address is compared with the repair code. When an address (defective address) of a defective memory cell is input, it matches the repair code. In this case, defective memory cells can be relieved equivalently by selecting and replacing redundant lines.

  FIG. 13 is a diagram for explaining an operation for repairing a defective line included in a memory array with a redundant line.

  Referring to FIG. 13, the memory array is divided into a plurality of sub memory blocks MA0 to MAk + 1.

  Sense amplifier bands SA0 to SAk + 2 for executing a data read operation are provided on both sides of each of the plurality of sub memory blocks MA0 to MAk + 1. A sense amplifier band SA sandwiched between adjacent sub memory array blocks MA is shared by adjacent sub memory array blocks MA. Now, the sub memory block MAk + 1 has redundant memory cells and includes a plurality of redundant lines (redundant rows).

  In this configuration, for example, when the presence of a defective memory cell is found in the sub memory array block MAk-2, the defective line including the defective memory cell is replaced with a redundant line arranged in the sub memory array block MAk + 1. . Thereby, it is possible to relieve a defective line.

  Here, when a refresh test is performed in the wafer test, a redundant line (redundant row or redundant column) is sequentially formed with a line (row or column) having a memory cell having the shortest data retention characteristic in the chip as a defective line. Replace with Thereby, all the memory cells are set to satisfy a predetermined refresh time tREF. In this case, it is necessary to ensure that the memory cells of the redundant line satisfy a predetermined refresh time.

  FIG. 14 is a diagram illustrating the relationship between the refresh time tREF in the refresh test and the number of defective bits (FBC (Fail bit count)) that do not satisfy the refresh time tREF. In FIG. 14, the horizontal axis indicates the refresh time, and the vertical axis indicates the FBC.

  Referring to FIG. 14, in order to satisfy refresh time tREF = 10 ms, it is necessary to replace ml redundant lines for refresh relief.

In the configuration according to the fourth embodiment, as described in the second embodiment, partial refresh is performed in the standby mode, and refresh is performed on a part of the memory space.

  For the partial refresh space in which the refresh is executed, which is a part of the memory space, the refresh test standard at the time of the wafer test is set strictly, and the redundant line is replaced and relieved.

  For example, as a refresh test standard (redundancy relief test standard) at the time of a wafer test, a wafer test with a refresh time tREF = 10 ms is executed for all memory spaces, and a redundant line is set so as to satisfy the refresh time tREF = 10 ms. Replace and rescue. Further, by requesting a refresh time tREF several times, for example, 20 ms, for the partial refresh space, the refresh test standard is stricter and the defective line is replaced with a redundant line for repair.

  With the configuration according to the fifth embodiment, it is possible to set the refresh time tREF of the partial refresh space for holding data in the standby mode to several times that of the entire memory array space. Therefore, the power consumption in the standby mode can be further reduced by adjusting (longening) the period PC or the like.

  In the configuration according to the fifth embodiment, only a part of the memory space is a system in which the refresh test is executed with a strict test standard for the refresh time tREF. Accordingly, the number of redundant lines required can be reduced.

  Note that the configuration according to the fifth embodiment of the present invention can be similarly applied to a configuration that performs partial refresh according to the fourth embodiment.

(Embodiment 6)
FIG. 15 schematically shows a whole structure of the memory circuit and its peripheral circuits according to the sixth embodiment of the present invention. For the memory circuit shown in FIG. 15, the peripheral circuit is activated in accordance with an indicator signal Inid given from a controller such as an external logic, and generates an m-bit refresh time control code RTSEL according to the ambient temperature (operating temperature). A refresh time control circuit 150 is provided. The power management unit 140 and the refresh time control circuit 150 are circuits around the memory core formed on the same semiconductor chip as the memory circuit (DRAM core), and are part of a logic block other than the DRAM core in the system LSI. Refresh time control circuit 150 receives external power supply voltage VDD as a high-side power supply voltage.

  The DRAM core includes a memory array 15, an array drive control unit 25, a control unit 30, an I / O unit 20, and a power supply control circuit 35. FIG. 15 shows that the power management unit 140 and the refresh time control circuit 150 are provided for one DRAM core. However, the power management unit 140 and the refresh time control circuit 150 are provided for a plurality of DRAM cores. May be provided in common.

  The power management unit 140 adjusts the assertion interval of the wakeup signal ALIVE according to the refresh time control code RTSEL from the refresh time control circuit 150, and adjusts the refresh time accordingly.

In the power supply control circuit 35, when the wakeup signal ALIVE is asserted, the refresh clock generation circuit 12 generates the refresh clock PHY. The refresh clock PHY defines a refresh cycle in which memory cell data is refreshed in the memory array 15. One refresh is executed in the memory array 15 in one cycle of the refresh clock PHY.

  The other configuration of the memory circuit (DRAM core) shown in FIG. 15 is the same as the configuration of the memory circuit shown in FIG. 2, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 16 is a timing chart showing the operation of the circuit shown in FIG. The timing diagram shown in FIG. 16 is substantially the same as the timing diagram shown in FIG.

  In the cycle of external clock signal CLK (hereinafter simply referred to as clock cycle) T1, refresh clock PHY is generated in accordance with the active state of wakeup signal ALIVE. As an example, the refresh clock PHY monitors the access to the DRAM core in the refresh clock generation circuit 12, and is generated at a predetermined time interval according to the output signal of the timer when the access is not performed for a predetermined time or longer. (Self-refresh mode without power down). Alternatively, the refresh clock generation circuit 12 may be activated by a control signal from a logic (not shown) when shifting to the low power consumption standby mode.

  When the low power consumption standby mode instruction signal (power down mode instruction signal) STBY is asserted, the power management unit 140 issues the refresh clock PHY provided from the refresh clock generation circuit 12 of the power control circuit 35 as the internal clock signal intCLK. To do. FIG. 16 also shows a state where the refresh clock PHY is output as the internal clock signal intCLK during the refresh clock cycle Ta1 while the refresh clock PHY is at the “L” level.

  In clock cycle T2, internal clock signal intCLK is switched, and the low power consumption standby mode is entered.

  Next, in cycle T3 of external clock signal CLK, power down instruction signals PD and / PD are set to “H” level and “L” level, respectively, and as shown in FIG. The array drive control unit 25 and the control unit 30 stop supplying power to circuit portions other than the circuits related to refresh.

  Next, in the DRAM core, refresh is executed according to the refresh address from the internal refresh address counter 11. Also in the present embodiment, the refresh is performed by concentrated refresh. This refresh is executed in each cycle of the internal clock intCLK. When the refresh is executed NREF times, the refresh of the entire memory space is completed.

  When refresh of all the memory spaces is completed, refresh instruction signal / SREF is deactivated in clock cycle Tn, and wakeup instruction signal ALIVE becomes L level in the next clock cycle Tn + 1 (hereinafter referred to as “H” level). And “L” level is simply denoted as H level and L level).

  When the wake-up signal ALIVE is negated, the power supply control circuit 35 stops the power supply, stops the generation of the internal voltages VPP..., And the power supply ready signal PWR_RDY is Deactivated. Also, the generation of the refresh clock PHY is stopped.

Next, the wake-up signal ALIVE is asserted at a predetermined interval while the low power consumption standby mode instruction signal STBY is at the H level. The negation period of the wake-up signal ALIVE can be adjusted according to the temperature, as will be described later in detail.

  As the wakeup signal ALIVE shifts from negation to assertion, the internal clock generation circuit in the power management unit 140 generates the internal clock signal intCLK according to the external clock signal CLK. The refresh clock generation circuit 12 is not supplied with a stable power supply voltage, and no refresh clock is generated. In FIG. 16, the external clock signal CLK and the internal clock signal intCLK are shown as being asynchronous, but the internal clock signal intCLK is synchronized with the external clock signal CLK from this clock cycle Tm + 1 to the clock cycle Tl. Generated.

  Next, when the internal power supply voltages VDDT, VPP, VBB, VCP and VBL for the memory core (DRAM core) return to a predetermined voltage level in the clock cycle Tl, the power supply ready signal PWR_RDY is asserted. In response, refresh instruction signal / SREF is asserted again, and refresh clock PHY is generated from refresh clock generation circuit 12, and this clock is switched to internal clock by clock switching circuit in power management unit 140. Output as signal intCLK.

  Thereafter, a refresh cycle is defined from the refresh clock cycle Tal according to the internal clock signal intCLK, and refresh is executed in the DRAM core. This operation is repeated in the same manner as described in the first embodiment while the low power consumption standby mode instruction signal STBY is asserted.

  In the sixth embodiment, the negation period PC of the wake-up signal ALIVE is adjusted according to the operating temperature. A configuration in which the power management unit 140 adjusts the negation period of the wake-up instruction signal ALIVE will be described in detail later.

  In FIG. 16, when the refresh clock PHY is generated in the cycle Ta1, the refresh is executed using the internal clock signal intCLK. However, refresh instruction signal / SREF may be asserted after refresh clock PHY is stably issued. That is, refresh may be executed from cycle Tal + 2.

  The period PD from the clock cycle Tm to the refresh cycle Tal is a period required from when the wake-up signal ALIVE is asserted until the power supply control circuit 35 returns to the normal state and the next refresh is executed. (Nanosecond) order. Therefore, the refresh instruction signal / SERF may be asserted at a later timing after the refresh clock PHY is stably generated. In order to show this state, FIG. 16 shows that there are several cycles between cycle Tm + 1 and cycle Tl of external clock signal CLK. This indicates that the number of clock cycles (with respect to the external clock signal) from when wakeup signal ALIVE is activated to when refresh is executed can be adjusted according to the internal configuration.

  In FIG. 16, the period PC during which the external clock signal CLK is counted, that is, the period in which the wake-up signal ALIVE is negated is determined by the refresh time tREF. Therefore, as the refresh time tREF becomes longer, the period PC can be lengthened accordingly. Therefore, the ratio of the period during which the current path is cut off increases, and in addition to the reduction of the DC current component and the reduction of the AC current component, the current consumption in the standby mode for holding data can be further reduced.

FIG. 17 schematically shows configurations of refresh clock generation circuit 12 and power management unit 140 shown in FIG. In FIG. 17, the refresh clock generation circuit 12 includes a timer 155 and an oscillation circuit 157 that generates a refresh clock PHY. The timer 155 is activated when the memory circuit is not accessed for a predetermined time or longer, and activates a mode (self-refresh mode) in which refresh is automatically performed internally. In this case, the internal power supply is not shut off (the power down mode is not set).

  When the power supply ready signal PWR_RDY is asserted and the output signal of the timer 155 indicates a time-up signal when the power-up ready signal PWR_RDY is asserted, the oscillation circuit 157 is activated and performs an oscillating operation at a predetermined cycle to generate the refresh clock PHY. Is generated. The oscillation circuit 157 may perform an oscillation operation in accordance with a control signal that is activated at a timing earlier than the instruction signal STBY in the low power consumption standby mode.

  When the logic circuit does not perform processing for a predetermined time or more, is in a wait state, and access to the DRAM core is not performed for a long time, the controller in the external logic circuit causes the low-consumption standby mode instruction signal STBY to Is asserted. The refresh mode of both the low-consumption standby mode instruction signal STBY from the logic circuit and the self-refresh mode in which refresh is performed by detecting the non-access period length within the DRAM core is realized.

  The oscillation circuit 157 detects the refresh mode in the DRAM core and performs refreshing by selecting word lines sequentially at predetermined intervals and performing low-power standby mode from an external logic circuit. When performing centralized refresh for refreshing the entire memory space at the time of mode instruction, the oscillation frequency is changed according to the refresh mode. At the time of distributed refresh, the oscillation frequency is lowered, and at the time of concentrated refresh, the oscillation frequency is raised. This control can be realized by switching the oscillation frequency by asserting / negating the low power consumption standby mode instruction signal STBY.

  When the wake-up signal ALIVE is negated, the oscillation circuit 157 stops its oscillation operation. Accordingly, the refresh clock PHY is not issued during the negation period of the wake-up instruction signal ALIVE. Further, the oscillation circuit 157 is enabled when the power supply ready signal PWR_RDY is asserted so that an unstable operation is not performed when the power is turned on.

  The power management unit 140 sets a refresh interval (period PC), and a first counter 162 that counts the external clock signal CLK according to the count-up value from the register circuit 160 when the wake-up instruction signal ALIVE is inactive. And a wake-up control circuit 164 that generates a wake-up signal ALIVE according to the count-up instruction signal CUP1 of the first counter 162, the refresh mode instruction signal / SREF, and the low power consumption standby mode instruction signal STBY.

  Register circuit 160 includes a plurality of registers Reg1-Regm and a selector SLK that selects one stored value of registers Reg1-Regm in accordance with refresh time control code RTSEL from refresh time control circuit 150 shown in FIG. In the registers Reg1-Regm, a concentrated refresh interval or refresh time is set according to the operating temperature (or ambient temperature; chip temperature). The register storage value selected by the selector SLK is given to the first counter 162 as a count up value. By using the register, it is possible to easily store the count values corresponding to a plurality of refresh times and select the corresponding refresh times according to the temperature detection information from the refresh time control circuit.

  The first counter 162 counts the external clock signal CLK triggered by the transition of the wakeup signal ALIVE to the negated state. When the count value reaches the count value given from register circuit 160, count-up instruction signal CUP1 is generated.

  When the low power consumption standby mode instruction signal STBY is asserted, the wakeup control circuit 164 negates the wakeup signal ALIVE in the next clock cycle in response to the negation of the refresh mode instruction signal / SREF. The wakeup control circuit 164 also asserts the wakeup signal ALIVE when the countup instruction signal CUP1 from the first counter 162 is asserted.

  Therefore, the assertion period of wakeup instruction signal ALIVE is determined by the assertion period of refresh mode instruction signal / SREF, and the negation period of wakeup signal ALIVE is determined by the count value of first counter 162. The length of the period PC shown in FIG. 16 is set by the count-up value of the first counter 162, that is, the count value from the register circuit 160.

  As described in the first embodiment, the period PA shown in FIG. 16 is a constant determined by the product of the period of the refresh clock PHY and the number of refresh cycles NREF. The period PB is a period from when the refresh operation is completed to when the wake-up instruction signal ALIVE is negated until the power source is cut off by the power source control circuit 35, and can be predicted in advance according to circuit characteristics. The period PD is a period from when the wakeup signal ALIVE is asserted to when the power supply is restored in the power supply control circuit 35 until the next refresh is executed. This period PD can also be predicted in advance according to circuit characteristics. The sum of the periods PA, PB, PC and PD is a period equal to or shorter than the refresh time tREF. Therefore, by increasing the period PC when the refresh time tREF can be increased, the current path cutoff period is lengthened, and the current consumption during standby can be reduced. The temperature dependence of the refresh time tREF will be described later.

  The power supply control unit 140 further includes a second counter 166 that generates a refresh instruction signal / SREF, a power-down control circuit 168 that generates power-down instruction signals PD and / PD, and an internal clock generation that generates an internal clock signal intCLK. Circuit 169.

  The second counter 166 is activated in response to the assertion of the low power consumption standby mode instruction signal STBY or the power supply ready signal PWR_RDY, and counts the refresh clock PHY for the number of refresh cycles NREF. During the counting period, the second counter 166 asserts the refresh instruction signal / SREF, and negates the refresh instruction signal / REF when counting up.

  As shown in the timing chart of FIG. 16, the second counter 166 asserts the refresh instruction signal / SREF after one clock cycle elapses after the assertion of the low power standby mode instruction signal STBY, and refreshes according to the assertion of the power supply ready signal PWR_RDY. The instruction signal / SREF is asserted. This timing adjustment is performed by providing a circuit that delays the signal STBY by one clock cycle. The refresh instruction signal / SREF is asserted by asserting the output signal of the delay circuit or asserting the power supply ready signal PWR_RDY.

The assertion period of the refresh instruction signal / SREF is determined by the count-up value of the second counter 166. The number of refresh cycles NREF differs depending on the number of word lines selected during one refresh operation. In the second counter 166, when the number of refresh cycles NREF to be counted can be changed, the following configuration can be used. A plurality of registers are provided for the second counter 166. Count values corresponding to the number of refresh cycles are set in these registers. Depending on the refresh cycle used, the contents of the register are selected and given to the second counter 166 as a count-up value. Instead, the refresh cycle number information is stored in the mode register at the time of initialization, and the stored value of this mode register is given to the second counter 166.

  Further, the second counter 166 generates a refresh instruction signal / SREF in accordance with the refresh clock PHY (outputs the refresh clock PHY as the refresh instruction signal / SREF) when the low power standby instruction signal STBY is negated. With this configuration, refresh can be performed by detecting the refresh mode in accordance with the output signal of timer 155 in the DRAM core.

  When the low power consumption standby mode instruction signal STBY is asserted, the power down control circuit 168 asserts the power down instruction signals PD and / PD at a predetermined timing (after one clock cycle in FIG. 16). The asserted state of power down instruction signals PD and / PD is maintained while the low power consumption standby mode is set. In accordance with the assertion of power-down instruction signals PD and / PD, the power supply transistor in I / O unit 20 is set to the cutoff state. Stopping the power supply in the power management unit 140 is controlled by a wake-up signal ALIVE.

  Internal clock generation circuit 169 selects one of refresh clock PHY and external clock signal CLK according to low power consumption refresh mode instruction signal STBY, power supply ready signal PWR_RDY, and wake-up signal ALIVE to generate internal clock signal intCLK. That is, when the low power consumption standby mode instruction signal STBY is driven from the negated state to the asserted state, the internal clock generating circuit 169 changes the refresh clock PHY to the external clock signal CLK in response to the transition to the asserted state. Select instead. This state is maintained until the wake-up signal ALIVE is negated. When the wakeup signal ALIVE is negated, the internal clock generation circuit 169 is set to a state for selecting the external clock signal CLK. When wakeup signal ALIVE is negated, internal clock generation circuit 169 has its output signal fixed at the L level. Instead, the internal clock generation circuit 169 may be configured to stop the internal clock generation operation by stopping the power supply when the wakeup signal ALIVE is negated.

  The internal clock generation circuit 169 selects the refresh clock PHY instead of the external clock signal CLK when the power supply ready signal PWR_RDY is asserted when the low power consumption standby mode instruction signal STBY is asserted. Output as intCLK. The internal clock generation circuit 169 is set to select the external clock signal CLK when the wakeup signal ALIVE is negated. This switching configuration can be realized by the following configuration, for example. That is, a flip-flop that is set in accordance with the assertion of the low power consumption standby mode instruction signal STBY or the power supply ready signal PWR_RDY when the signal STBY is asserted and reset in accordance with the negation of the wake-up signal ALIVE is used, and the output signal is used as the internal clock selection signal Use as

The internal clock generation circuit 169 may be configured to always select the refresh clock PHY instead of the external clock signal CLK when the low power consumption standby mode instruction signal STBY is asserted. The refresh clock PHY from the oscillation circuit 157 is not generated when the wake-up instruction signal ALIVE is negated, and the refresh clock PHY is not generated while the power supply ready signal PWR_RDY is in the negated state. Even when the refresh clock PHY is always selected to generate the internal clock signal intCLK during the consumption standby mode, no particular problem occurs. Since the internal clock signal is generated internally during standby, the generation of the internal clock signal can be stopped when the wakeup signal ALIVE is negated during standby, and the internal clock signal is generated during a necessary period. Thus, current consumption can be reduced.

  FIG. 18 is a diagram showing the temperature dependence of the refresh time tREF. In FIG. 18, the horizontal axis indicates the temperature, and the vertical axis indicates the logarithmic value of the refresh time. As shown in FIG. 18, the refresh time tREF becomes shorter as the temperature rises. That is, the refresh time tREF includes various leakage currents with respect to the charges accumulated in the memory cell capacitor, such as junction leakage current at the storage node, channel leakage current of the transistor in the memory cell, and gate leakage current of the capacitor insulating film. Depends on temperature characteristics. These leakage currents increase as the temperature increases.

  When the refresh time tREF is fixed at the maximum guaranteed operating temperature of the semiconductor integrated circuit device (semiconductor chip), even if the chip temperature when set to the low power consumption standby mode is a low temperature close to room temperature, the maximum operation is achieved. Data is held according to the short refresh time tREF at the guaranteed temperature. Therefore, in this case, refresh is executed at intervals shorter than necessary, and current consumption increases. A count-up value is set in the registers Reg1-Regm in the register circuit 160 so as to set a plurality of stages of refresh time tREF corresponding to the temperature (operating temperature) range of the chip, and the count-up value is selected according to the temperature information. . In this case, refresh can be performed with a refresh time optimum for the chip temperature, and a minimum data holding standby current at the chip temperature can be realized.

  To the refresh time control circuit 150 shown in FIG. 15, the signal Indi is asserted immediately before the system side enters the sleep mode (low power consumption standby mode). In this sleep mode, the low power consumption standby mode instruction signal STBY is also asserted from the system side. The refresh time control circuit 150 generates a count-up value selection bit (refresh time control code) RTSEL corresponding to the chip temperature (operating temperature or ambient temperature) according to the assertion of the signal Indi, and sends it to the register circuit 160 in the power management unit 140. give.

  FIG. 19 is a diagram showing an example of the configuration of refresh time control circuit 150 shown in FIG. 19, the refresh time control circuit 150 includes a digital control temperature characteristic detection circuit 170 and a tuning code selection circuit 172 that generates a refresh time control code RTSEL according to an output value of the temperature characteristic detection circuit 170.

  The temperature characteristic detection circuit 170 has a positive characteristic short period oscillator 175 having a positive temperature characteristic and performing an oscillation operation according to a signal Indi having a predetermined time width, and the positive characteristic short period oscillator 175 when the signal Indi is asserted. Counter 176 that counts the pulse signal from output node NDB, negative characteristic short period oscillator 177 having a negative temperature characteristic and oscillating in accordance with the output signal of counter 176, and output pulse signal of negative characteristic short period oscillator 177 Is included.

  When the signal Indi is asserted, the counter 176 asserts its output signal until its count value reaches a predetermined value N. When the output signal of the counter 176 is negated, the positive characteristic oscillator 175 stops the oscillation operation.

  The negative characteristic short cycle oscillator 177 performs an oscillation operation when the output signal of the counter 176 is asserted. The counter 178 also counts the output pulses of the negative characteristic short cycle oscillator 177 when the output signal of the counter 176 is asserted.

  The oscillation period of the positive characteristic short period oscillator 175 may be longer than or equal to the oscillation period of the negative characteristic short period oscillator 177.

  FIG. 20 is a timing chart showing the operation of the temperature characteristic detection circuit 170 shown in FIG. Hereinafter, the operation of the temperature characteristic detection circuit 170 shown in FIG. 19 will be described with reference to FIG.

  A signal Indi given from, for example, a memory management unit or a controller on the system side is given as a pulse having a predetermined time width when entering the sleep mode. The temperature detection operation is performed during the period when the pulse is at the H level. In FIG. 20, one pulse of this signal Indi is shown enlarged. The signal Indi being given a plurality of times indicates that the pulse signal Indi is generated at the transition to each sleep mode. By detecting the chip temperature using this signal Indi, the refresh time corresponding to the chip temperature can be set reliably in the low power consumption standby mode.

  Positive characteristic short cycle oscillator 175 is activated in response to the transition of signal Indi at the H level to perform an oscillation operation. Counter 176 counts a predetermined number (N) of pulse signals applied via output node NDB of positive characteristic short period oscillator 175. Until the count value reaches N, the counter 176 outputs an H level signal. While the output signal of counter 176 is at the H level, positive characteristic short period oscillator 175, negative characteristic short period oscillator 177 and counter 178 are activated to perform predetermined operations, respectively.

  The positive characteristic short period oscillator 175 has a positive temperature characteristic, and the oscillation frequency increases as the temperature rises. The negative characteristic short period oscillator 177 has a negative temperature characteristic, and the oscillation frequency decreases as the temperature increases.

  While the output signal of node NDC of counter 176 is asserted (during H level), negative characteristic short cycle oscillator 177 performs an oscillation operation at a predetermined cycle. While the output signal of counter 176 is at the H level, counter 178 counts the number of pulses applied from negative characteristic short cycle oscillator 177 via node NDD.

  The tuning code selection circuit 172 compares the count value of the counter 178 with the count value N of the counter 176, and generates a refresh time control code RTSEL according to the magnitude result or the difference value thereof.

  FIG. 21 shows operating characteristics of short-cycle oscillators 175 and 177 shown in FIG. In FIG. 21, the horizontal axis indicates the temperature TMP, and the vertical axis indicates the oscillation frequency. The oscillation frequency of the positive characteristic oscillator (positive characteristic short period oscillator) 175 increases as the temperature TMP increases. On the other hand, the oscillation frequency of the negative characteristic oscillator (negative characteristic short period oscillator) 177 decreases as the temperature TMP increases. It is assumed that the oscillation frequency of the positive characteristic oscillator 175 and the short period oscillator 177 are equal at room temperature TMP0 (the short period oscillator 177 is M times the oscillation period of the short period oscillator 175 (M ≧ 1)). The count value of the counter 178 is N · M.

When the temperature TMP is higher than the room temperature TMP0, the oscillation frequency of the positive characteristic oscillator 175 is increased, while the oscillation frequency of the negative characteristic oscillator 177 is decreased. The period during which the counter 176 reaches the count value N is shortened, and the number of pulse signals from the short cycle oscillator 177 is also decreased. Accordingly, in this case, the count value of the counter 178 is smaller than the value N · M at room temperature. Therefore, when the count value of the counter 178 is smaller than the value N · M at room temperature, it can be determined that the temperature (operating temperature: chip temperature) TMP is higher than the room temperature TMP0.

  On the other hand, when temperature TMP becomes lower than room temperature TMP0, the oscillation frequency of negative characteristic short period oscillator 177 increases, while the oscillation frequency of positive characteristic short period oscillator 175 decreases. Therefore, the H level period of the output signal output from counter 176 via node NDC becomes longer. At this time, the number of pulses given from the negative characteristic short period oscillator 177 increases. Therefore, the count value of the counter 178 is larger than the count value N · M at room temperature TMP0. Therefore, when the count value of the counter 178 is larger than the count value N · M at room temperature, the temperature TMP can be identified as being lower than the room temperature TMP0.

  The tuning code selection circuit 172 generates a refresh time control code RTSEL in accordance with the difference between the count value of the counter 178 and the room temperature value N · M. The tuning code selection circuit 172 may simply decode the count value of the counter 178 and generate the refresh time control code RTSEL. The refresh time control code RTSEL may be generated in accordance with a signed difference value from the reference value with the counter value of the counter 178 at room temperature as a reference.

  It should be noted that the oscillation frequencies of short cycle oscillators 175 and 177 indicate a state where the oscillation frequency of short cycle oscillator 177 is high in the timing chart shown in FIG. However, the oscillation frequencies of these short period oscillators 175 and 177 may be set to the same frequency.

  The positive characteristic short period oscillator 175 having a positive temperature characteristic can be configured by, for example, a current-controlled oscillator, and the negative characteristic short period oscillator 177 having a negative temperature characteristic can be realized by, for example, an inverter type oscillator. Hereinafter, specific configurations of these oscillators 175 and 177 will be described.

  FIG. 22 is a diagram showing an example of the configuration of positive characteristic short period oscillator 175 shown in FIG. In FIG. 22, the positive characteristic short cycle oscillator 175 receives the n-stage cascaded CMOS inverters IV1-IVn, the output signal of the final-stage inverter IVn, and the oscillation activation signal OSC_ACT (= Indi). NAND gate NG1 for supplying an output signal to CMOS inverter IV1 and current control transistors CST1-CSTn for adjusting the operating current of CMOS inverters IV1-IVn are included.

  These current control source transistors CST1-CSTn are provided corresponding to CMOS inverters IV1-IVn, respectively, and are connected between the N-channel MOS transistor of the corresponding CMOS inverter and the ground node. A bias voltage BIASL having a positive temperature characteristic is applied to the gates of these current control transistors CST1-CSTn. A power supply voltage VDD is supplied as a high-side power supply voltage to the CMOS inverters IV1 to IVn.

In the current-controlled oscillator shown in FIG. 22, bias voltage BIASL has a positive temperature characteristic, and the voltage level rises as the temperature rises. In each of the current control transistors CST1 to CSTn, the gate voltage increases with an increase in temperature, and the amount of drive current increases. Therefore, the operating current of the CMOS inverters IV1-IVn increases as the temperature rises, and when the ring oscillator constituted by the NAND gate NG1 and the CMOS inverters IV1-IVn is operated, the oscillation cycle is shortened and the oscillation frequency is increased. Output signal OSC_AUT of this oscillator is applied to node NDB shown in FIG.

  In the configuration of positive characteristic short period oscillator 175 shown in FIG. 22, current control transistors CST1-CSTn may be formed of PMOS transistors and provided at the high-side power supply node. In this case, the voltage level of the bias voltage (BIASH) decreases as the temperature increases. Current control transistors may be provided for the high-side and low-side power supply nodes of CMOS inverters IV1 to IVn.

  FIG. 23 is a diagram illustrating an example of a circuit that generates the bias voltage BIASL. In FIG. 23, the bias voltage generation circuit converts a constant current generation circuit 180 that generates a constant current independent of temperature from the voltage VDD of the high-side power supply node, and converts the current I from the constant current generation circuit 180 into a voltage. A resistance element ZR1 for generating the bias voltage BIASL is included. The resistance value of the resistance element ZR1 has a positive temperature characteristic, and the resistance value increases as the temperature rises. Therefore, the voltage level of the bias voltage BIASL also rises as the temperature rises.

  The circuit for generating the bias voltage BIASL is not limited to the configuration of the bias voltage generating circuit shown in FIG. A constant voltage generation circuit that generates a bias voltage BIASL having a positive temperature characteristic may be used.

  The voltage VDD of the high-side power supply node to which the constant current generating circuit 180 is coupled is an external voltage. Instead, the internally generated power supply voltage is the high-side power supply voltage of the constant current generating circuit 180. May be used as Since constant current generation circuit 180 generates a high-side power supply voltage VDD and a constant current independent of temperature, either the external power supply voltage or the internally generated power supply voltage may be used as the high-side power supply voltage.

  24 is a diagram showing an example of the configuration of negative characteristic short period oscillator 177 shown in FIG. In FIG. 24, negative characteristic short cycle oscillator 177 is a NAND gate that receives k-stage cascaded CMOS inverters IV11-IV1k, an output signal of final stage inverter IV1k, and oscillation activation signal OSC_ACT applied from node NDC. NG2. The output signal of NAND gate NG2 is applied to first-stage inverter IV11. The oscillation pulse signal OSC_OUT is output from the final stage inverter IV1k to the node NDD.

  In the configuration shown in FIG. 24, negative characteristic short period oscillator 177 having a negative temperature characteristic is formed of an inverter type oscillator. The k-stage cascaded CMOS inverters IV11 to IV1k have a lower operating speed as the temperature rises. Therefore, as the temperature rises, the oscillation frequency decreases, and a negative temperature characteristic can be realized.

  The power supply voltage VDD is also applied to the high-side power supply node for the CMOS inverters IV11-IV1k.

  FIG. 25 is a diagram showing another configuration of the negative characteristic short period oscillator 177. In FIG. 25, negative characteristic short-cycle oscillator 177 includes h-stage cascaded CMOS inverters IV21-IV2h, RC delay circuits RCDL1-RCDLh provided at input portions of inverters IV21-IV2h, and final-stage inverter IV2h. NAND gate NG3 which receives the output signal and oscillation activation signal OSC_ACT.

CMOS inverters IV21-IV2h are connected in series with RC delay circuits RCDL1-RCLDh. Each of RC delay circuits RCDL1-RCLDh includes a resistance element R for transmitting a signal from the previous stage circuit to an input of the next stage CMOS inverter and a capacitance element C connected between the input of the corresponding CMOS inverter and the ground node. .

  An output signal of NAND gate NG3 is applied to CMOS inverter IV21 via first-stage RC delay circuit RCDL1. An oscillation output signal OSC_OUT transmitted on the node NDD is generated from the final stage CMOS inverter IV2h.

  In the case of the configuration of negative characteristic short period oscillator 177 shown in FIG. 25, RC delay circuits RCDL1-RCLDh are provided. In RCDL1-RCDLh, the resistance value of the resistance element R increases with increasing temperature, and the operating speed of the CMOS inverters IV21-IV2h also decreases with increasing temperature. Therefore, it is possible to realize an oscillator whose oscillation cycle becomes slower as the temperature rises. In particular, by using an RC delay circuit, a negative characteristic short period oscillator having a large temperature dependence can be realized.

  Also in oscillator 177 shown in FIG. 25, power supply voltage VDD is applied to the high-side power supply node of CMOS inverters IV21-IV2h.

  FIG. 26 shows an example of the configuration of tuning code selection circuit 172 shown in FIG. FIG. 26 shows an example in which the counter 178 of the temperature detection circuit outputs a 3-bit count value and the tuning code selection circuit generates a 2-bit refresh time control code.

  In FIG. 26, a tuning code selection circuit 172 receives an OR gate 172a that receives a count bit C <1: 0> from a counter 178, an output signal from the count bit C <2> and the OR gate 172a, and a selection bit Sel. AND gate 172c for generating <1>, and NAND gate 172b for generating selection bit Sel <0> in response to count bit C <2> and the output signal of OR gate 172a.

  FIG. 27 shows a list of logics of tuning code selection circuit 172 shown in FIG. As shown in FIG. 27, when the count value of the counter 178 is between 0 and 3, the count bit C <2> is “0” (L level), and the tuning code selection circuit 172 selects the selection bit from the NAND gate 172b. Sel <0> is “1” (H level), and the selection bit Sel <1> is “0”.

  When the count value is 4, the bits C <2: 0> are (1, 0, 0), and the output signal of the OR gate 172a is L level. Therefore, the selection bit Sel <0> from the NAND gate 172b is “1”, while the selection bit Sel <1> from the AND gate 172c is “0”.

  When the count value is 5 to 7, the bit C <2> is “1”, and one of the count bits C <1> and C <0> is “1”. Therefore, the output signal of the OR gate 172a is at the H level, and the selection bit Sel <1> from the AND gate 172c is “1”. On the other hand, since the NAND gate 172b receives H level signals at both inputs, the selection bit Sel <0> becomes “0”.

  In the case of the configuration of the tuning code selection circuit shown in FIG. 26, a 2-bit (m = 2) refresh time control code RTSEL is generated. As a result, the refresh time is adjusted in two stages.

The count value C <2: 0> is given from the counter 178 of the temperature characteristic detection circuit. When the count value of the counter 178 is increased, the oscillation frequency of the negative characteristic short period oscillator is increased. On the other hand, when the counter 178 is decreased, the oscillation frequency of the negative characteristic short period oscillator 177 is increased. Corresponds to the state of low. That is, when the value of the count bits C <2: 0> is increased, the ambient temperature (chip temperature) TMP is lower than the reference room temperature TMP0. On the other hand, when the value of the count bits C <2: 0> decreases, this corresponds to a state where the temperature TMP has increased.

  Therefore, when the control bits Sel <1: 0> are (10), the refresh time tREF is lengthened, and when the control bits Sel <1: 0> is (01), the refresh time is shortened. By adjusting the refresh time tREF according to the value of the count bits C <2: 0>, the refresh time according to the ambient temperature can be set.

  The count value of the counter 178 is not limited to 2 bits. An appropriate number of bits may be selected according to the oscillation frequency and temperature characteristics of the short-cycle oscillators 175 and 177. Further, the refresh time may be adjusted not in two stages but in three or more stages (the bit number m of the refresh time control code RTSEL is set to 3 or more).

  Further, in the temperature characteristic detection circuit 170 shown in FIG. 19, the short period oscillator 175 may have a negative temperature characteristic, and the short period oscillator 177 may have a positive temperature characteristic. The relationship between the count value and the temperature is only reversed, and similarly, the refresh time can be adjusted according to the count value of the counter 178.

  As described above, according to the sixth embodiment of the present invention, the temperature of the chip on which the semiconductor integrated circuit device is mounted is detected, and the refresh time is adjusted according to the detected temperature. Therefore, an optimal refresh time can be set according to the operating environment, and current consumption during standby can be reduced. As a result, the current required for data retention during standby (data retention standby current) can be set to a minimum value, and a standby current comparable to that of the ultra-low standby current SRAM can be realized.

  As the temperature detection circuit, oscillators having different temperature characteristics are used, and the temperature is detected based on their oscillation frequencies. These oscillators are arranged close to the chip of the semiconductor integrated circuit device. Therefore, the variation in the temperature characteristic of the oscillator due to the process dependence of the transistor parameter can be canceled out in the oscillators having different temperature characteristics, and accurate temperature detection can be performed.

  The signal Indi for setting the temperature detection and refresh time update timing is given from the system side a plurality of times when shifting to the sleep mode, performs a count operation for each pulse, and sets the refresh time based on the average value of the count values. A configuration for setting / adjusting may be used.

(Embodiment 7)
FIG. 28 schematically shows a structure of a DRAM core and peripheral circuits according to the seventh embodiment of the present invention. Hereinafter, the DRAM core and its peripheral circuit are referred to as a memory circuit.

The memory circuit shown in FIG. 28 differs from the memory circuit shown in FIG. 15 in the following points. That is, the refresh time control circuit 150 is supplied with the low power consumption standby mode instruction signal STBY instead of the signal Indi. The refresh time control circuit 150 internally generates a refresh time control code RTSEL when the low power consumption standby mode instruction signal STBY is asserted. The refresh time control circuit 150 further generates a delayed standby mode instruction signal STBYD in synchronization with the generated refresh time control code RTSEL and supplies it to the power management unit 140. The other configuration of the memory circuit shown in FIG. 28 is the same as that of the memory circuit shown in FIG. 15, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 29 is a diagram more specifically showing the configuration of refresh time control circuit 150 shown in FIG. The refresh time control circuit 150 shown in FIG. 29 differs from the refresh time control circuit 150 shown in FIG. 19 in the following points. That is, in refresh time control circuit 150, delay circuit 190 that delays low power consumption standby mode instruction signal STBY for a predetermined time, an output signal of delay circuit 190, and an output signal of counter 176 included in temperature characteristic detection circuit 170 And a gate circuit 192 for generating delayed standby mode instruction signal STBYD. The other configuration of refresh time control circuit 150 shown in FIG. 29 is the same as that of refresh time control circuit 150 shown in FIG. 19, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. .

  Gate circuit 192 asserts delayed standby mode instruction signal STBYD when the output signal of delay circuit 190 is asserted and becomes H level, and counter 176 completes the count operation and the signal of its output node NDC becomes L level. .

  FIG. 30 is a timing chart showing the operation of the refresh time control circuit 150 shown in FIG. Hereinafter, the operation of the refresh time control circuit 150 shown in FIG. 29 will be described with reference to FIG.

  At the time of shifting to the low power consumption standby mode, first, the low power consumption standby mode instruction signal STBY is asserted. In accordance with the assertion of the low power consumption standby mode instruction signal STBY, in the temperature characteristic detection circuit 170, the positive characteristic short period oscillator 175 starts an oscillation operation, and the counter 176 also starts a count operation. During the counting period of counter 176, the signal at node NDC is at H level, and short-cycle oscillator 177 and counter 178 perform oscillation and counting operations, respectively.

  When the counter 176 counts the count number N, the signal at the output node NDC of the counter 176 becomes L level. In response, short cycle oscillators 175 and 177 stop oscillating, and counter 178 stops counting. At this time, the count value of the counter 178 is given to the tuning code selection circuit 172, and the refresh time control code RTSEL from the tuning code selection circuit 172 is in a definite state (as shown in FIG. 26, the tuning code selection circuit 172 is performing a static selection operation).

  On the other hand, the output signal of delay circuit 190 becomes H level during the counting period of counter 176. In response, when the count period of counter 176 is completed, gate circuit 192 asserts delayed standby mode instruction signal STBYD (drives to H level).

  The power management unit 140 executes the same operation control as described in the first embodiment in accordance with the delayed standby mode instruction signal STBYD.

The length of the count period of the counter 176 varies depending on the temperature characteristic of the positive characteristic short period oscillator 175. The delay circuit 190 is set to H level during the count period of the counter 176 regardless of the ambient temperature. Therefore, when the count operation of counter 176 is completed, delayed standby mode instruction signal STBYD is changed to refresh time control code RTSEL.
Can be provided to the power management unit 140 in synchronization with the

  By using the delay circuit 190 and the gate circuit 192, the delayed standby mode instruction signal STBYD can be asserted in the low power consumption standby mode after the counting operation of the counter 176 is completed. Further, the delayed standby instruction signal DSTBY can be negated according to the low power consumption standby instruction signal STBY.

  Note that the delay time of the delay circuit 190 may be set to a time longer than the count period of the counter 176. In this case, after the refresh time control code RTSEL output from the tuning code selection circuit 172 is confirmed and the power management unit 140 selects the refresh time, the self-refresh mode (low-consumption standby mode) may be entered. it can.

  A low-consumption standby mode instruction signal STBY is supplied from the system side to the refresh time control circuit 150 instead of the signal Indi. Therefore, it is not necessary on the system side to generate both the low-consumption standby mode instruction signal STBY and the refresh time adjustment control signal Indi, and the timing control is facilitated. Further, only one type of signal is generated on the system side, and the configuration for refresh time adjustment in the low power consumption standby mode is simplified.

  Further, after the refresh time selection operation is completed internally in accordance with the standby mode instruction signal STBY, the delayed standby mode instruction signal STBYD is asserted to the refresh time control circuit 150 and supplied to the power management unit 140 in synchronization with this. . Therefore, the power management unit 140 can reliably set the refresh time according to the chip temperature (ambient temperature) when shifting to the low power consumption standby mode.

(Embodiment 8)
FIG. 31 schematically shows a whole structure of the memory circuit according to the eighth embodiment of the present invention. The memory circuit shown in FIG. 31 differs from the memory circuit shown in FIG. 28 in the following points. That is, an AND circuit 195 that receives wakeup signal ALIVE and low power consumption standby mode instruction signal STBY is provided for refresh time control circuit 150. When the output signal MODF of the AND circuit 195 is asserted, the refresh time control circuit 150 internally performs a refresh time selection operation corresponding to the temperature, and updates the refresh time control code RTSEL. The other configuration of the memory circuit shown in FIG. 31 is the same as that of the memory circuit shown in FIG. 28. Corresponding portions are allotted with the same reference numerals, and detailed description thereof is omitted.

  FIG. 32 schematically shows a configuration of register circuit 160 included in power supply management unit 140 shown in FIG. 32, a pulse generation circuit 200 that generates a pulse signal in accordance with wake-up signal ALIVE and delayed standby mode instruction signal STBYD is provided for register circuit 160. Pulse generation circuit 200 generates a one-shot pulse signal having a predetermined time width in accordance with the transition of wakeup signal ALIVE to the negated state or the transition of delayed standby mode instruction signal STBYD to the asserted state.

  In register circuit 160, selector SLKA is activated in accordance with the pulse signal from pulse generation circuit 200, and selects one of the values stored in registers Reg1-Regm in accordance with refresh time control code RTSEL provided from refresh time control circuit 150. And output as the refresh time set value REFTA.

  FIG. 33 is a timing chart representing an operation of the memory circuit shown in FIGS. Hereinafter, operations of the power management unit 140 and the refresh time control circuit 150 shown in FIGS. 31 and 32 will be described with reference to FIG.

  At time t10, the low power consumption standby mode instruction signal STBY is asserted on the system side. At this time, the wake-up signal ALIVE is in an asserted state. Therefore, the output signal MODF of the AND circuit 195 is asserted, and the refresh time control circuit 150 internally performs a refresh time selection operation (temperature detection and control bit generation).

  When the selection operation is completed in refresh time control circuit 150, refresh time control code RTSEL is determined at time t11, and delayed standby mode instruction signal STBYD is asserted in synchronization therewith. In accordance with the assertion of delayed standby mode instruction signal STBYD, pulse generation circuit 200 shown in FIG. 32 generates a one-shot pulse signal. In response, selector SLKA is activated in register circuit 160, and any stored value of registers Reg1-Regm is selected in accordance with refresh time control code RTSEL to generate refresh time set value REFTA. When the refresh is executed internally, the refresh is executed with a refresh time corresponding to the chip temperature (ambient temperature) at the time of transition to the standby mode.

  When the refresh period is completed at time t12, the wakeup signal ALIVE is negated. In response, output signal MODF of AND circuit 195 is negated, and the internal circuit (oscillator and counter) of refresh time control circuit 150 is reset. At this time, the pulse generation circuit 200 generates a one-shot pulse signal in accordance with the negation of the wake-up signal ALIVE. At this time, however, the refresh time control circuit 150 does not perform a new temperature detection operation. Therefore, the refresh time control code RTSEL has the same value as the refresh time control code A determined at time t11 (the internal refresh of the temperature detection circuit 170 is executed later than the update of the register circuit 160). Therefore, the refresh time set value REFTA from the register circuit 160 is also the same value as the value A set at time t11.

  When the wakeup signal ALIVE is asserted again at time t13, the output signal MODF of the AND circuit 195 is asserted again. In response, refresh time control circuit 150 again generates refresh time control code RTSEL corresponding to the chip temperature, and refresh time control code RTSEL is updated to a value B corresponding to the chip temperature. At this time, since the pulse generation circuit 200 shown in FIG. 32 does not generate a pulse yet, the refresh time setting value REFTA output from the register circuit 160 is maintained at the previous value A.

  When wake-up signal ALIVE is negated at time t14, pulse generation circuit 200 shown in FIG. 32 generates a one-shot pulse signal, and selector SLKA performs a new selection operation in register circuit 160, and a new refresh time The set value REFTA (B) is output.

  Therefore, at the time of shifting to the low power consumption standby mode, refresh is performed with the same refresh time in the first refresh period and the next second refresh period. In this case, the time from the transition to the low power consumption standby mode to the second refresh period (t13 to time t10) is short, and the operating temperature (chip temperature) of this memory circuit does not change so much, and no particular problem occurs. .

  When the low power consumption standby mode is maintained for a long time, it can be expected that the chip temperature (ambient temperature) gradually decreases when the memory circuit enters the low power consumption standby mode from the normal operation mode. That is, immediately after the transition to the low power consumption standby mode, even if the refresh time tREF is short, it can be expected that the refresh time tREF becomes longer as this time elapses. As a result, data can be held according to the refresh time tREF at an appropriate time interval according to the chip temperature, and the data holding standby current can be further reduced.

  A configuration in which the inside of the refresh time control circuit 150 is reset in response to the assertion transition of the delayed standby mode instruction signal STBYD may be used. In this case, wakeup signal ALIVE and low power consumption standby mode instruction signal STBY are in an asserted state, and refresh time control circuit 150 can again start oscillation and counting operations. Thereby, at time t12, the refresh period setting value REFTA can be updated according to the new refresh time control code.

  As described above, according to the eighth embodiment of the present invention, the refresh time setting information is updated according to the chip temperature (ambient temperature) at the time of transition to the standby mode and at the start of the subsequent self-refresh operation. Thereby, even when the chip temperature gradually decreases in the low power consumption standby mode, the refresh time can be adjusted, and the data holding standby current can be reduced.

(Embodiment 9)
FIG. 34 schematically shows an overall configuration of the memory circuit according to the ninth embodiment of the present invention. The memory circuit shown in FIG. 34 differs from the memory circuit shown in FIG. 15 in the following points. That is, the power supply control circuit 35 is not provided with the refresh clock generation circuit 12. On the other hand, the frequency of external clock signal CLK applied to power management unit 140 is switched between the normal operation mode and the standby mode, as in the configuration shown in FIG. That is, external clock signal CLK is a high-speed clock signal in the normal operation mode. On the other hand, when shifting to the low standby mode, the system side reduces the current consumption of this logic block (logic circuit such as a processor) in the low power consumption standby mode. Switch to a low-frequency clock signal.

  The power management unit 140 generates the internal clock signal intCLK by an oscillator that oscillates at an appropriate period of, for example, 15 ns during the low power consumption standby mode period and the external clock signal CLK is at the H level. In the DRAM core, this internal clock signal intCLK is used as a refresh clock to perform a refresh operation.

  The other configuration of the memory circuit shown in FIG. 34 is the same as that of the memory circuit shown in FIG. 15. Corresponding portions are allotted with the same reference numerals, and detailed description thereof is omitted.

  FIG. 35 schematically shows a structure of a portion for generating internal clock signal intCLK and refresh instruction signal / SREF of power management unit 140 shown in FIG. Internal clock generation circuit 210 corresponds to internal clock generation circuit 169 shown in FIG. 17, and refresh instruction signal generation circuit 220 corresponds to second counter 160 shown in FIG.

  In FIG. 35, internal clock generation circuit 210 selects one of the output pulse signal of oscillator 212 and external clock signal CLK in accordance with oscillator 212 that oscillates when activated and low-consumption standby mode instruction signal STBY. A selector 214 that generates a signal intCLK is included.

  Oscillator 212 oscillates when refresh instruction signal / SREF is at L level and external clock signal CLK is at H level. As described above, the oscillator 212 is an oscillator that oscillates at a period of 15 ns, for example. This oscillator 212 is not required to have a temperature detection function, and its oscillation frequency is adjusted so as to be less temperature dependent. Further, the power supply voltage VDD is used as the high-side power supply voltage of the oscillator 212.

  The selector 214 selects the output pulse signal of the oscillator 212 when the low power consumption standby mode instruction signal STBY is asserted, and selects the external clock signal CLK when the low power consumption standby mode instruction signal STBY is negated.

  Refresh instruction signal generation circuit 220 includes pulse generation circuits 221 and 222 that generate pulse signals when shifting to a low power consumption standby mode and when power is restored in the low power consumption standby mode. The pulse generation circuit 221 generates a one-shot pulse signal in response to the transition to the assertion of the power supply ready signal PWR_RDY. The pulse generation circuit 222 generates a one-shot pulse signal in response to the transition to the assertion of the low power consumption standby mode instruction signal STBY.

  Refresh instruction signal generation circuit 220 further includes an AND circuit 223 that receives the pulse signal of pulse generation circuit 221 and the low-consumption standby mode instruction signal STBY, and an AND circuit 224 that receives the output signal of pulse generation circuit 222 and external clock signal CLK. OR circuit 225 receiving the output signals of AND circuits 223 and 224.

  Therefore, the AND circuit 223 generates a one-shot pulse signal that becomes H level when the internal power supply is restored in the low power consumption standby mode. The AND circuit 224 generates a one-shot pulse signal when the external clock signal CLK is at the H level during the transition to the low power consumption standby mode. Therefore, a one-shot pulse signal is generated from the OR circuit 225 at the time of transition to the standby mode or when the power supply is restored internally.

  Refresh instruction signal generation circuit 220 is further set to a counter 226 that counts internal clock signal intCLK at the time of activation, and a set / set that is set in response to the count up signal of counter 226 and reset in accordance with the output signal of OR circuit 225 A reset flip-flop 227 is included.

  The counter 226 refreshes the internal signal intCLK while the low power consumption standby mode instruction signal STBY and the wakeup signal ALIVE are at the H level (asserted), that is, in the low power consumption standby mode, while the wakeup signal ALIVE is asserted. When the number of cycles NREF is counted, a one-shot count-up signal is generated.

  Set / reset flip-flop 227 generates refresh instruction signal / SREF from its output Q. Therefore, refresh instruction signal / SREF is asserted when the output signal of OR circuit 225 goes high, and negated when the count value of counter 226 reaches refresh cycle number NREF and the entire memory space is refreshed.

  Here, the AND circuit 223 is used to prevent the power supply ready signal PWR_RDY from rising and entering the low power consumption refresh mode internally when the power is turned on at the time of system startup.

FIG. 36 is a timing diagram representing an operation of the memory circuit according to the ninth embodiment of the present invention. The operation of the circuits shown in FIGS. 34 and 35 will be described below with reference to FIG.

  At the time of shifting to the low power consumption standby mode, the frequency of the external clock signal CLK is first switched to a low frequency on the controller or processor (logic circuit) side of the system. Thereafter, the low power consumption standby mode instruction signal STBY is asserted.

  In the power management unit 140, the pulse generation circuit 222 of the refresh instruction signal generation circuit 220 generates a one-shot pulse signal in accordance with the assertion of the low power consumption standby mode instruction signal. That is, when external clock signal CLK rises to H level in cycle T1, flip-flop 227 is reset via AND circuit 224 and OR circuit 225, and refresh instruction signal / SREF is asserted.

  In response to the assertion of refresh instruction signal / SREF, oscillator 212 is activated in internal clock generation circuit 210 and oscillates at a predetermined cycle of, for example, 15 ns. The selector 214 selects the output signal of the oscillator 212 in accordance with the assertion of the low power consumption standby mode instruction signal STBY. Therefore, internal clock signal intCLK is issued sequentially from cycle Ta1 after a predetermined time after time T1. In the control unit 30 of the DRAM core, when the refresh instruction signal / SREF is asserted, a control signal for executing the refresh operation is generated according to the internal clock signal intCLK (row access is executed).

  In the low power consumption standby mode, the counter 226 counts the internal clock signal intCLK and counts up to the number of refresh cycles NREF in the memory core when the wakeup signal ALIVE is asserted. When the cycle TaNREF of the internal clock signal intCLK is reached, the count-up signal output from the counter 226 is asserted. In response, set / reset flip-flop 227 is set, and refresh instruction signal / SREF is negated. Responsively, oscillator 212 stops its oscillation operation, and internal clock signal intCLK is fixed at the L level.

  When refresh instruction signal / SREF is negated, wake-up signal ALIVE is negated after a predetermined time (see FIG. 17). Thereby, also in the power supply control circuit 35, the internal power supply is stopped. In the I / O unit 20 of the DRAM core, the power down instruction signals PD and / PD have already been asserted at the time of transition to the standby mode, and the supply of the power supply voltage is stopped.

  The wake-up signal ALIVE is maintained in a negated state in the power management unit 140 for a period defined by the refresh time control code RTSEL from the refresh time control circuit 150. When the wakeup signal ALIVE is negated, the power supply ready signal PWR_RDY is also negated, and the generation operation of all internal voltages such as the voltage VPP in the power supply control circuit 35 is stopped.

  When a predetermined refresh interval elapses, the wakeup signal ALIVE is asserted in synchronization with the rising of the external clock signal CLK in the cycle Tn. The counter 226 is enabled in accordance with the assertion of the wakeup signal ALIVE. At this time, since the internal clock signal intCLK has not yet been generated, the count value of the counter 226 is not updated.

When the wake-up signal ALIVE is asserted, internal voltages are generated again in the power supply control circuit 35. When the voltage level of these internal voltages or the reference voltage for generating the internal voltage returns to a predetermined value, the power supply ready signal PWR_RDY is asserted. The In accordance with the assertion of power supply ready signal PWR_RDY, pulse generation circuit 221 shown in FIG. 35 generates a one-shot pulse signal. In response, set / reset flip-flop 227 is reset via AND circuit 223 and OR circuit 225, and refresh instruction signal / SREF is asserted again.

  In accordance with the assertion of refresh instruction signal / SREF, oscillator 212 starts an oscillation operation, and internal clock signal intCLK is generated. Therefore, again, refresh addresses QA [1] to QA [NREF] are sequentially generated during the cycle Tan to cycle Tan + NREF-1 of the internal clock signal intCLK, and centralized refresh is executed. When this centralized refresh is completed, the refresh instruction signal / SREF is negated again to set the power supply control circuit 35 to the power down mode again. Thereafter, a series of these operations are repeatedly executed while the low power consumption standby mode is set.

  Periods PA, PB, PC, and PD are the same as those in the first embodiment. In addition, the power cut-off control in the I / O unit 20 in the control unit 30 in the control unit 30 when the wake-up signal ALIVE is negated in the power control circuit 35 and the power-down mode instruction signals PD and / PD are asserted This is the same as in the case of Form 1 (see FIGS. 4 and 5).

  Also in this case, the refresh time control circuit 150 adjusts according to the chip temperature in the refresh period according to the signal Indi given from the system side, although not shown in the timing chart of FIG. In order to adjust the refresh time, the configuration of the previous embodiment 7 or 8 may be used.

  As described above, according to the ninth embodiment of the present invention, the refresh clock is generated using the external clock signal CLK whose frequency is lowered in the low power consumption standby mode. Therefore, the power supply control circuit 35 does not require a circuit for generating the refresh clock PHY, and the current consumption can be reduced. In addition, the same effects as in the previous sixth to eighth embodiments can be obtained.

(Embodiment 10)
FIG. 37 schematically shows a whole structure of the memory circuit according to the tenth embodiment of the invention. In FIG. The memory circuit shown in FIG. 37 differs from the memory circuit shown in FIG. 34 in the following points. That is, to refresh time control circuit 150, output signal MODF of AND circuit 195 receiving wake-up signal ALIVE and low power consumption standby mode instruction signal STBY is applied as a refresh time adjustment activation signal. The other configuration of the memory circuit shown in FIG. 37 is the same as that of the memory circuit shown in FIG. 34, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  The configuration of the memory circuit shown in FIG. 37 is substantially equivalent to a combination of the configurations shown in the eighth and ninth embodiments. Therefore, even in the configuration of the memory circuit shown in FIG. 37, current consumption can be further reduced. Further, even if the ambient temperature changes as the standby mode setting time elapses, it is possible to accurately set the refresh time according to the chip temperature and reduce the current consumption.

In FIG. 37, a memory management unit 252 and a clock generation circuit 254 are further shown. The memory management unit 252 and the clock generation circuit 254 are provided in the logic circuit portion outside the memory circuit or in the logic circuit peripheral portion. The memory management unit 252 generates an address signal ADD and a command CMD according to an access request from logic such as a processor (not shown), and asserts a low power consumption standby mode instruction signal STBY according to the sleep mode instruction signal SLEEP.

  The sleep mode instruction signal SLEEP is asserted when the processing of the logic circuit is stopped for a predetermined time or in accordance with an external standby instruction signal. The clock generation circuit 254 switches the frequency of the generated clock signal CLK from the high frequency to the low frequency in accordance with the assertion of the sleep mode instruction signal SLEEP. Clock signal CLK from clock generation circuit 254 is applied to each circuit block such as a DRAM core and a logic circuit on a semiconductor chip on which a system LSI is formed.

  As described above, according to the tenth embodiment of the present invention, in the configuration in which the clock signal is a low frequency clock signal in the low power consumption standby mode, the refresh time control code according to the wakeup signal and the low power consumption standby mode instruction signal Is generated. Therefore, even if the chip temperature changes over time after the transition to the standby mode, the refresh time can be set to the optimum value following the temperature change, and the standby current for data retention is reduced. be able to.

  Although the operation of the memory circuit according to the tenth embodiment has not been described, the refresh time control circuit 150 updates the refresh time control code RTSEL when the wakeup signal ALIVE is asserted, as in the previous eighth embodiment. The power management unit 140 sets the refresh time tREF according to the refresh control bit when the wakeup signal ALIVE is negated. In the first refresh period, the refresh time control code RTSEL is set according to the assertion of the standby instruction signal STBY. In power management unit 140, refresh time update is enabled according to the transition to assertion of delayed standby mode instruction signal STBYD, and the refresh time is set according to refresh time control code RTSEL.

  Therefore, the configuration of the eighth embodiment can be used as the configuration of the register circuit of power supply management unit 140 and the internal configuration of refresh time control circuit 150.

(Embodiment 11)
FIG. 38 schematically shows a structure of refresh time control circuit 150 according to the eleventh embodiment of the present invention. In the refresh time control circuit 170 shown in FIG. 38, the short-cycle oscillators 175 and 177 perform an oscillation operation when the signal Indi is asserted. The counters 176 and 178 count the output pulse signals of the short cycle oscillators 175 and 177 when the signal Indi is asserted.

  In this temperature characteristic detection circuit 170, a subtraction circuit 260 for subtracting the count values of the counters 176 and 178 is further provided. When the signal Indi is negated, the counters 176 and 178 are reset to the initial values after the output signal of the subtraction circuit 260 is determined, or the respective count values are reset in response to the transition to the assertion of the signal Inti. Is done.

  Tuning code selection circuit 172 generates refresh time control code RTSEL according to output value DIF of subtraction circuit 260 of temperature characteristic detection circuit 170.

  Short cycle oscillators 175 and 177 have a positive temperature characteristic and a negative temperature characteristic, respectively.

FIG. 39 is a timing chart showing the operation of the temperature characteristic detection circuit shown in FIG. The operation of refresh time control circuit 150 shown in FIG. 38 will be described below with reference to FIG.

  When shifting to the sleep mode, the memory circuit shifts to the value consumption standby mode. At this time, before the standby mode instruction signal STBY (not shown) is asserted, a signal Indi for adjusting the refresh time is issued from the system side. In accordance with the assertion of the signal Indi, the short period oscillators 175 and 177 oscillate. Counters 176 and 178 are also enabled during the assertion period of signal Indi and count the output pulse signals of short period oscillators 175 and 177, respectively.

  At a low temperature, the oscillation frequency of the negative characteristic short period oscillator 177 is higher than the oscillation frequency of the positive characteristic short period oscillator 175, and the count value of the counter 178 is higher than the count value of the count 176. On the other hand, at a high temperature, the oscillation frequency of the positive short-cycle oscillator 175 is higher than the oscillation frequency of the short-cycle oscillator 177. Therefore, when the temperature rises, the count value of the counter 176 becomes larger than the count value of the counter 178. The subtraction circuit 260 subtracts the count values of these counters 176 and 178, and generates a difference value DIF indicating the subtraction result. Therefore, the chip temperature (ambient temperature) can be identified by the difference value DIF. Tuning code selection circuit 172 is composed of, for example, a decoding circuit, and generates m-bit refresh time control code RTSEL according to this difference value DIF.

  FIG. 40 shows an operation mode of temperature characteristic detection circuit 170 shown in FIG. As shown in FIG. 40, the oscillation frequency of the positive short-period oscillator 175 increases as the temperature TMP increases. On the other hand, the oscillation frequency of the negative characteristic short period oscillator 177 increases as the temperature TMP decreases.

  Consider a state where the oscillation frequencies of these short-cycle oscillators 175 and 177 are equal at room temperature TMP0. In this case, the count values of the counters 176 and 178 are equal, and the output difference value DIF of the subtraction circuit 260 is zero. Therefore, when the difference value DIF is expressed in 2's complement notation, if the sign bit is “0”, the difference value DIF is positive, and the oscillation frequency of the positive characteristic short period oscillator 175 is less than the negative characteristic. It is shown that it is higher than the oscillation frequency of the periodic oscillator 177. Therefore, in this case, the temperature TMP can be identified as being higher than the room temperature TMP0. On the other hand, when the sign bit of the difference value DIF is “1”, it is indicated that the oscillation frequency of the positive short-cycle oscillator 175 is lower than the oscillation frequency of the negative short-cycle oscillator 177. Therefore, in this case, it is identified that the temperature TMP is lower than the room temperature TMP0.

  In addition, the difference value DIF can identify how much the temperature TMP is deviated from the room temperature TMP0. Therefore, the temperature TMP can be divided into multi-stage regions, and the refresh time tREF can be set for each temperature region. In this case, the tuning code selection circuit 1752 is configured to decode the difference value DIF and generate an m-bit refresh time control code RTSEL. As the configuration of the tuning code selection circuit 172, the following configuration can be used. Decodes m-bit refresh time control code RTSEL, sets only one bit out of m bits to “1”, and designates one of registers Reg 1 -Regm in the register circuit included in power management unit 140 To do.

  In the eleventh embodiment, as the configuration of the power management unit 140, the configurations shown in the previous sixth to tenth embodiments can be used.

Further, the oscillation frequency of short-cycle oscillators 175 and 177 is not particularly required to be equal at room temperature TMP0. It is only necessary that the negative characteristic short cycle oscillator 177 has an oscillation frequency of M · F0 with respect to the oscillation frequency F0 of the short cycle oscillator 175 at room temperature TMP0 (M ≧ 1). Since the difference value DIF of the number of output pulses within a certain period changes with temperature, even in that case, the tuning code selection circuit 172 using the decoding circuit may generate the m-bit refresh time control code RTSEL. it can.

  Further, as the short-cycle oscillators 175 and 177, the configuration shown in the previous sixth embodiment can be used. However, in order to accurately detect the temperature using the difference value, it is desirable to use a circuit having a large temperature characteristic as an oscillator. For example, when adjusting the operating current of a CMOS inverter with a bias voltage, a resistance element (polysilicon resistance) having a high temperature dependency is used as a resistance element for converting a constant current into a voltage, and its resistance value is increased as much as possible. This is because if the resistance value is large, the resistance value that changes in accordance with the temperature change becomes large.

  As described above, according to the eleventh embodiment of the present invention, the refresh time control circuit counts the number of output pulses of the oscillator within a certain period and generates a refresh time control code according to the difference value of the count value. Yes. Therefore, it is possible to accurately set the refresh time to an optimum value according to the chip temperature (ambient temperature or operating temperature).

  Also, the temperature is detected using the difference value, and variations in transistor characteristics (operation speed) due to process variations can be canceled out in the positive and negative characteristics oscillators, and the temperature can be detected accurately. Is possible.

(Embodiment 12)
FIG. 41 schematically shows a structure of refresh time control circuit 150 according to the twelfth embodiment of the present invention. In the configuration of the refresh time control circuit 150 shown in FIG. 41, a control circuit 270 that generates a one-shot pulse signal in accordance with a signal Indi is provided before the temperature characteristic detection circuit 170.

  The temperature characteristic detection circuit 170 is activated when the output pulse signal of the control circuit 270 is activated, and is activated when the output pulse signal of the control circuit 270 is generated. A counter 176 that counts 175 output pulse signals is included. The count value of the counter 176 is given to the tuning code selection circuit 172.

  In the configuration of refresh time control circuit 150 shown in FIG. 41, one oscillator 175 having one positive temperature characteristic is used. The refresh time is adjusted in accordance with the change in the oscillation frequency due to the temperature characteristic of the oscillator 175.

  FIG. 42 is a timing chart showing the operation of the temperature characteristic detection circuit 170 shown in FIG. The operation of temperature characteristic detection circuit 170 shown in FIG. 41 will be described below with reference to FIG.

When entering the sleep mode, first, the signal Indi is asserted from the system side. The control circuit 270 generates a pulse signal having a predetermined time width in response to the assertion of the signal Indi. Short cycle oscillator 175 and counter 176 operate during a period (assertion period) when the pulse signal applied from control circuit 270 to node NDA is at the H level. At a low temperature, the oscillation frequency of the positive characteristic short period oscillator 175 is low and the count value of the counter 176 is small. On the other hand, at a high temperature, the oscillation frequency of positive characteristic short-cycle oscillator 175 increases and the count value of counter 176 increases. In accordance with the count value of the counter 176, the tuning code selection circuit 172 generates a refresh time control code RTSEL.

  FIG. 43 is a diagram showing an operation principle of the temperature characteristic detection circuit 170 shown in FIG. In FIG. 43, the horizontal axis represents the temperature TMP, and the vertical axis represents the frequency F. Now, it is assumed that the oscillation frequency of the positive characteristic short period oscillator 175 is F0 at room temperature TMP0. When the temperature TMP becomes higher than the room temperature TMP0, the oscillation frequency of the positive short-cycle oscillator 175 increases (F0 <F). On the other hand, when the temperature TMP becomes lower than the room temperature TMP0, the oscillation frequency F of the positive short-cycle oscillator 175 becomes lower than the frequency F0 (F0> F). Therefore, when the count value of counter 176 increases above the count value corresponding to frequency F0, temperature TMP is higher than room temperature TMP0, and conversely, the count value of counter 176 is smaller than the count value corresponding to frequency F0. In this case, the temperature TMP can be identified as being lower than the room temperature TMP0. Further, by looking at the count value of the counter 176, the deviation between the temperature TMP and the room temperature TMP0 can be identified together.

  Therefore, tuning code selection circuit 172 generates m-bit refresh time control code RTSEL according to the count value of counter 176 with reference to refresh time tREF for frequency F0 at room temperature TMP0. In this case, the tuning code selection circuit 172 can be constituted by a decoding circuit that decodes the count value of the counter 176. Alternatively, the tuning code selection circuit 172 may be configured by a table memory in which the control code RTSEL is used as an address and the address of a register corresponding to the refresh time is stored in each address.

  Further, as the configuration of the positive characteristic short period oscillator 175, as shown in FIG. 22, a current control type oscillator can be used (the bias voltage is increased as the temperature rises).

  When the count value of the counter is differentiated using the subtracting circuit as in the eleventh embodiment, it can be considered that the temperature characteristic is expanded equivalently due to the influence of both the positive and negative temperature characteristics. Therefore, when using the difference value, it is not required that the temperature characteristic be particularly large. However, in the twelfth embodiment, the refresh time is set according to the temperature characteristic of one positive characteristic short period oscillator 175. Therefore, it is desirable to use a circuit having a temperature dependence as large as possible as the positive characteristic short period oscillator 175. In order to increase this temperature characteristic, the temperature characteristic of the bias voltage is increased in the current-controlled oscillator (the temperature characteristic of the drive element for current / voltage conversion of the bias voltage generation unit is increased).

  The configuration of the refresh time control circuit shown in the twelfth embodiment can also be applied to the refresh time control circuit of the memory circuit shown in the sixth to tenth embodiments. The oscillator may be an oscillator having negative temperature characteristics.

  The control circuit 270 is supplied with a signal Indi. However, as shown in parentheses in FIG. 41, the control circuit 270 may be configured to generate a pulse signal having a predetermined time width in accordance with the assertion of the low power consumption standby mode instruction signal STBY.

  Alternatively, a configuration may be used in which delayed low-consumption standby instruction signal STBYD is generated in accordance with the deassertion of the pulse signal on node NDA of control circuit 270.

As described above, according to the twelfth embodiment of the present invention, one oscillator and one counter are used as the temperature characteristic detection circuit in the refresh time control circuit. Therefore, the area occupied by the temperature characteristic detection circuit can be reduced, and the current consumption can be reduced. In addition, as a memory circuit, the effects of the memory circuits described in Embodiments 6 to 10 can also be obtained.

  In the configurations shown in the sixth to twelfth embodiments, an m-bit refresh time control code is generated by the tuning code selection circuit to select a register of the register circuit. In this case, a table memory for selecting a stored value (a count value for setting a negation period of the signal ALIVE) using a value given from the temperature characteristic detection circuit 170 to the tuning code selection circuit 172 as an address may be used.

  Further, the register circuit may be constituted by a ROM, and the stored value may be fixedly set, or the stored value of the register may be set at initialization at power-on.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The semiconductor integrated circuit device according to the present invention can be applied to a DRAM core included in a system LSI. As an application of this system LSI, there is a device using a battery such as a portable device as a power source, and the current consumption during standby can be greatly reduced by applying it to an application requiring low standby current consumption. . In general, the present invention can also be applied to an embedded DRAM.

1 is a schematic block diagram of a system LSI 1 according to a first embodiment of the present invention. It is a diagram illustrating a memory circuit MEM1 and its peripheral circuits according to the first embodiment of the present invention. It is a diagram illustrating a configuration of a memory array and its peripheral circuit according to the first embodiment of the present invention. 1 is a schematic block diagram illustrating an I / O unit 20 according to a first embodiment of the present invention. 3 is a diagram illustrating an internal voltage generation circuit that generates an internal voltage of a power supply control circuit 35. FIG. 5 is a timing chart showing an operation in a standby mode of the memory circuit according to the first embodiment of the present invention. FIG. 11 schematically shows a memory array and its peripheral circuits according to a second embodiment of the present invention. It is a figure explaining the space of the memory array refreshed in response to the input of the input control data DR [1: 0]. It is a figure explaining the power supply with respect to the subarray block group according to Embodiment 2 of this invention. It is a figure which shows roughly the structure of the memory array according to Embodiment 3 of this invention, and its peripheral circuit. FIG. 14 is a timing diagram representing an operation in a standby mode of a memory circuit according to a third embodiment of the present invention. It is a figure which shows schematic structure of the memory array and its peripheral circuit according to Embodiment 4 of this invention. It is a figure explaining the case where the defective line contained in a memory array is relieved with a redundant line. It is a figure which shows the relationship between the refresh time tREF in a refresh test, and the number of defective bits which do not satisfy the refresh time tREF. It is a figure which shows roughly the whole structure of the semiconductor integrated circuit device according to Embodiment 6 of this invention. FIG. 16 is a timing chart showing an operation of the semiconductor integrated circuit device shown in FIG. 15. FIG. 16 schematically shows configurations of a refresh clock generation circuit and a power management unit shown in FIG. 15. It is a figure which shows the temperature dependence of refresh time. FIG. 16 schematically shows a configuration of a refresh time control circuit shown in FIG. 15. FIG. 20 is a timing chart showing an operation of the refresh time control circuit shown in FIG. 19. FIG. 20 is a diagram for explaining the operation principle of the refresh time control circuit shown in FIG. 19. FIG. 20 is a diagram illustrating an example of the configuration of the positive-characteristic short-period oscillator illustrated in FIG. 19. FIG. 23 is a diagram illustrating an example of a circuit that generates a bias voltage illustrated in FIG. 22. It is a figure which shows an example of a structure of the negative characteristic short period oscillator shown in FIG. FIG. 20 is a diagram showing another configuration of the negative characteristic short period oscillator shown in FIG. 19. FIG. 20 is a diagram illustrating an example of a configuration of a tuning code selection circuit illustrated in FIG. 19. It is a figure which shows the logic of operation | movement of the tuning code selection circuit shown in FIG. It is a figure which shows roughly the whole structure of the semiconductor integrated circuit device according to Embodiment 7 of this invention. FIG. 29 schematically shows a configuration of a refresh time control circuit shown in FIG. 28. FIG. 30 is a timing chart showing an operation of the refresh time control circuit shown in FIG. 29. It is a figure which shows roughly the structure of the whole semiconductor integrated circuit device according to Embodiment 8 of this invention. FIG. 32 is a diagram schematically showing a configuration of a register circuit and parts related to the register circuit included in the power management unit shown in FIG. 31. FIG. 32 is a timing chart showing an operation of the semiconductor integrated circuit device shown in FIG. 31. It is a figure which shows roughly the whole structure of the semiconductor integrated circuit device according to Embodiment 9 of this invention. It is a figure which shows schematically the structure of the principal part of the power management part shown in FIG. FIG. 35 is a timing chart showing an operation of the semiconductor integrated circuit device shown in FIG. 34. It is a figure which shows roughly the structure of the whole semiconductor integrated circuit device according to Embodiment 10 of this invention. It is a figure which shows roughly the structure of the refresh time control circuit according to Embodiment 11 of this invention. FIG. 39 is a timing chart showing an operation of the refresh time control circuit shown in FIG. 38. It is a figure for demonstrating the operation | movement principle of the temperature characteristic detection circuit shown in FIG. It is a figure which shows roughly the structure of the refresh time control circuit of the semiconductor integrated circuit device according to Embodiment 12 of this invention. FIG. 42 is a timing chart showing an operation of the refresh time control circuit shown in FIG. 41. FIG. 42 is a diagram for describing an operation principle of a refresh time control circuit shown in FIG. 41.

Explanation of symbols

1 system LSI, 4 row decoder, 5 column decoder, 11 refresh address counter, 12, 12 # refresh clock generation circuit, 13 reference voltage level detection circuit, 15, 15s memory array, 20 I / O unit, 25 array drive control unit , 30, 31 control unit, 35, 35 # power control circuit, 40, 40 #, 40 # a, 41 power management unit, 51 data line control unit, 52 write driver, 53 read amplifier, 54 output unit, 61
VPP generation circuit, 62 VBB generation circuit, 63 VCR generation circuit, 64 VBL generation circuit, 65 VDDT generation circuit, 140 power supply management unit, 150 refresh time control circuit, 160 register circuit, 162 first counter, 164 wakeup control circuit, 166 Second counter, 168 power down control circuit, 169 internal clock generation circuit, 170 temperature characteristic detection circuit, 172 tuning code selection circuit, 175 positive characteristic short period oscillator, 176 counter, 177 negative characteristic short period oscillator, 178 counter, 190 delay Circuit, 192 gate circuit, 195 AND circuit, 200 pulse generation circuit, 210 internal clock generation circuit, 220 refresh instruction signal generation circuit, 260 subtraction circuit, 270 control circuit.

Claims (20)

A semiconductor integrated circuit device having a normal mode and a standby mode,
A memory array having a plurality of memory cells;
A control circuit for executing a refresh operation of the plurality of memory cells in accordance with a refresh instruction signal based on a predetermined refresh time for the memory array;
An internal voltage generation circuit that receives an external power supply voltage and generates an internal voltage for executing a predetermined operation of the memory array;
A management unit for controlling power supply of the semiconductor integrated circuit,
The internal voltage generation circuit includes a first power cut-off switch that cuts off the supply of the external power supply voltage in response to an instruction,
In the standby mode, the control circuit performs the refresh operation in response to the input of the refresh instruction signal based on the predetermined refresh time,
The management unit instructs the first power cut-off switch to cut off the supply of the external power supply voltage after the refresh operation is completed in the standby mode, and the first power cut-off before executing the refresh operation. A semiconductor integrated circuit device that instructs a switch to supply the external power supply voltage.   The semiconductor integrated circuit device according to claim 1, wherein the management unit outputs the refresh instruction signal based on the predetermined refresh time in synchronization with a clock signal. An input / output unit for receiving and supplying external power supply voltage independently of the internal voltage generation circuit to execute data exchange with the memory array;
The input / output unit includes a second power cut-off switch that cuts off the supply of the external power supply voltage in response to an instruction,
The semiconductor integrated circuit device according to claim 1, wherein the management unit instructs the second power cut-off switch to cut off the supply of the external power supply voltage in response to a signal that instructs the standby mode. The external power supply voltage includes a first power supply voltage and a second power supply voltage that is lower than the first power supply voltage,
An array driver for driving the memory array under the control of the controller;
The memory array is divided into a plurality of memory blocks;
The array driving unit is provided corresponding to each of the plurality of memory blocks, and each receives a supply of the internal voltage generated by the internal voltage generation circuit and the second power supply voltage, and drives the corresponding memory block A plurality of array drive units for
A plurality of second drive units provided corresponding to the plurality of array drive units, respectively, for shutting off supply of at least one of the internal voltage and the second power supply voltage to the corresponding array drive units in response to an instruction. Including two power-off switches,
In the standby mode, the control circuit receives the refresh instruction signal for instructing execution of the refresh operation to some selected memory blocks of the plurality of memory blocks, and is selected. Driving the array driving unit corresponding to the memory block to perform the refresh operation on the memory cells included in the selected memory block;
The management unit responds to an input of a signal for instructing the standby mode, the internal voltage with respect to the second power cut-off switch of the array drive unit corresponding to the memory block that is not selected for the refresh operation. The semiconductor integrated circuit device according to claim 1, wherein an instruction to cut off supply of at least one of the second power supply voltages is given.   5. The semiconductor integrated circuit device according to claim 2, wherein a timing at which the refresh instruction signal is asserted is adjusted according to a temperature to be used.   The management unit asserts the refresh instruction signal to the selected memory block based on an input of data for selecting a part of the plurality of memory blocks during the standby mode, and The semiconductor integrated circuit device according to claim 4, wherein execution of a refresh operation is instructed.   The semiconductor integrated circuit device operates in synchronization with a first clock signal in the normal mode, and operates in synchronization with a second clock signal having a frequency lower than that of the first clock in the standby mode. The semiconductor integrated circuit device according to claim 1. A plurality of the memory arrays;
The control circuit provided corresponding to a plurality of the memory arrays;
The internal voltage generation circuit provided corresponding to a plurality of the memory array,
In the standby mode, the control circuit corresponding to some selected memory arrays of the plurality of memory arrays receives the refresh instruction signal that instructs execution of the refresh operation, Executing the refresh operation on the memory array,
The management unit is configured to respond to an input of a signal for instructing the standby mode, and the first power cut-off switch of the internal voltage generation circuit corresponding to the memory array to be unselected among the plurality of memory arrays. The semiconductor integrated circuit device according to claim 1, wherein an instruction to cut off the supply of the external power supply voltage is given to the device.   A test standard at the time of wafer test is set so that a refresh time is longer than other memory blocks for some selected memory blocks among the plurality of memory blocks in which the refresh operation is performed in the standby mode. The semiconductor integrated circuit device according to claim 4, which is changed. A memory array having memory cells that require refresh of stored data; an array control unit that controls a refresh operation of data in the memory cells of the memory array; and data in the memory cells of the memory array under the control of the array control unit A memory core including an array drive control unit for performing refresh of the memory and an input / output unit for writing and reading data to and from the memory cell,
A refresh time control circuit for detecting an ambient temperature of the memory core according to a refresh execution instruction signal, and setting a count value for defining a refresh time according to the detection result;
Power supply control for generating a control signal for supplying a necessary power supply voltage to the memory core and interrupting power supply to the input / output unit according to a standby mode instruction signal for instructing a standby mode when a wakeup signal is activated A power management unit that controls a refresh operation of the memory core, and the power management unit has a cycle defined according to a count value from the refresh time control circuit when the standby mode instruction signal is activated. A wake-up signal is deactivated and applied to at least the power supply control circuit, and a refresh instruction signal is activated and applied to the memory core. The array control unit of the memory core controls the array drive according to the activation of the refresh instruction signal. Control the memory cell to refresh the memory cell data. A semiconductor integrated circuit device.   11. The semiconductor integrated circuit device according to claim 10, wherein the refresh execution instruction signal is supplied from an external controller and is activated before the standby mode instruction signal is activated when entering the standby mode.   11. The semiconductor integrated circuit device according to claim 10, wherein the refresh execution instruction signal is generated according to the wake-up signal and a standby mode instruction signal for instructing the standby.   A clock switching circuit that generates an internal clock signal having a frequency higher than that of an external clock signal and supplies the internal clock signal to the memory core when the standby mode instruction signal is activated; 11. The semiconductor integrated circuit device according to claim 10, wherein when the instruction signal is activated, the refresh operation is controlled using the internal clock signal as a refresh operation cycle defining signal. The power supply control circuit further includes a refresh clock generation circuit that generates a refresh clock signal that defines a unit cycle period in which the refresh is performed,
The semiconductor integrated circuit device according to claim 10, wherein the power management unit generates the refresh clock signal as an internal clock signal instead of an external clock signal and supplies the refresh clock signal to the memory core in the standby mode. The refresh time control circuit includes:
A first oscillation circuit having a first temperature characteristic and oscillating in response to activation of the refresh execution instruction signal;
Counting the output of the first oscillation circuit, maintaining the count-up signal in an active state until counting up, and maintaining at least the first oscillation circuit in the oscillation state during the activation period of the count-up signal A first counter to
A second oscillation circuit having a second temperature characteristic different from the first temperature characteristic and performing an oscillation operation during activation of a count-up signal from the first counter;
A second counter for counting an output signal of the second oscillation circuit during activation of a count-up signal from the first counter;
11. The semiconductor integrated circuit device according to claim 10, further comprising: a tuning code selection circuit that generates a selection code that defines the refresh time according to a count value of the second counter and supplies the selection code to the power management unit as the count value.   The refresh time control circuit further generates the standby mode instruction signal according to the low-consumption standby mode instruction signal and the count-up signal of the first counter in synchronization with the output of the tuning code selection signal, and the power management The semiconductor integrated circuit device according to claim 15, wherein the semiconductor integrated circuit device is supplied to a portion. The refresh execution instruction signal is maintained in an active state for a predetermined period,
The refresh time control circuit includes:
A first oscillation circuit having a first temperature characteristic, activated in response to activation of the refresh execution instruction signal, and oscillating during an active state of the indicator signal;
A first counter for counting the output of the first oscillation circuit;
A second temperature characteristic different from the first temperature characteristic that is activated in response to the activation of the refresh execution instruction signal and oscillates during an activation state of the refresh execution instruction signal; An oscillation circuit;
A second counter for counting the output of the second oscillation circuit;
A subtraction circuit for obtaining a difference value between count values of the first and second counters;
The semiconductor integrated circuit device according to claim 10, further comprising: a tuning code selection circuit that generates a selection code that defines the refresh time according to a difference value from the subtraction circuit and supplies the selection code to the power management unit as the count value. The refresh time control circuit includes:
A pulse generation circuit for generating a pulse signal having a predetermined pulse width in response to the activation of the refresh execution instruction signal;
A first oscillation circuit having a first temperature characteristic, activated in response to activation of the pulse signal, and oscillating during an activation period of the pulse signal;
A counter that is activated in response to the activation of the pulse signal, counts the output of the first oscillation circuit, and outputs the count value;
The semiconductor integrated circuit device according to claim 10, further comprising: a tuning code selection circuit that generates a selection code that defines the refresh time according to a count value of the counter and supplies the selection code to the power management control unit as the count value.   The power management unit further includes a register circuit that stores a plurality of refresh time designation data and selects the refresh time designation data from the plurality of refresh data according to a count value from the refresh time control circuit, from the register circuit 11. The semiconductor integrated circuit device according to claim 10, wherein a deactivation period of the wake-up signal and the refresh instruction signal is defined by the selected refresh time designation data. The refresh execution instruction signal is a low-consumption standby mode instruction signal that specifies the standby mode,
11. The semiconductor integrated circuit device according to claim 10, wherein the refresh time control circuit generates the standby instruction signal in parallel with the output of the count value in accordance with the low power consumption standby mode instruction signal and supplies the standby instruction signal to the power management unit.

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