TWM599462U - Memory operation ability prediction structure - Google Patents

Abstract

A prediction structure for memory operation capability, which is installed on a motherboard, includes several memory modules to be tested, and reads in a basic input/output system (BIOS) with memory margin test function How to test each memory module under test, a switch module connecting the input module and each memory module under test, a measurement module connected to the switch module, and a connection to the quantity The processing module of the test module. In this way, by quickly changing the BIOS frequency and the delay of the read and write sequence, the motherboard test method of this creation can measure the accurate voltage and current values, and it is close to the practical dynamic random access memory (dynamic random access memory). Random access memory (DRAM) integrated circuit (integrated circuit, IC) chips are used together, and the operating range of each single DRAM IC chip can be measured in the operation mode, so as to predict the size of each DRAM IC chip. Operation ability, which can effectively carry out operation ability test under various conditions, and improve the accuracy of classification.

Description

Memory operation ability prediction structure

This creative department is about a predictive structure of memory operation capabilities, especially involving a The motherboard test method that can measure accurate voltage and current values, especially by quickly changing the basic input/output system (Basic Input/Output System, BIOS) frequency and the delay of reading and writing sequence, can measure each The operating range of a single dynamic random access memory (DRAM) integrated circuit (IC) chip, so that the operating capability of each DRAM IC chip can be predicted, and various conditions can be effectively performed Under the operation ability test, improve the accurate value of classification.

In the manufacturing process of memory circuits and devices, such as DRAM, it is necessary to test the Memory circuit or device. Usually, automatic test equipment (ATE) coupled to the memory circuit or device (ie, device under test (DUT)) is used to complete this test. The ATE generates certain predetermined test signals and transmits them to the DUT and the response signals are received from the DUT and the DUT is evaluated based on the responses.

At present, ATE itself already provides accurate voltage, meter and timing control, based on This is a classification of automated testing. However, because the test equipment like ATE is very expensive, the high test cost weakens the price competitiveness; moreover, the operation ability of each single IC obtained from the test results is not tested in the operation mode, which is not suitable for actual use. The demand.

In addition, in addition to ATE, the conventional technologies are relatively cheap to use and are practically The motherboard in operation mode is used to test multiple ICs together. This method is closer to the way that ICs are actually used to operate applications, so the motherboard is the testing method that most people choose to use; however, this method is the most criticized shortcoming Because the voltage is not accurate enough and the current cannot be measured, it is impossible to know which of the many ICs consumes more power. In terms of timing control, only the frequency can be operated and cannot be tested. Therefore, although the motherboard is a test performed in the actual operating mode, the classification is not accurate enough.

In view of this, although the ATE method is already a standard in the field of memory testing However, the cost of the test device is still very high, and each IC is not tested in the operating mode, and although the motherboard is tested in the operating mode, the classification is not accurate enough. Therefore, ordinary users cannot meet the needs of users in actual use.

The main purpose of this creation is to overcome the above-mentioned problems encountered by learning skills and Provides a way to quickly change the BIOS frequency and CL, so that the motherboard test method of this creation can measure the accurate voltage and current values, and it is close to the practical method of using multiple DRAM IC chips together. It can measure each The operating range of a single DRAM IC chip can be used to predict the operating capability of each DRAM IC chip, thereby effectively performing operating capability tests under various conditions, and improving the memory operating capability prediction structure for classification accuracy.

In order to achieve the above purpose, this creation is a prediction structure of memory operation ability, Installed on a motherboard, it includes: a number of memory modules to be tested; an input module for reading in and reading in the system the basic output with memory margin test function how to test each memory module to be tested , And the memory margin test is a memory test mode under a specific timing operation mode; a switching module connects the input module and each memory module to be tested for each memory module to be tested The module switches the measurement mode according to one of the measured voltage or the measured current, so that each memory module under test performs the memory margin test; a measurement module is connected to the switching module, and the measurement module The group includes a voltage measurement unit and a current measurement unit, which are used to measure a memory characteristic of each memory module under test in a specific sequence of operation mode, including the ability to switch to the voltage measurement mode A power supply voltage of each memory module under test is measured through the voltage measurement unit, and the current flow through each memory under test can be measured by the current measurement unit when switching to the current measurement mode A current of a module, where the memory characteristics include voltage information and current information measured in a specific timing operation mode; and a processing module connected to the measurement module for reading the measurement module The group measures a memory characteristic of each memory module under test in a specific time sequence of operation mode, and combines the memory margin test with the voltage and current measurement to utilize each memory module under test The operable interval is to record the current operable interval range of each memory module under test through different BIOS frequency settings and different CLs, so as to quickly filter and classify each memory module under test. In the operation mode of a specific time sequence, a single accurate operation can be obtained to obtain the accurate value of the classification interval of each memory module under test, so as to predict the operation capability of each memory module under test.

In the above-mentioned embodiment of this creation, each memory module under test can be a DRA IC Wafer.

In the above-mentioned embodiment of this creation, the processing module can be a central processing unit (Central processing unit, CPU).

In the foregoing embodiment of this creation, the memory margin test is performed at a specific timing 3200 Memory test mode in the operating mode of MHz, 3600 MHz or 4000 MHz.

In the above-mentioned embodiment of this creation, the voltage measurement unit measures each of the memory to be tested The power supply voltage of the body module ranges from small to large, and the current measurement unit measures the flow through each of the records to be tested The memory module has a current from small to large.

In the foregoing embodiment of the present creation, the processing module further includes a storage unit for Record the current operational range of each memory module to be tested in the storage unit.

Please refer to "Picture 1", which is a block diagram of this creation. as the picture shows: This creation is a prediction structure of memory operation capability, which is installed on a motherboard 100 and includes several memory modules under test (device under test, DUT) 1, an input module 2, and a switch module 3. , A measurement module 4, and a processing module 5.

Each memory module 1 under test mentioned above can be a dynamic random access memory Body (dynamic random access memory, DRAM) integrated circuit (IC) chips are DRAM IC chip 1 to DRAM IC chip N.

The input module 2 is used to input the basic input and output with memory margin test function into the system The BIOS (Basic Input/Output System, BIOS) reads how to test each memory module 1 to be tested, and the memory margin test is a memory test mode under a specific timing operation mode.

The switch module 3 is connected to the input module 2 and each memory module under test 1. For each memory module 1 under test to switch the measurement mode according to one of the measured voltage or the measured current, so that each memory module 1 under test performs the memory margin test.

The measurement module 4 is connected to the switch module 3, which includes a voltage measurement unit 41 And a current measurement unit 42 for measuring a memory characteristic of each memory module 1 under test in a specific timing operation mode, including the voltage measurement by switching to the voltage measurement mode The unit 41 measures a power supply voltage of each memory module under test 1, and can measure the current flowing through each memory module under test through the current measurement unit 42 when switching to the current measurement mode 1. A current, where the memory characteristics include voltage information and current information measured in a specific time sequence of operation mode.

The processing module 5 is connected to the measurement module 4, which can be a central processing unit (Central processing unit, CPU), used to read the measurement module 4 in a specific timing operation mode to measure a memory characteristic of each memory module 1 under test, and pass the memory margin test and voltage Combined with current measurement, the operating range of each memory module 1 under test is recorded through different BIOS frequency settings and different read and write timing delays. The range of current operable ranges can be quickly screened and classified, so that each memory module 1 under test can be operated accurately and individually in a specific timing operation mode, and each memory module 1 under test can be obtained. The precise value of the classification interval is used to predict the operation capability of each memory module 1 under test. If so, a new prediction structure of memory operation capability is constructed by the above disclosed device.

In a specific embodiment, the memory margin test mentioned in this creation is performed at a specific timing. For example: memory test mode in 3200 MHz, 3600 MHz or 4000 MHz operation mode. In actual use, a measurement module 4 for detecting the memory characteristics of each memory module 1 under test can be provided in front of each memory module 1 under test, which includes a voltage measurement unit 41 And the current measuring unit 42 measures the voltage information and current information of each memory module 1 under test, including the voltage measurement unit 41 measuring each memory module 1 under test from small to large A power supply voltage, and the current measuring unit 42 measures the current flowing through each memory module 1 under test from small to large. Moreover, each measurement module 4 is directly connected to the processing module 5, so that the processing module 5 can know the memory characteristics of each memory module 11 under test; for example, when the timing is set by the BIOS In the 4000 MHz operation mode, the measurement module 4 detects whether each memory module 1 under test can read and write the voltage and voltage of each memory module 1 under test at this timing during the test. Current information, if the memory module under test 1 can be successfully read and written, it means that it can pass the test in the 4000 MHz operation mode. Therefore, the memory module 1 under test that successfully reads and writes can know its operating range at 4000 MHz. In this way, the voltage value and current value in each operation mode of a specific time sequence can be known. Then the processing module 5 records the remaining margin of each memory module 1 under test, that is, writes the operating range of each memory module 1 under test into a storage unit 51 for recording .

This creation uses some specific parameters in the operation (for example: reference voltage (VREF)) It can be measured and compared. DRAM IC chips can be classified by quickly changing the BIOS frequency and CL settings. The operating range of each DRAM IC chip can be determined through different frequency settings and different read/write timing delays. Know the operating range of each DRAM IC chip at present. Through such fast screening, a fast classification can be achieved, so that each single DRAM IC chip can be accurately operated under the operation mode to find its classification range. The precise value of, which can predict the operating ability of each DRAM IC chip, and in practice, each DRAM IC chip can have a higher operating efficiency when it is running. In this way, by quickly changing the BIOS frequency and CL, the motherboard test method of this creation can measure the accurate voltage and current values, and it is close to the practical method of using multiple DRAM IC chips together, which can be measured. The operating range of each single DRAM IC chip can effectively test the operating ability under various conditions and improve the accuracy of classification.

In summary, this creation is a predictive structure of memory operation capability, which can effectively change Make good use of the various shortcomings by quickly changing the BIOS frequency and read/write timing The delay of this creation allows the motherboard testing method of this creation to measure accurate voltage and current values, and it is close to the practical method of using multiple dynamic random access memory (DRAM) integrated circuit (IC) chips together. , It can measure the operating range of each single DRAM IC chip, so that the operating ability of each DRAM IC chip can be predicted. Therefore, the operating ability test under various conditions can be effectively carried out, and the accurate value of classification can be improved. The creation of this creation can be more advanced, more practical, and more in line with the needs of users. It has indeed met the requirements of a new patent application, and a patent application is filed in accordance with the law.

However, the above are only the preferred embodiments of this creation, and should not be limited to this The scope of implementation of this creation is determined; therefore, everything made in accordance with the scope of the patent application for this creation and the content of the new specification The simple equivalent changes and modifications should still fall within the scope of this creation patent.

100: Motherboard 1: Memory module to be tested 2: Input module 3: Switch module 4: Measurement module 41: Voltage measurement unit 42: Current measurement unit 5: Processing module 51: Storage unit

Figure 1 is a block diagram of this creation.

100: Motherboard

1: Memory module to be tested

2: Input module

3: Switch module

4: Measurement module

41: Voltage measurement unit

42: Current measurement unit

5: Processing module

51: storage unit

Claims (6)

A prediction structure for memory operation capability is installed on a motherboard and includes: Several memory modules under test (device under test, DUT); An input module for reading the basic input/output system (BIOS) with memory margin test function into how to test each memory module under test, and the memory margin test is performed at a specific timing The memory test mode under the operating mode; A switching module is connected to the input module and each memory module to be tested, and is used to switch the measurement mode for each memory module to be tested according to one of the measured voltage or the measured current, so that Performing the memory margin test for each memory module to be tested; A measurement module connected to the switching module. The measurement module includes a voltage measurement unit and a current measurement unit for measuring each memory module under test in a specific timing operation mode A memory characteristic includes the ability to measure a power supply voltage of each memory module under test through the voltage measurement unit when switching to the voltage measurement mode, and the ability to measure the power supply voltage of each memory module under test when switching to the measurement current mode The current measuring unit measures a current flowing through each of the memory modules to be tested, wherein the memory characteristics include voltage information and current information measured in an operation mode with a specific time sequence; and A processing module connected to the measurement module for reading the measurement module to measure a memory characteristic of each memory module under test in a specific timing operation mode, and pass the memory margin test Combined with voltage and current measurement, each memory module under test can be used to record each memory module under test through different BIOS frequency settings and different read/write timing delays. The range of current operable intervals can be quickly screened and classified, so that each memory module under test can be operated accurately and individually in a specific timing operation mode, and the classification interval of each memory module under test can be obtained The precise value of is used to predict the operating capability of each memory module under test. According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which Each of the memory modules under test can be a dynamic random access memory (DRAM) integrated circuit (IC) chip. According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which The processing module can be a central processing unit (CPU). According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which , The memory margin test is a memory test mode under the operation mode of 3200 MHz, 3600 MHz or 4000 MHz at a specific timing. According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which , The voltage measurement unit measures the power supply voltage of each memory module under test from small to large, and the current measurement unit measures the flow through each memory module under test from small to large One current. According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which The processing module further includes a storage unit for recording the currently operable range of each memory module to be tested into the storage unit.

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