TWM599462U - Memory operation ability prediction structure - Google Patents

Memory operation ability prediction structure Download PDF

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TWM599462U
TWM599462U TW109202519U TW109202519U TWM599462U TW M599462 U TWM599462 U TW M599462U TW 109202519 U TW109202519 U TW 109202519U TW 109202519 U TW109202519 U TW 109202519U TW M599462 U TWM599462 U TW M599462U
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memory
module
test
under test
memory module
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林正隆
梁萬棟
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森富科技股份有限公司
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Abstract

一種記憶體操作能力預測結構,係安裝於一主機板上,其包括數個待測記憶體模組、一將具有內存餘裕測試功能的基本輸出入系統(Basic Input/Output System,BIOS)讀入如何測試每一該待測記憶體模組、一連接該輸入模組與每一該待測記憶體模組之切換模組、一連接該切換模組之量測模組、以及一連接該量測模組之處理模組。藉此,通過快速改變BIOS頻率與讀寫時序的延遲,使本創作的主機板測試方式可以量測到精準的電壓值與電流值,並且是接近實務上多顆動態隨機存取記憶體(dynamic random access memory, DRAM)積體電路(integrated circuit, IC)晶片一起運用的方式,可在操作模式下量測出每一單顆DRAM IC晶片的操作區間範圍,從而可以預測每一DRAM IC晶片之操作能力,進而能有效地進行各種條件下的操作能力測試,提升分類的精準值 。A prediction structure for memory operation capability, which is installed on a motherboard, includes several memory modules to be tested, and reads in a basic input/output system (BIOS) with memory margin test function How to test each memory module under test, a switch module connecting the input module and each memory module under test, a measurement module connected to the switch module, and a connection to the quantity The processing module of the test module. In this way, by quickly changing the BIOS frequency and the delay of the read and write sequence, the motherboard test method of this creation can measure the accurate voltage and current values, and it is close to the practical dynamic random access memory (dynamic random access memory). Random access memory (DRAM) integrated circuit (integrated circuit, IC) chips are used together, and the operating range of each single DRAM IC chip can be measured in the operation mode, so as to predict the size of each DRAM IC chip. Operation ability, which can effectively carry out operation ability test under various conditions, and improve the accuracy of classification.

Description

記憶體操作能力預測結構Memory operation ability prediction structure

本創作係有關於一種記憶體操作能力預測結構,尤指涉及一種 可量測到精準的電壓值與電流值的主機板測試方式,特別係指通過快速改變基本輸出入系統(Basic Input/Output System,BIOS)頻率與讀寫時序的延遲,可量測出每一單顆動態隨機存取記憶體(dynamic random access memory, DRAM)積體電路(integrated circuit, IC)晶片的操作區間範圍,從而可以預測每一DRAM IC晶片之操作能力,進而能有效地進行各種條件下的操作能力測試,提升分類的精準值者。 This creative department is about a predictive structure of memory operation capabilities, especially involving a The motherboard test method that can measure accurate voltage and current values, especially by quickly changing the basic input/output system (Basic Input/Output System, BIOS) frequency and the delay of reading and writing sequence, can measure each The operating range of a single dynamic random access memory (DRAM) integrated circuit (IC) chip, so that the operating capability of each DRAM IC chip can be predicted, and various conditions can be effectively performed Under the operation ability test, improve the accurate value of classification.

在記憶體電路及裝置之製造過程中,如DRAM,有必要測試該 記憶體電路或裝置。通常使用耦接至該記憶體電路或裝置(亦即,被測裝置(device under test, DUT))之自動測試設備(automatic test equipment, ATE)來完成此測試。由該ATE產生某些預定測試信號並將其傳輸至該DUT且該自DUT接收回應信號且基於該等回應評估該DUT。 In the manufacturing process of memory circuits and devices, such as DRAM, it is necessary to test the Memory circuit or device. Usually, automatic test equipment (ATE) coupled to the memory circuit or device (ie, device under test (DUT)) is used to complete this test. The ATE generates certain predetermined test signals and transmits them to the DUT and the response signals are received from the DUT and the DUT is evaluated based on the responses.

目前ATE本身就已經有提供精準的電壓、電表與時序控制,基 本上是自動化測試的分類。然而,因為像ATE的測試設備很昂貴,高測試成本削弱了價格競爭力;而且,測試結果所得的每一顆單顆IC的操作能力都不是在操作的模式下進行測試,較無法符合實際使用之需求。 At present, ATE itself already provides accurate voltage, meter and timing control, based on This is a classification of automated testing. However, because the test equipment like ATE is very expensive, the high test cost weakens the price competitiveness; moreover, the operation ability of each single IC obtained from the test results is not tested in the operation mode, which is not suitable for actual use. The demand.

另外,習知的技術除了ATE之外,還有使用相對便宜且在實際 操作模式下的主機板來進行多顆IC一起測試,此方式比較接近實際上IC拿來操作應用的方式,所以主機板是較多人選擇使用的測試方法;然而,此方法最為人詬病的缺點在於其電壓並不夠準確、電流無法量測,從而無法得知眾多IC中的哪一顆IC耗電量比較大,而時序控制方面又僅有頻率能操作與不能操作的測試。因此主機板雖是演練在實際操作模式下所進行的測試,但其分類並不夠精準。 In addition, in addition to ATE, the conventional technologies are relatively cheap to use and are practically The motherboard in operation mode is used to test multiple ICs together. This method is closer to the way that ICs are actually used to operate applications, so the motherboard is the testing method that most people choose to use; however, this method is the most criticized shortcoming Because the voltage is not accurate enough and the current cannot be measured, it is impossible to know which of the many ICs consumes more power. In terms of timing control, only the frequency can be operated and cannot be tested. Therefore, although the motherboard is a test performed in the actual operating mode, the classification is not accurate enough.

鑑此,儘管ATE這個方法在記憶體測試的領域已經是一種標準 做法,但其測試裝置的成本依舊很高,並且每一顆IC都不是在操作的模式下進行測試,而主機板雖是在操作模式下測試但分類又不夠精準。故,一般習用者係無法符合使用者於實際使用時之所需。 In view of this, although the ATE method is already a standard in the field of memory testing However, the cost of the test device is still very high, and each IC is not tested in the operating mode, and although the motherboard is tested in the operating mode, the classification is not accurate enough. Therefore, ordinary users cannot meet the needs of users in actual use.

本創作之主要目的係在於,克服習知技藝所遭遇之上述問題並 提供一種通過快速改變BIOS頻率與CL,使本創作的主機板測試方式可以量測到精準的電壓值與電流值,並且是接近實務上多顆DRAM IC晶片一起運用的方式,可量測出每一單顆DRAM IC晶片的操作區間範圍,從而可以預測每一DRAM IC晶片之操作能力,進而能有效地進行各種條件下的操作能力測試,提升分類精準值之記憶體操作能力預測結構。 The main purpose of this creation is to overcome the above-mentioned problems encountered by learning skills and Provides a way to quickly change the BIOS frequency and CL, so that the motherboard test method of this creation can measure the accurate voltage and current values, and it is close to the practical method of using multiple DRAM IC chips together. It can measure each The operating range of a single DRAM IC chip can be used to predict the operating capability of each DRAM IC chip, thereby effectively performing operating capability tests under various conditions, and improving the memory operating capability prediction structure for classification accuracy.

為達以上之目的,本創作係一種記憶體操作能力預測結構,係 安裝於一主機板上,其包括:數個待測記憶體模組;一輸入模組,用以將具有內存餘裕測試功能的基本輸出入系統讀入如何測試每一該待測記憶體模組,而該內存餘裕測試係在特定時序的操作模式下的內存測試模式;一切換模組,連接該輸入模組與每一該待測記憶體模組,用以對每一該待測記憶體模組依照量測電壓或量測電流之一而切換量測模式,使每一該待測記憶體模組進行該內存餘裕測試;一量測模組,連接該切換模組,該量測模組包括一電壓量測單元及一電流量測單元,用以在特定時序的操作模式下量測每一該待測記憶體模組之一記憶體特性,包括在切換於量測電壓模式下可經由該電壓量測單元量測每一該待測記憶體模組之一電力供應電壓,而在切換於量測電流模式下可經由該電流量測單元量測流經每一該待測記憶體模組之一電流,其中該記憶體特性包括在特定時序的操作模式下量測所得的電壓資訊及電流資訊;以及一處理模組,連接該量測模組,用以讀取該量測模組在特定時序的操作模式下量測每一該待測記憶體模組之一記憶體特性,通過該內存餘裕測試與電壓及電流量測結合在一起,利用每一該待測記憶體模組可操作的區間係透過不同的BIOS頻率設定、不同的CL,記錄每一該待測記憶體模組當前可操作的區間範圍,藉此快速篩選、分類,使每一該待測記憶體模組在特定時序的操作模式下可以單顆精準的操作,獲得每一該待測記憶體模組分類區間的精準值,俾以預測(prediction)每一該待測記憶體模組之操作能力。 In order to achieve the above purpose, this creation is a prediction structure of memory operation ability, Installed on a motherboard, it includes: a number of memory modules to be tested; an input module for reading in and reading in the system the basic output with memory margin test function how to test each memory module to be tested , And the memory margin test is a memory test mode under a specific timing operation mode; a switching module connects the input module and each memory module to be tested for each memory module to be tested The module switches the measurement mode according to one of the measured voltage or the measured current, so that each memory module under test performs the memory margin test; a measurement module is connected to the switching module, and the measurement module The group includes a voltage measurement unit and a current measurement unit, which are used to measure a memory characteristic of each memory module under test in a specific sequence of operation mode, including the ability to switch to the voltage measurement mode A power supply voltage of each memory module under test is measured through the voltage measurement unit, and the current flow through each memory under test can be measured by the current measurement unit when switching to the current measurement mode A current of a module, where the memory characteristics include voltage information and current information measured in a specific timing operation mode; and a processing module connected to the measurement module for reading the measurement module The group measures a memory characteristic of each memory module under test in a specific time sequence of operation mode, and combines the memory margin test with the voltage and current measurement to utilize each memory module under test The operable interval is to record the current operable interval range of each memory module under test through different BIOS frequency settings and different CLs, so as to quickly filter and classify each memory module under test. In the operation mode of a specific time sequence, a single accurate operation can be obtained to obtain the accurate value of the classification interval of each memory module under test, so as to predict the operation capability of each memory module under test.

於本創作上述實施例中,每一該待測記憶體模組可係一DRA IC 晶片。 In the above-mentioned embodiment of this creation, each memory module under test can be a DRA IC Wafer.

於本創作上述實施例中,該處理模組可係一中央處理單元 (central processing unit, CPU)。 In the above-mentioned embodiment of this creation, the processing module can be a central processing unit (Central processing unit, CPU).

於本創作上述實施例中,該內存餘裕測試係在特定時序3200 MHz、3600 MHz或4000 MHz的操作模式下的內存測試模式。 In the foregoing embodiment of this creation, the memory margin test is performed at a specific timing 3200 Memory test mode in the operating mode of MHz, 3600 MHz or 4000 MHz.

於本創作上述實施例中,該電壓量測單元量測每一該待測記憶 體模組由小到大之一電力供應電壓,及該電流量測單元量測流經每一該待測記 憶體模組由小到大之一電流。 In the above-mentioned embodiment of this creation, the voltage measurement unit measures each of the memory to be tested The power supply voltage of the body module ranges from small to large, and the current measurement unit measures the flow through each of the records to be tested The memory module has a current from small to large.

於本創作上述實施例中,該處理模組更包括一儲存單元,用以 將每一該待測記憶體模組當前可操作的區間範圍記錄至該儲存單元中。 In the foregoing embodiment of the present creation, the processing module further includes a storage unit for Record the current operational range of each memory module to be tested in the storage unit.

請參閱『第1圖』所示,係本創作之方塊示意圖。如圖所示: 本創作係一種記憶體操作能力預測結構,係安裝於一主機板100上,其包括數個待測記憶體模組(device under test, DUT)1、一輸入模組2、一切換模組3、一量測模組4、以及一處理模組5所構成。 Please refer to "Picture 1", which is a block diagram of this creation. as the picture shows: This creation is a prediction structure of memory operation capability, which is installed on a motherboard 100 and includes several memory modules under test (device under test, DUT) 1, an input module 2, and a switch module 3. , A measurement module 4, and a processing module 5.

上述所提每一該待測記憶體模組1可係一動態隨機存取記憶 體(dynamic random access memory, DRAM)積體電路(integrated circuit, IC)晶片,為DRAM IC晶片 1至DRAM IC晶片N。 Each memory module 1 under test mentioned above can be a dynamic random access memory Body (dynamic random access memory, DRAM) integrated circuit (IC) chips are DRAM IC chip 1 to DRAM IC chip N.

該輸入模組2用以將具有內存餘裕測試功能的基本輸出入系 統(Basic Input/Output System,BIOS)讀入如何測試每一該待測記憶體模組1中,而該內存餘裕測試係在特定時序的操作模式下的內存測試模式。 The input module 2 is used to input the basic input and output with memory margin test function into the system The BIOS (Basic Input/Output System, BIOS) reads how to test each memory module 1 to be tested, and the memory margin test is a memory test mode under a specific timing operation mode.

該切換模組3連接該輸入模組2與每一該待測記憶體模組 1,用以對每一該待測記憶體模組1依照量測電壓或量測電流之一而切換量測模式,使每一該待測記憶體模組1進行該內存餘裕測試。 The switch module 3 is connected to the input module 2 and each memory module under test 1. For each memory module 1 under test to switch the measurement mode according to one of the measured voltage or the measured current, so that each memory module 1 under test performs the memory margin test.

該量測模組4連接該切換模組3,其包括一電壓量測單元41 及一電流量測單元42,用以在特定時序的操作模式下量測每一該待測記憶體模組1之一記憶體特性,包括在切換於量測電壓模式下可經由該電壓量測單元41量測每一該待測記憶體模組1之一電力供應電壓,以及在切換於量測電流模式下可經由該電流量測單元42量測流經每一該待測記憶體模組1之一電流,其中該記憶體特性包括在特定時序的操作模式下量測所得的電壓資訊及電流資訊。 The measurement module 4 is connected to the switch module 3, which includes a voltage measurement unit 41 And a current measurement unit 42 for measuring a memory characteristic of each memory module 1 under test in a specific timing operation mode, including the voltage measurement by switching to the voltage measurement mode The unit 41 measures a power supply voltage of each memory module under test 1, and can measure the current flowing through each memory module under test through the current measurement unit 42 when switching to the current measurement mode 1. A current, where the memory characteristics include voltage information and current information measured in a specific time sequence of operation mode.

該處理模組5連接該量測模組4,其可係一中央處理單元 (central processing unit, CPU),用以讀取該量測模組4在特定時序的操作模式下量測每一該待測記憶體模組1之一記憶體特性,通過該內存餘裕測試與電壓及電流量測結合在一起,利用每一該待測記憶體模組1可操作的區間係透過不同的BIOS頻率設定、不同的讀寫時序的延遲,記錄每一該待測記憶體模組1當前可操作的區間範圍,藉此快速篩選、分類,使每一該待測記憶體模組1在特定時序的操作模式下可以單顆精準的操作,獲得每一該待測記憶體模組1分類區間的精準值,俾以預測(prediction)每一該待測記憶體模組1之操作能力。如是,藉由上述揭露之裝置構成一全新之記憶體操作能力預測結構。 The processing module 5 is connected to the measurement module 4, which can be a central processing unit (Central processing unit, CPU), used to read the measurement module 4 in a specific timing operation mode to measure a memory characteristic of each memory module 1 under test, and pass the memory margin test and voltage Combined with current measurement, the operating range of each memory module 1 under test is recorded through different BIOS frequency settings and different read and write timing delays. The range of current operable ranges can be quickly screened and classified, so that each memory module 1 under test can be operated accurately and individually in a specific timing operation mode, and each memory module 1 under test can be obtained. The precise value of the classification interval is used to predict the operation capability of each memory module 1 under test. If so, a new prediction structure of memory operation capability is constructed by the above disclosed device.

於一具體實施例中,本創作所提內存餘裕測試係在特定時序, 例如:在3200 MHz、3600 MHz或4000 MHz的操作模式下的內存測試模式。實際運用時,可在每一該待測記憶體模組1前方都設有一偵測每一該待測記憶體模組1記憶體特性之量測模組4,其包含以電壓量測單元41及電流量測單元42量測每一該待測記憶體模組1之電壓資訊及電流資訊,包括由該電壓量測單元41量測每一該待測記憶體模組1由小到大之一電力供應電壓,及該電流量測單元42量測流經每一該待測記憶體模組1由小到大之一電流。而且每一量測模組4都與處理模組5直接連接,使該處理模組5可得知每一該待測記憶體模組11之記憶體特性;舉例而言,當時序由BIOS設定在4000 MHz的操作模式下,測試時該量測模組4就在此時序下偵測每一該待測記憶體模組1是否能讀寫每一該待測記憶體模組1的電壓與電流資訊,若能成功讀寫的待測記憶體模組1即表示其在4000 MHz的操作模式下是可以通過測試。因此成功讀寫的待測記憶體模組1可以得知其在4000 MHz下的操作區間,依此方式,從而使各個特定時序的操作模式下的電壓值與電流值皆可得知。再由該處理模組5去記錄每一該待測記憶體模組1剩餘的餘裕量,亦即將每一該待測記憶體模組1的操作區間範圍寫入至一儲存單元51中作記錄。 In a specific embodiment, the memory margin test mentioned in this creation is performed at a specific timing. For example: memory test mode in 3200 MHz, 3600 MHz or 4000 MHz operation mode. In actual use, a measurement module 4 for detecting the memory characteristics of each memory module 1 under test can be provided in front of each memory module 1 under test, which includes a voltage measurement unit 41 And the current measuring unit 42 measures the voltage information and current information of each memory module 1 under test, including the voltage measurement unit 41 measuring each memory module 1 under test from small to large A power supply voltage, and the current measuring unit 42 measures the current flowing through each memory module 1 under test from small to large. Moreover, each measurement module 4 is directly connected to the processing module 5, so that the processing module 5 can know the memory characteristics of each memory module 11 under test; for example, when the timing is set by the BIOS In the 4000 MHz operation mode, the measurement module 4 detects whether each memory module 1 under test can read and write the voltage and voltage of each memory module 1 under test at this timing during the test. Current information, if the memory module under test 1 can be successfully read and written, it means that it can pass the test in the 4000 MHz operation mode. Therefore, the memory module 1 under test that successfully reads and writes can know its operating range at 4000 MHz. In this way, the voltage value and current value in each operation mode of a specific time sequence can be known. Then the processing module 5 records the remaining margin of each memory module 1 under test, that is, writes the operating range of each memory module 1 under test into a storage unit 51 for recording .

本創作透過操作中的一些特定的參數(例如:參考電壓(VREF)) 可被測量與比較,藉由快速改變BIOS頻率與CL設定,而把DRAM IC晶片分類出來,利用每顆DRAM IC晶片可操作的區間係透過不同的頻率設定、不同的讀寫時序的延遲,從而得知每一顆DRAM IC晶片目前可操作的區間範圍,透過如此快速的篩選,達成快速的分類,使每一單顆DRAM IC晶片在操作模式下可以單顆精準的操作,找出其分類區間的精準值,從而可以預測每一DRAM IC晶片之操作能力,進而讓實務上每一DRAM IC晶片在運行的時候可以有更高的操作效率。藉此,通過快速改變BIOS頻率與CL,使本創作的主機板測試方式可以量測到精準的電壓值與電流值,並且是接近實務上多顆DRAM IC晶片一起運用的方式,可量測出每一單顆DRAM IC晶片的操作區間範圍,從而能有效地進行各種條件下的操作能力測試,提升分類的精準值。 This creation uses some specific parameters in the operation (for example: reference voltage (VREF)) It can be measured and compared. DRAM IC chips can be classified by quickly changing the BIOS frequency and CL settings. The operating range of each DRAM IC chip can be determined through different frequency settings and different read/write timing delays. Know the operating range of each DRAM IC chip at present. Through such fast screening, a fast classification can be achieved, so that each single DRAM IC chip can be accurately operated under the operation mode to find its classification range. The precise value of, which can predict the operating ability of each DRAM IC chip, and in practice, each DRAM IC chip can have a higher operating efficiency when it is running. In this way, by quickly changing the BIOS frequency and CL, the motherboard test method of this creation can measure the accurate voltage and current values, and it is close to the practical method of using multiple DRAM IC chips together, which can be measured. The operating range of each single DRAM IC chip can effectively test the operating ability under various conditions and improve the accuracy of classification.

綜上所述,本創作係一種記憶體操作能力預測結構,可有效改 善習用之種種缺點,通過快速改變基本輸出入系統(BIOS)頻率與讀寫時序 的延遲,使本創作的主機板測試方式可以量測到精準的電壓值與電流值,並且是接近實務上多顆動態隨機存取記憶體(DRAM)積體電路(IC)晶片一起運用的方式,可量測出每一單顆DRAM IC晶片的操作區間範圍,從而可以預測每一DRAM IC晶片之操作能力,因而能有效地進行各種條件下的操作能力測試,提升分類的精準值,進而使本創作之產生能更進步、更實用、更符合使用者之所須,確已符合新型專利申請之要件,爰依法提出專利申請。 In summary, this creation is a predictive structure of memory operation capability, which can effectively change Make good use of the various shortcomings by quickly changing the BIOS frequency and read/write timing The delay of this creation allows the motherboard testing method of this creation to measure accurate voltage and current values, and it is close to the practical method of using multiple dynamic random access memory (DRAM) integrated circuit (IC) chips together. , It can measure the operating range of each single DRAM IC chip, so that the operating ability of each DRAM IC chip can be predicted. Therefore, the operating ability test under various conditions can be effectively carried out, and the accurate value of classification can be improved. The creation of this creation can be more advanced, more practical, and more in line with the needs of users. It has indeed met the requirements of a new patent application, and a patent application is filed in accordance with the law.

惟以上所述者,僅為本創作之較佳實施例而已,當不能以此限 定本創作實施之範圍;故,凡依本創作申請專利範圍及新型說明書內容所作 之簡單的等效變化與修飾,皆應仍屬本創作專利涵蓋之範圍內。 However, the above are only the preferred embodiments of this creation, and should not be limited to this The scope of implementation of this creation is determined; therefore, everything made in accordance with the scope of the patent application for this creation and the content of the new specification The simple equivalent changes and modifications should still fall within the scope of this creation patent.

100:主機板 1:待測記憶體模組 2:輸入模組 3:切換模組 4:量測模組 41:電壓量測單元 42:電流量測單元 5:處理模組 51:儲存單元 100: Motherboard 1: Memory module to be tested 2: Input module 3: Switch module 4: Measurement module 41: Voltage measurement unit 42: Current measurement unit 5: Processing module 51: Storage unit

第1圖,係本創作之方塊示意圖。Figure 1 is a block diagram of this creation.

100:主機板 100: Motherboard

1:待測記憶體模組 1: Memory module to be tested

2:輸入模組 2: Input module

3:切換模組 3: Switch module

4:量測模組 4: Measurement module

41:電壓量測單元 41: Voltage measurement unit

42:電流量測單元 42: Current measurement unit

5:處理模組 5: Processing module

51:儲存單元 51: storage unit

Claims (6)

一種記憶體操作能力預測結構,係安裝於一主機板上,其包括: 數個待測記憶體模組(device under test, DUT); 一輸入模組,用以將具有內存餘裕測試功能的基本輸出入系統(Basic Input/Output System,BIOS)讀入如何測試每一該待測記憶體模組,而該內存餘裕測試係在特定時序的操作模式下的內存測試模式; 一切換模組,連接該輸入模組與每一該待測記憶體模組,用以對每一該待測記憶體模組依照量測電壓或量測電流之一而切換量測模式,使每一該待測記憶體模組進行該內存餘裕測試; 一量測模組,連接該切換模組,該量測模組包括一電壓量測單元及一電流量測單元,用以在特定時序的操作模式下量測每一該待測記憶體模組之一記憶體特性,包括在切換於量測電壓模式下可經由該電壓量測單元量測每一該待測記憶體模組之一電力供應電壓,而在切換於量測電流模式下可經由該電流量測單元量測流經每一該待測記憶體模組之一電流,其中該記憶體特性包括在特定時序的操作模式下量測所得的電壓資訊及電流資訊;以及 一處理模組,連接該量測模組,用以讀取該量測模組在特定時序的操作模式下量測每一該待測記憶體模組之一記憶體特性,通過該內存餘裕測試與電壓及電流量測結合在一起,利用每一該待測記憶體模組可操作的區間係透過不同的BIOS頻率設定、不同的讀寫時序的延遲,記錄每一該待測記憶體模組當前可操作的區間範圍,藉此快速篩選、分類,使每一該待測記憶體模組在特定時序的操作模式下可以單顆精準的操作,獲得每一該待測記憶體模組分類區間的精準值,俾以預測(prediction)每一該待測記憶體模組之操作能力。 A prediction structure for memory operation capability is installed on a motherboard and includes: Several memory modules under test (device under test, DUT); An input module for reading the basic input/output system (BIOS) with memory margin test function into how to test each memory module under test, and the memory margin test is performed at a specific timing The memory test mode under the operating mode; A switching module is connected to the input module and each memory module to be tested, and is used to switch the measurement mode for each memory module to be tested according to one of the measured voltage or the measured current, so that Performing the memory margin test for each memory module to be tested; A measurement module connected to the switching module. The measurement module includes a voltage measurement unit and a current measurement unit for measuring each memory module under test in a specific timing operation mode A memory characteristic includes the ability to measure a power supply voltage of each memory module under test through the voltage measurement unit when switching to the voltage measurement mode, and the ability to measure the power supply voltage of each memory module under test when switching to the measurement current mode The current measuring unit measures a current flowing through each of the memory modules to be tested, wherein the memory characteristics include voltage information and current information measured in an operation mode with a specific time sequence; and A processing module connected to the measurement module for reading the measurement module to measure a memory characteristic of each memory module under test in a specific timing operation mode, and pass the memory margin test Combined with voltage and current measurement, each memory module under test can be used to record each memory module under test through different BIOS frequency settings and different read/write timing delays. The range of current operable intervals can be quickly screened and classified, so that each memory module under test can be operated accurately and individually in a specific timing operation mode, and the classification interval of each memory module under test can be obtained The precise value of is used to predict the operating capability of each memory module under test. 依申請專利範圍第1項所述之記憶體操作能力預測結構,其中 ,每一該待測記憶體模組可係一動態隨機存取記憶體(dynamic random access memory, DRAM)積體電路(integrated circuit, IC)晶片。 According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which Each of the memory modules under test can be a dynamic random access memory (DRAM) integrated circuit (IC) chip. 依申請專利範圍第1項所述之記憶體操作能力預測結構,其中 ,該處理模組可係一中央處理單元(central processing unit, CPU)。 According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which The processing module can be a central processing unit (CPU). 依申請專利範圍第1項所述之記憶體操作能力預測結構,其中 ,該內存餘裕測試係在特定時序3200 MHz、3600 MHz或4000 MHz的操作模式下的內存測試模式。 According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which , The memory margin test is a memory test mode under the operation mode of 3200 MHz, 3600 MHz or 4000 MHz at a specific timing. 依申請專利範圍第1項所述之記憶體操作能力預測結構,其中 ,該電壓量測單元量測每一該待測記憶體模組由小到大之一電力供應電壓,及該電流量測單元量測流經每一該待測記憶體模組由小到大之一電流。 According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which , The voltage measurement unit measures the power supply voltage of each memory module under test from small to large, and the current measurement unit measures the flow through each memory module under test from small to large One current. 依申請專利範圍第1項所述之記憶體操作能力預測結構,其中 ,該處理模組更包括一儲存單元,用以將每一該待測記憶體模組當前可操作的區間範圍記錄至該儲存單元中。 According to the prediction structure of memory operation capability described in item 1 of the scope of patent application, among which The processing module further includes a storage unit for recording the currently operable range of each memory module to be tested into the storage unit.
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