CN1472651A - Memory module testing and patching method and device - Google Patents
Memory module testing and patching method and device Download PDFInfo
- Publication number
- CN1472651A CN1472651A CNA021275890A CN02127589A CN1472651A CN 1472651 A CN1472651 A CN 1472651A CN A021275890 A CNA021275890 A CN A021275890A CN 02127589 A CN02127589 A CN 02127589A CN 1472651 A CN1472651 A CN 1472651A
- Authority
- CN
- China
- Prior art keywords
- memory
- patching
- testing
- memory modules
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention uses spare storage unit in internal memory to record funlted internal memory address when the module fault is detected and discovered. The electric fusing method is applied to block addressing path of faulted internal memory address and a spare address is used to replace it. It is not necessary to replace the faulted internal memory chip manually so the manpower and production cost can be saved effectively.
Description
Technical field
The invention relates to a kind of memory modules, and particularly relevant for a kind of memory module testing and patching method and device.
Background technology
In general PC now (the be called for short PC) system, mainly by motherboard, interface card, form with institute such as peripherals, and can the say so heart of computer system of motherboard wherein.On motherboard, except central processing unit (Central Processing Unit is arranged, be called for short CPU), internal memory control chip and can be for outside the slot of mounting interface card, still there are several can supply to install the memory module slot (memory module slot) of memory modules, it can be according to user's demand, the memory modules (memory module) of varying number is installed, and each memory modules then is made up of several memory chips.
General employed internal memory in PC, SDRAM (Synchronous dynamic random access memory) (Synchronous dynamic random access memory is arranged, be called for short SDRAM), with Double Data Rate DRAM (Dynamic Random Access Memory) (double data rate dynamic random accessmemory is called for short DDR DRAM).Wherein, SDRAM is the accessing operation that the rising edge of frame of reference clock pulse carries out data, and DDR DRAM then carries out the accessing operation of data for the rising edge of frame of reference clock pulse and falling edge, to reach double message transmission rate in system's clock pulse frequency.
The DDR DRAM memory modules that develops on the market is to use the memory module slot of the 184 pin position specifications that meet the JEDEC standard at present, the sdram memory module is then used the memory module slot of 168 pin positions, so the assembling of memory modules need cooperate the specification of slot to make, complete and need and just can use after tested.Known memory modules is made flow process as shown in Figure 1, from memory chip charging (step S110), assembling (step S120) then, test (step S130), as the test by then completing (step S150) but and shipment, but as when the judgement of S140 step has any memory address fault (fail), then need to the S160 step with manually the memory chip tip-off of fault is changed another good memory chip, then test again again.This kind practice has following shortcoming:
1. need the maintenance personal of cultivate professional, can be competent at this patch work, cause production cost to reduce.
2. production procedure is comparatively complicated, causes turnout to improve.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of memory module testing and patching method and device, it can block the memory address of fault automatically, and utilize the standby address of the spare memory cell of memory chip to replace, and need not change another good memory chip, not only can simplify production procedure, more can save the production cost of memory modules.
For reaching above-mentioned and other purpose, the invention provides a kind of memory module testing and patching method, be applicable to test and repair a memory modules, the memory address that it comprises the following steps: test memory module at first and writes down fault in the memory modules; Again the memory chip on the memory modules is set at test pattern; Then with the addressing path of the memory address that blocks fault, and choose the mode that a standby address replaces and repair; At last the memory chip on the memory modules is set at normal mode.
Wherein, block fault memory address the addressing path and to choose the step that a standby address replaces be to finish with electric fusing (Electrical fuse blow) method.And during the test memory module, be that each memory address to memory modules carries out that data write and the data read action, and confirm whether the data that read are correct.
The present invention provides a kind of memory module testing and patching device in addition, is applicable to test and repairs a memory modules, and this device comprises at least: the special-purpose board of Storage Media and memory test.Wherein, Storage Media is used for storing the testing and patching program of testing and patching memory modules; And the special-purpose board of memory test reaches and loads its testing and patching program from Storage Media in order to the plant memory modules, to carry out the testing and patching program of memory modules.Wherein and with above-mentioned memory module testing and patching method carry out its testing and patching program.
In the preferred embodiment of the present invention, but its Storage Media be floppy disk and disk or be the Storage Media of stored routines such as similar hard disk drive or CD-ROM drive, and can more comprise a display, to show its testing and patching result.
By in the above-mentioned explanation as can be known, because memory module testing and patching method provided by the invention and device are when finding the memory modules fault, it is the addressing path of blocking the memory address of fault with electric blowout method, and choose a standby address and replace, and no longer change the memory chip of fault with manual type, so can effectively save the manpower and the cost of testing and patching, and improve the turnout of memory modules.
Description of drawings
Fig. 1 is that a kind of known memory modules is made process flow diagram;
Fig. 2 is that the memory modules of the preferred embodiment according to the present invention is made process flow diagram; And
Fig. 3 is the memory module testing and patching device synoptic diagram of the preferred embodiment according to the present invention.
S110～S275: flow process is made, tests and repaired to memory modules
S300: memory module testing and patching device
S310: Storage Media
S320: the special-purpose board of memory test
S330: memory module slot
S340: display
Embodiment
Please refer to shown in Figure 2ly, it is to make process flow diagram according to the memory modules of a preferred embodiment of the present invention.Show its making flow process among the figure from memory chip charging (step S210), but assembling (step S220) then, test (step S230) are as can then having finished making (step S250) and shipment by test smoothly.But as when the judgement of S240 step has any memory address fault (fail), in order to save labour turnover and the element replacement cost, be to give up originally with artificial memory chip tip-off with fault, change the method for repairing and mending of another good memory chip again, replace and change with standby address with the spare memory cell (memory cell) of the memory chip in the memory modules, this is that memory modules of the present invention is repaired step, will illustrate as after.
At first, the memory address of test failure must be write down (step S260), used during for follow-up repairing memory modules.The method that behind the designed memory address that blocks fault of the memory chip on the memory modules, replaces with a standby address again, for example be to block the memory address of fault and the method that replaces with a standby address with electric fusing (Electrical fuse blow) method, be to be about to memory chip earlier when being set at the pattern of test pattern or other abnormal operation, then memory chip is set at test pattern (step S265), utilization for example is that electric blowout method blocks the memory address of fault and replaces (step S270) with a standby address then, this moment is because of finishing the repairing of the memory address of fault in the memory modules, so again memory chip is set the normal mode (step S275) of getting back to normal running, is beneficial to test again or use.
Please refer to shown in Figure 3ly, it is the memory module testing and patching device synoptic diagram of the preferred embodiment according to the present invention.Show among the figure that this memory module testing and patching device 300 comprises at least: the special-purpose board 320 of Storage Media 310 and memory test.Wherein, Storage Media 310 is used for storing the testing and patching program of testing and patching memory modules; And have the memory module slot 330 that quantity does not wait on the special-purpose board 320 of memory test, the pin number amount of this memory module slot 330 needs to conform to the pin position of the memory modules of desiring testing and patching with specification, desire the memory modules of testing and patching so that plant, certainly, those skilled in the art should know that it also can be a computer motherboard as shown in FIG..When test is finished and is activated in the memory modules plant, but the special-purpose board 320 of memory test will be from for example being floppy disk and disk or being Storage Media 310 its testing and patching programs of loading of stored routines such as similar hard disk drive or CD-ROM drive, to begin to carry out the testing and patching program of memory modules.Testing and patching program wherein is the memory module testing and patching step among above-mentioned Fig. 2, no longer repeats herein.
In addition, carry out process and result in order clearly to understand with the testing and patching program of the whole memory modules of control, this memory module testing and patching device 300 more comprises a display 340, to carry out process and result's auxiliary demonstration as the testing and patching program of whole memory modules.
In sum, because a kind of memory module testing and patching method of the present invention and device are when the test memory module, as find the memory modules fault, need not be with the memory chip tip-off, change again another good memory chip, so it has the following advantages at least:
1. can reduce required specialized maintenance personnel's number, and save it and cultivate cost.
2. can simplify production procedure, and improve output.
3. because do not need to change another good memory bar, so can effectively reduce memory chip Consumed cost.
Claims (9)
1. a memory module testing and patching method is applicable to test and repairs a memory modules, it is characterized in that this method comprises the following steps:
Test this memory modules;
Write down this memory address of fault in this memory modules; And
Block the addressing path of this memory address of fault, and choose a standby address and replace.
2. memory module testing and patching method as claimed in claim 1 is characterized in that, the addressing path of blocking this memory address of fault is to finish with electric blowout method.
3. memory module testing and patching method as claimed in claim 1 is characterized in that, tests this memory modules and is each memory address to this memory modules and carry out that data write and the data read action, and confirm whether the data that read are correct.
4. memory module testing and patching method as claimed in claim 1 is characterized in that, more comprises the step that the memory chip on this memory modules is set at test pattern.
5. a memory module testing and patching device is applicable to test and repairs a memory modules, it is characterized in that this device comprises:
One Storage Media, a testing and patching program of this storing media stores one this memory modules of testing and patching; And
The special-purpose board of one memory test, this special use board this memory modules of planting, and load this testing and patching program from this Storage Media, and carry out a testing and patching program of this memory modules;
Wherein this testing and patching program comprises the following steps:
Test this memory modules;
Write down this memory address of fault in this memory modules;
Memory chip on this memory modules is set at test pattern;
Block the addressing path of this memory address of fault, and choose a standby address and replace; And
Memory chip on this memory modules is set at normal mode.
6. memory module testing and patching device as claimed in claim 5 is characterized in that, this Storage Media is a floppy disk and disk.
7. memory module testing and patching device as claimed in claim 5 is characterized in that, this Storage Media is a hard disk drive.
8. memory module testing and patching device as claimed in claim 5 is characterized in that, this Storage Media is a CD-ROM drive.
9. memory module testing and patching device as claimed in claim 5 is characterized in that, more comprises a display, to show its testing and patching result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021275890A CN1472651A (en) | 2002-08-01 | 2002-08-01 | Memory module testing and patching method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021275890A CN1472651A (en) | 2002-08-01 | 2002-08-01 | Memory module testing and patching method and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1472651A true CN1472651A (en) | 2004-02-04 |
Family
ID=34143561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021275890A Pending CN1472651A (en) | 2002-08-01 | 2002-08-01 | Memory module testing and patching method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1472651A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222025A (en) * | 2011-06-17 | 2011-10-19 | 华为数字技术有限公司 | Method and device for eliminating memory failure |
| CN110532124A (en) * | 2019-09-06 | 2019-12-03 | 西安易朴通讯技术有限公司 | Memory partition method and device |
| CN112397135A (en) * | 2020-11-06 | 2021-02-23 | 润昇系统测试(深圳)有限公司 | Testing and repairing device and testing and repairing method |
| CN113496758A (en) * | 2020-04-01 | 2021-10-12 | 森富科技股份有限公司 | Memory operation capability prediction method |
-
2002
- 2002-08-01 CN CNA021275890A patent/CN1472651A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222025A (en) * | 2011-06-17 | 2011-10-19 | 华为数字技术有限公司 | Method and device for eliminating memory failure |
| CN110532124A (en) * | 2019-09-06 | 2019-12-03 | 西安易朴通讯技术有限公司 | Memory partition method and device |
| CN113496758A (en) * | 2020-04-01 | 2021-10-12 | 森富科技股份有限公司 | Memory operation capability prediction method |
| CN113496758B (en) * | 2020-04-01 | 2024-06-18 | 森富科技股份有限公司 | Memory Operation Capability Prediction Method |
| CN112397135A (en) * | 2020-11-06 | 2021-02-23 | 润昇系统测试(深圳)有限公司 | Testing and repairing device and testing and repairing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6161177A (en) | Method for selecting, detecting and/or reprogramming system BIOS in a computer system | |
| EP2026356B1 (en) | Method for creating a memory defect map and optimizing performance using the memory defect map | |
| US8020053B2 (en) | On-line memory testing | |
| US20070174718A1 (en) | Generation and use of system level defect tables for main memory | |
| US20030041295A1 (en) | Method of defects recovery and status display of dram | |
| US7401270B2 (en) | Repair of semiconductor memory device via external command | |
| CN111338851B (en) | Method, device, computer equipment and storage medium for automatically repairing fault memory boot hPR | |
| US20210166777A1 (en) | Memory repair circuit, memory repair method, and memory module using memory repair circuit | |
| CN113366576A (en) | Retention self-test for power loss operations on memory systems | |
| CN111984487A (en) | Method and device for recording fault hardware position off-line | |
| US20150227461A1 (en) | Repairing a memory device | |
| CN110322921A (en) | A kind of terminal and electronic equipment | |
| CN1740992A (en) | The BIOS on-line rewriting method | |
| CN102255208A (en) | Riser card | |
| CN1472651A (en) | Memory module testing and patching method and device | |
| CN102324251A (en) | Signal wire in order to the program fail in the instruction memory | |
| CN102479124A (en) | Test method | |
| CN113851180A (en) | System for detecting SSD (solid State disk) standby power reliability, test fixture and SSD | |
| KR100825068B1 (en) | Built in self test and built in self repair system | |
| CN101187879B (en) | Electronic system and data processing method thereof | |
| US20030051193A1 (en) | Computer system with improved error detection | |
| CN115602242B (en) | Storage device and test method thereof | |
| CN109215724B (en) | Method and device for automatically detecting and repairing memory | |
| CN101441598B (en) | Data storage method | |
| CN116662042A (en) | Memory device, working method thereof, computer readable storage medium and equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |