JP2002343096A - Test system of semiconductor memory module and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test system in which various tests can be performed for many memory modules in conditions being close to actual use and of which a development cost and a manufacturing cost are lower. SOLUTION: A test system of a semiconductor memory module is provided with a personal computer 23 having a bus bridge IC delivering and receiving a signal directly to and from a reference memory module 200 and performing write-in and read-out of data, a signal extracting means 210 extracting input/ output signal between the bus bridge IC and the reference memory module 200 to the outside, a signal distributing means 40 distributing the input/output signals to a plurality of terminals, a test module control means 120 supplying an address signal and a write-in data signal in distributed signals to a memory module for test and comparing a read-out data signal in the distributed signals with a read-out data signal outputted from the memory module for test, and a data processing device 30 totalizing compared results by each comparing means of a plurality of test module control means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a test system for testing a semiconductor memory module such as a dual in-line memory module (Dual In-line Memory Module), and a technique that is useful when applied to a method for manufacturing a semiconductor memory module.

[0002]

2. Description of the Related Art Conventionally, as a test system related to a semiconductor memory, a general-purpose memory tester for performing various analyzes and tests on a packaged semiconductor memory, or a memory in which the semiconductor memory is mounted on a substrate. There was a module tester that checks the wiring connection and the like on mounting for modules.

[0003]

However, since the above-mentioned general-purpose memory tester is intended for a semiconductor memory in a packaging stage, it cannot be tested in terms of hardware or software under conditions close to actual use. There was a problem. For example, a test including a problem in mounting the memory module, a test for verifying compatibility with a peripheral circuit that accesses data to the memory, and a test for verifying an influence of a program process on the memory module cannot be performed. Therefore, even when a memory module is manufactured using a semiconductor memory that has passed the test of the general-purpose memory tester, there is a problem that a module that fails in a test under actual use conditions occurs.

In recent years, semiconductor memory modules have
For example, diversification is progressing in terms of its operation frequency, operation timings such as single rate and double rate, and presence / absence of various functions such as parity check. There is also a problem that it is not easy to make the test contents correspond to the development.

A general-purpose memory tester independently generates a test signal to be input to a semiconductor memory, and generates a wide range of test signals, and responds to various test items and various semiconductor memories. In order to independently analyze the signal output from the memory, it must be possible to analyze a wide range of signals. Therefore, there is a problem that the development cost and the manufacturing cost are extremely high.

Further, in the above-described conventional module tester and the like, since the test conditions are fixed and only simple test patterns are set, there is a problem that it is impossible to cope with various functional tests of the semiconductor module.

SUMMARY OF THE INVENTION An object of the present invention is to enable various tests to be performed on a large number of memory modules under conditions close to actual use. It is an object of the present invention to provide a test system which can easily change the test contents in response to the change of the test, and can reduce the development cost and the manufacturing cost.

Another object of the present invention is to provide a method for manufacturing a highly reliable semiconductor memory module using the above-described test system.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a memory module operating device having at least memory control means for directly exchanging signals with a reference memory module to read and write data,
A signal extracting means for extracting an input / output signal between the memory control means and the reference memory module to the outside, a signal distribution means for distributing the input / output signal to a plurality, and an address signal and a write data signal in the distributed signal. A plurality of test modules each having signal supply means for supplying to the test memory module, and comparison means for comparing the read data signal in the distributed signal with the read data signal output from the test memory module Control means;
A data processing device for summing up the comparison results by the respective comparing means of the plurality of test module control means.

According to such means, a signal actually input / output between the memory control means and the reference memory module is copied to the plurality of test memory modules,
Since the test memory module is verified by comparing the operation of the test memory module based on the signal with the operation of the reference memory module, various functional tests can be performed on many test memory modules at once. You can do it. Also, by making the operation contents of the reference memory module the same as in the case of actual use, a test can be performed under conditions close to actual use, and by changing the control contents of the memory control means to various patterns, Compatible with functional tests.

Specifically, a personal computer can be applied as the memory module operation device. By using a personal computer of a model to which the memory module is actually mounted, the test memory module can be tested under conditions very close to actual use. Further, in a personal computer, various types of memory access can be easily realized, and thus, the variation of the test content is abundant.

Further, since the signal output to the memory module at the time of the test is output from the memory control means of the personal computer, the development cost and the manufacturing cost of the test system are lower than when the test signal is generated independently. Cost can be reduced. Further, since the judgment of the failure selection of the memory module is performed, for example, by comparing the read data, it is not necessary to analyze the output signal in detail, and the development cost and the manufacturing cost of the test system can be reduced.

Further, when the type of the memory module and its use environment (such as the system environment of a personal computer) are changed, a personal computer compatible with the memory module can be exchanged as the memory module operation device, thereby simplifying the operation. The test contents can be made to correspond to the change of the memory module.

Preferably, the signal distribution means is configured to distribute the same input / output signal among a plurality of distribution destinations with a time lag. Otherwise, the plurality of test memory modules all perform the same operation at the same time, and the power consumption greatly fluctuates. Therefore, the power supply voltage supplied to the plurality of test memory modules may become unstable. is there. Therefore, the power supply voltage can be stabilized by distributing the input / output signals at different times as described above.

More desirably, the signal extracting means includes:
A drawer board having a memory socket capable of mounting a memory module, a connection terminal having the same shape as a connection terminal of the memory module, and a lead cable for drawing a signal from a signal line connecting the connection terminal and the terminal of the memory socket;
It is preferable to include a connection terminal attachable to a bus slot for connecting a peripheral device to a computer, and an output board having an output circuit for outputting a signal input via the lead cable to the outside.

According to such means, the input / output of the reference memory module can be easily performed using a memory module operating device (for example, a personal computer or its system board) having a configuration close to the environment in which the memory module is actually used. Signal extraction and external output can be performed. That is, the drawer board is mounted on the memory socket to which the signal line is connected to the memory control means, and the reference memory module is mounted on the memory socket on the drawer board. Can be drawn out through the Further, the output board can be mounted on a bus slot to output a signal from the output board to the outside. Power for the circuits on the output board can also be supplied from the bus slots.

The above-mentioned signal distribution means may be provided on an output substrate, and the output substrate may distribute the extraction signal into a plurality of signals and output the extracted signals to the outside. Alternatively, a signal distribution means is provided on the drawer board to distribute signals on the drawer board, or a signal distribution means is provided outside to distribute signals to input / output signals output from the output board. It may be configured to perform signal distribution at a plurality of locations by using a combination.

A method of manufacturing a semiconductor memory module according to the present invention is a method of manufacturing a semiconductor memory module in which a packaged semiconductor memory is mounted on a substrate. An inspection process of performing a probe inspection, a processing process of cutting and packaging blocks that have passed the probe inspection, and a first test process of performing a burn-in test, a DC item, and a setup hold measurement on the packaged semiconductor memory And a mounting step of mounting the semiconductor memory, which has passed the first test step, on a substrate, and a second test of performing a function test for reading and writing data to and reading data from the semiconductor memory module mounted using the test system described above. And a process.

According to such a manufacturing method, since the functional test is performed under conditions close to actual use, it is possible to reliably select defects that cannot be found at the packaging stage but are first discovered at the actual use stage. And a highly reliable memory module can be provided. Furthermore, since the function test that has been conventionally performed on the semiconductor memory in the packaged stage is performed using the above-described test system after mounting the memory module, the overall test time can be significantly reduced. That is, the test at the memory module stage using the above-described test system can be performed at the same time as the test at the memory module stage using the above-described test system, for example, from the viewpoint of the handling ease of the semiconductor memory, than the test at the packaging stage using the general-purpose memory tester Since the number of semiconductor memories greatly increases, the test time can be shortened accordingly.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall external view showing a module tester as a preferred embodiment of a memory module test system according to the present invention, and FIG. 2 is an overall block diagram showing an internal configuration of the module tester.

The module tester 1 of this embodiment is a packaged SDRAM (Synchronous Dynamic Radar).
This is a system capable of performing a functional test on a plurality of memory modules collectively for a memory module (for example, a DIMM) in which a semiconductor memory such as an ndom access memory is mounted on a substrate. As shown in FIG.
The module tester 1 includes a thermostatic chamber unit 10 in which a large number of memory modules 100 to be tested (hereinafter, referred to as test modules) are housed, a control unit 12 for controlling the temperature of the thermostatic chamber unit 10, and a reference operation for module testing. Unit 20 equipped with a measurement PC (personal computer) 23 as a memory module operating device and a display panel 22 for displaying test status and the like, selection of test conditions for test modules, totalization of test results and system It is composed of a control PC 30 for performing overall control. The control PC 30 includes a display panel 32 for displaying an operation status, and input / output devices such as a keyboard and a mouse. An indicator lamp 21 indicating that the test operation is being performed is provided above the measuring unit 20, and a thermostat 10 is provided above the thermostat control unit 12.
An indicator light 11 indicating that the temperature control is being performed is provided.

As shown in FIG. 2, a large number of test units 130 each having a test module 100 and a test module control board 120 mounted on a mounting board 110 are accommodated in the thermostatic chamber unit 10. This test unit 130
Will be described later in detail. In addition, the thermostat unit 10
Is filled with a certain amount of dry air.

Also, as shown in FIG.
0, a low-speed interface 24 for performing data communication with the control PC 30 and the control unit 12A of the thermostatic chamber control unit 12 in addition to the measurement PC 23 and the display panel 22 described above.
A power supply control unit 25 that controls power supply to each unit of the measurement personal computer 23, and a power supply & module control unit 2 that controls power supply and an operation clock of the reference memory module 200.
6 and the like are provided.

The measurement PC 23 performs various functional operations to provide a reference operation of the test module 100 (hereinafter, referred to as a reference module) and an external input / output signal of the reference module 200. Are provided.

Between the measuring unit 20 and the thermostatic chamber unit 10, a distribution board 4 for distributing a signal externally output from the measuring PC 23 and supplying the signal to the thermostatic chamber 10 side.
0 is provided.

In FIG. 2, reference numeral 80 denotes the reference module 20.
Extraction signals extracted from input / output pins 0, 81 are output signals that are externally output after waveform shaping of the extraction signal 80, and 82 is a distribution signal obtained by distributing the output signal 81. Also, 8
Reference numeral 3 denotes a low-speed bus signal for notifying the presence or absence of the input of the extraction signal 80 and the output of the output signal 81; 84, a low-speed bus signal from the test module control board 120 indicating test results of the test module 100; A control signal for changing conditions such as the temperature control unit 86; a signal 86 for instructing temperature setting of the thermostatic chamber unit 10; a signal 87 for notifying a state of the thermostatic chamber unit 10; A signal for displaying and outputting a test status such as the status of 10, and a signal 89 for designating a power supply voltage and an operation clock.

Next, the details of each of the above components will be described. FIG. 3 is a diagram showing a system board mounted on the measurement PC, and FIG. 4 is a block diagram showing a functional configuration of the system board.

The measurement PC 23 is provided with a CPU (Central Procedures) on a system board 240 called a so-called motherboard.
sing unit) 241, memory module 2 serving as main memory
42, a personal computer configured by connecting an expansion card such as a video card or a LAN board that outputs a video signal to a display panel, a storage device such as a hard disk, and input / output devices such as a keyboard and a mouse.

As shown in FIG. 3, the system board 240
Includes a memory socket 243 in which a memory module 242 is mounted and a bus slot 2 in which an expansion card is mounted.
44, CPU 241 and memory module 242
Cache memory 24 which is a high-speed buffer storage between
5. High-speed bus 251 (FIG. 4) to which CPU 241 is connected, dedicated bus 253 (FIG. 4) for memory module 242, and low-speed bus 252 to which expansion cards are connected
A bus bridge 246A as a memory control means, which is one of integrated circuits called a chip set for transferring data between (FIG. 4), and a so-called chip set for performing bus control of a low-speed bus 252 to which an expansion card is connected. A bus controller 246B which is one of the integrated circuits called, a power supply unit 249 for inputting power supply and generating a power supply voltage necessary for the CPU 241, a setting pin for setting a frequency of a system clock and a frequency of an operation clock of the memory module, etc. , Generally provided.

The power supply & module control unit 26 shown in FIG. 2 is connected to the setting pins and the power supply unit 249 of the system board 240. At
The frequency of the operation clock of the reference memory module 200 can be changed.

Since the measurement PC 23 is configured to move the reference module 100 under conditions close to actual use, modules that have little relation to the operation of the reference module 100
For example, input / output devices and various peripheral devices may be operated without being attached. In addition, a storage device such as a hard disk stores a test operation program for reading / writing data from / to the memory module in various patterns, and the reference module 200 is configured to perform the test operation based on the program. May be.

When the type of the memory module to be tested (for example, a DRAM of a single data rate or a DRAM of a double data rate) is changed, the system board 240 can be easily replaced with a type adapted to the change. .

As shown in FIG. 4, access to the memory module 242 from the CPU 241 or a peripheral device mounted in the bus slot 244 is executed via the bus bridge 246A. And this bus bridge 246A
Signals input and output between the reference module 200 and
It is extracted as a reference signal for a test operation.

FIG. 5 is an explanatory diagram of a method for extracting a signal from a reference memory module mounted on a system board.

In the module tester 1 of this embodiment, as shown in FIG.
Signals input / output to / from all the connection terminals of the reference modules 200 are drawn out for distribution to the test module 100. Note that a configuration may be adopted in which a signal is not extracted from a power supply voltage supply terminal of the reference module 200, and a power supply voltage is separately supplied to each test module 100. Similarly, it may be configured to omit the extraction of the clock signal.

FIG. 6A is a configuration diagram showing an example of an extraction board for extracting a signal and an output board for externally outputting a signal. FIGS. 6B and 6C are diagrams showing a modification of the drawer substrate.

In the module tester 1 of this embodiment, a drawer board 210 and an output board 220 as shown in FIG.

The drawer board 210 is connected to the system board 240
A connection terminal mountable in the upper memory socket 243 and a memory socket 213 in which the basic module 200 is mounted.
And a printed wiring connecting the connection terminal portion and the memory socket 213, and a lead cable 215 connected to the printed wiring and leading a signal out of the board.

Then, the drawer board 210 is mounted on the memory socket 243 of the system board 240, and
By mounting the reference module 200 in the memory socket 213 on the drawer board 210, the bus bridge 246A
And the reference module 200 are wired and connected,
The signal during this period is drawn out to the outside via the lead cable 215.

Since the drawer board 210 is mounted on the system board 240 with the reference module 200 mounted, there is a case where the surrounding structure hinders the mounting, which makes the mounting easier. Therefore, FIG.
Modifications of the drawer substrate 210 as shown in FIGS.

Of these, the type shown in FIG. 6B has a drawer board 210A with a longer length and a memory socket 213 provided at a position higher than the board surface of the system board 240. The reference module 200 is horizontally fixed at a position higher than the adjacent memory module 242. According to such a configuration, the reference module 200 can be set while avoiding the adjacent memory module 242.

The type shown in FIG.
A memory socket 213 is provided on the base side of the base module 10B, and this memory socket is used as the reference module 200.
Is inserted in an oblique state (the state shown by the dotted line in FIG. 6C), and then the reference module 200 is rotated until the state becomes a horizontal state (the state shown by the solid line in FIG. 6C). The configuration is such that the reference module 200 is fixed. With such a configuration, it is easy to handle the reference module 200 when the drawer board 210B is mounted.

The output board 220 is driven by the power supply voltage supplied from the bus slot 244. This output board 22
0, a connection connector 221 for connecting the lead cable 215 of the extraction board 210, a buffer 222 (FIG. 5) for waveform shaping into an input extraction signal, distributing signals to two systems, and one of these signals. And a signal distribution circuit 223 (FIG. 5) for delaying the output by several clocks (for example, one clock or two clocks) and outputting the same. The operation of this delay will be described later. Then, the distributed signal is output to the outside via the cable 224.

The buffer 222 is provided with a differential amplifier for converting the extracted clock signal into a differential signal, and the clock signal is output as a differential signal. Note that other data signals, address signals, command signals, and the like may be converted into differential signals and output.

With the above configuration, when the measurement PC 22 operates to input and output signals between the reference module 200 and the bus bridge 246A, these input and output signals are externally transmitted through the extraction board 210 and the output board 220. Is output to

FIGS. 7A and 7B are diagrams showing the arrangement of test modules set in the thermostat unit 10. FIG. 7A is a side view of a test unit in which a test module and a control board are mounted on one mounting board. (B) is a top view thereof, (c)
Is a bottom view showing 24 sets of test units set in a thermostat, and (d) is a top view thereof.

In this embodiment, the test module 100
Are mounted on a large number (for example, 24) of mounting substrates 110 that can be carried into the thermostat unit 10. Mounting board 1
Two test modules 100 are mounted on the upper surface side of 10, and a test module control board 120 for test control of these test modules 100 is disposed on the lower surface side.

The test module control board 120 includes:
Two memory module control circuits 121, 121 (see FIG. 10) corresponding to the two test modules 100, 100 are provided. Further, the test module control board 1
A transmission cable (not shown) for transmitting a signal from the distribution board 40 and a low-speed data transfer cable (not shown) used for data communication with the control PC 30 are connected to 20. Details of the memory module control circuit 121 will be described later.

The mounting board 110, the two test modules 100, 100, and the test module control board 120 form a set of test units 130. (For example, 24 sets).

FIG. 8 is a diagram showing a signal distribution system for distributing the extraction signal extracted from the reference memory module, and FIG. 9 is a time chart of signals input to and output from each unit in this distribution system. Shown respectively.

In the module tester 1 of this embodiment, the extracted signals are distributed in order to supply the signals extracted from the system board 240 of the measurement PC 23 to a number of test units 130 in the thermostat unit 10.
The distribution of the extraction signal is performed by the output substrate 220 mounted on the measurement PC 23 and the distribution substrate 40 provided between the measurement PC 23 and the thermostat unit 10.

That is, as shown in FIG. 8, first, the signal extracted by the extraction board 210 is divided into two systems by the distribution circuit 223 of the output board 220.

In the distribution board 40, the two distribution circuits 4
1 and 41, the test unit 13 in which the input two signals are set in the thermostat unit 10 respectively.
The number is distributed according to the number of zeros. For example, one test unit 130 has two test module control circuits 121,
If the system is equipped with 121 and 24 test units 130, the distribution circuit 41 for distributing the first signal distributes the signal to 24 signals and distributes the second signal. The circuit 41 similarly distributes the signal to 24 signals.

Synchronous flip-flops F / F are provided at the front and rear stages of the distribution circuits 223, 41, 41, respectively. These flip-flops F / F hold and store data in synchronization with a clock signal. By outputting, as shown in FIG.
The transmission is performed at the same cycle speed only by shifting by several cycles from the timing at 0. As a clock signal for operating the flip-flop F / F, for example, an operation clock extracted from a terminal of the reference module 200 is used.

In the output board 220, the distribution circuit 22
By making the number of flip-flops F / F of the third stage different between the first system and the second system, the signals of each system are output with a predetermined cycle (for example, one cycle or two cycles) shift. Has become.

As described above, the signal of the first system and the signal of the second system are output with the signal timing shifted by one cycle, so that the test module control circuit 121 and the test module 200 to which the first system signal is input are output. And the respective operation timings of the test module control circuit 121 and the test module 200 to which the signal of the second system is input are shifted by a predetermined cycle, whereby many test modules 200 perform the same operation at once. The disadvantage that the power consumption greatly fluctuates and the power supply voltage becomes unstable is avoided.

FIG. 10 shows that the test module control board 2
FIG. 3 is a functional block diagram showing a functional configuration of test module control circuits mounted on the test module.

The test module control circuit 121 includes an address bit control section 1211, a control bit control section 1
212, a control bit analysis unit 1213, a data bit control unit 1214, an application determination switching unit 1215, a determination control unit 1216 as comparison means, and the like. Of these, the address bit control unit 1211, the data bit control unit 1214, and the application determination switching unit 1215 constitute a signal supply unit that supplies an address signal and a write data signal to the test module 100.

The test module control circuit 121 has a bus bridge 2 pulled out by the drawer board 210.
An address signal, a control signal, and a write data signal input from the reference module 200 to the reference module 200 and a read data signal output from the reference module 200 to the bus bridge 246A are input from the distribution circuit 40.

The address bit control section 1211 outputs the input address signal to the test module 100 at the same timing as the control signal and the data signal.
The control bit control unit 1212 matches the timing of the input control signal with the test module 1
00 and supplies the same control signal to the control bit analysis unit 1213. The control bit analysis unit 1213 decodes the control signal and outputs a control signal indicating whether the mode is the write mode or the read mode to the data bit control unit 1214 and the application determination switching unit 1215.
Output to If the control signal from control bit analysis section 1213 is a signal indicating the write mode, data bit control section 1214 outputs the input data signal to application determination switching section 1215, and the control signal indicates the read mode. If it is a signal, the input data signal is output to the determination control unit 1216 as expected value data. The application determination switching unit 1215 includes a control bit analysis unit 121
If the control signal from 3 is a signal indicating the write mode,
While the write data from the data bit control unit 1214 is transferred to the test module 100, if the control signal is a signal indicating the read mode, the read data signal from the test module 100 is transferred to the determination control unit 1216. The determination control unit 1216 includes a data bit control unit 121
And a buffer area for temporarily storing the expected value data from the test module 4, and compares the expected value data with the read data from the test module to make a right / wrong determination. Judgment control unit 121
The result determined by the comparison in step 6 is, for example, temporarily stored in a buffer and sent to the control PC 30 in a predetermined format.

In the control PC 30, all the test units 1
The data of the comparison determination result transmitted from 30 is totaled,
The data under the tally and the tally result are displayed on the display panel 32 or output as a data file. This makes it possible to judge the failure of each test module 100.

As described above, according to the module tester 1 of this embodiment, the signal of the reference module 200 operating under the same conditions as the actual use is extracted, and the test module 100 is operated based on this signal to perform verification. Therefore, a large number of test modules can be collectively tested under conditions close to actual use, and various functional tests can be easily realized by reading and writing data to and from the reference module 200 in various patterns. Can be done.

As a device for operating the reference module 200, a measurement PC 22 which is a personal computer is used.
, The development cost and the manufacturing cost of the test system can be reduced as compared with the case where the signal for operating the reference module 200 is generated independently. When the type of the memory module to be tested and its usage environment are changed, the test contents and test conditions can be easily changed according to the memory module by replacing the measurement PC 22 with a personal computer corresponding to the memory module. Can be performed.

As a means for extracting a signal from the reference module 200, a drawer board 210 mountable on a memory socket and an output board 220 mountable on a bus slot are used, which is an actual use environment of the memory module. Signal extraction can be easily performed in a personal computer or the like. In addition, the drawer substrate 210
The output board 200 and the output board 200 can be easily attached to and detached from various system boards.

Next, a description will be given of a manufacturing process of a memory module when the module tester 1 is introduced.

FIG. 11 shows a flow chart of the manufacturing process of the memory module in this case.

In the manufacturing process of the memory module,
Each of the wafer stage, the packaging stage in which a semiconductor chip is incorporated in a plastic or ceramic case, and the module stage in which a packaged semiconductor memory is mounted on a substrate includes a test process for selecting defective products.

When the module tester 1 according to the present invention is introduced, the total time required for the test process in each of the above steps can be shortened as compared with the conventional manufacturing process, and under the conditions closer to actual use. Testing can be performed.

That is, when the module tester 1 according to the present invention is introduced, first, after a wafer is generated (step S1), a probe is applied to each block of the memory integrated circuit formed on the wafer to determine a defect. Perform a probe test to test for memory cells and the like (step S
2). Then, if there is a defective cell, a remedy such as replacing with a redundant cell provided for rescue is performed (step S3). The process at the wafer stage is the same as the conventional general manufacturing process.

Then, after performing a processing for cutting and packaging the wafer for each block (step S
4) A burn-in test (step S5), a DC test using a memory tester (step S6), and a timing test (step S7) are performed on the semiconductor memory in the packaging stage. Here, in the burn-in test, for example, a temperature acceleration test or a supply of a voltage 1.5 times the specified value, for example, is performed to check whether the circuit is short-circuited or opened. In the DC test, DC items such as operating current and leakage current flowing between the power supply voltage supply terminals with the power supply voltage applied are measured to verify that the specifications are satisfied, and in the timing test, the specified operation clock is specified. The setup time and the hold time when operating in the above are measured and verified whether the specifications are satisfied. Here, the semiconductor memory out of the specifications is selected as a defective product.

In the manufacturing process of the memory module of this embodiment, in the next stage, an assembling process of a memory module for mounting a plurality of semiconductor memories on a printed circuit board (step S
8). Then, a long test is performed on the memory module using the module tester 1 (step S
9) and a function test (step S10) are performed. The long test verifies that the operating clock operates normally within a predetermined range of frequencies, for example, half or twice the specified value.The functional test verifies whether various bits are read and written with the specified operating clock to generate error bits. Is done.
Here too, if an error is found, it will be rejected. Then, the module that has passed the above test is shipped as a normal product (step S11).

In the manufacturing process of this embodiment,
The long test and the function test performed in the packaging stage by the memory tester are performed in the module stage by the module tester 1. Thereby,
Long tests and functional tests are performed under conditions close to actual use.Furthermore, functional tests can test various patterns more easily than when using a memory tester. In this way, it is possible to reliably sort out a defect that is found for the first time, and to provide a highly reliable memory module.

Further, while the memory tester can test only a small number of semiconductor memories at the same time, the test using the module tester 1 of the embodiment can simultaneously test many memory modules mounted with a plurality of semiconductor memories. It is possible to perform a test of a simple pattern in a shorter time than before.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, as a module operation device for providing a reference operation of a memory module, a personal computer on which a memory module is actually mounted may be used, or data may be accessed from such a personal computer to the memory module. May be extracted to operate only the circuit configuration of that part. In addition, a circuit that controls the operation of a circuit configuration for accessing data to the memory module is added to set a setting that cannot be performed by a general personal computer (for example, to expand a setting range of an operating frequency, to set an amplitude of an input signal or a power supply voltage). The size may be set. In addition, the board configuration for extracting input / output signals of the reference module and the circuit configuration for distributing the extracted signals can be appropriately changed.

In the above description, the invention made mainly by the present inventor has been described as a module tester used in a manufacturing process of a memory module which is a field of application as a background, but the present invention is not limited to this. For example, it can be widely used when performing a function test of a memory module for various purposes such as a delivery check of the memory module.

[0079]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, a memory module test can be performed under conditions close to actual use, and various and functional tests can be easily performed by using a personal computer as a module operation device. Further, there is an effect that the development cost and the manufacturing cost of the test system can be reduced. In addition, even when the type of the memory module or the usage environment is changed, it is possible to easily cope with the change.

Further, according to the method of manufacturing a memory module using the module tester of the present invention, it is possible to reliably sort out even a defect which occurs for the first time in actual use.
There is an effect that a highly reliable memory module can be provided. Further, there is an effect that the time required for the test can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is an overall external view showing a module tester as a preferred embodiment of a memory module test system according to the present invention.

FIG. 2 is an overall block diagram illustrating an internal configuration of a module tester according to an embodiment.

FIG. 3 is a diagram showing a system board mounted as a measurement system on the module tester of the embodiment.

FIG. 4 is a functional block diagram showing an internal configuration of the system board of FIG. 3;

FIG. 5 is a diagram illustrating a method of extracting a signal from a reference memory module.

FIG. 6 is a configuration diagram illustrating an example of an extraction board for extracting a signal and an output board for externally outputting a signal, and FIGS. 6B and 6C are diagrams illustrating modified examples of the extraction board.

FIG. 7 shows an arrangement state of test modules.
(A) is a side view of a test unit in which a test module and a control board are mounted on one mounting board, (b) is a top view thereof, and (c) shows 24 test units set in a thermostat. FIG. 3D is a bottom view, and FIG.

FIG. 8 is a diagram showing a signal distribution method for distributing an extraction signal extracted from a reference memory module.

FIG. 9 is a time chart showing the input / output timing of signals in each distribution board and measurement memory.

FIG. 10 is a functional block diagram illustrating a functional configuration of a test module control circuit.

FIG. 11 is a flowchart showing a manufacturing process of a memory module when the module tester of the embodiment is used.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Module tester (test system) 10 Thermostatic chamber unit 12 Thermostatic chamber control unit 20 Measurement unit 23 Measurement PC (Module operation device) 30 Control PC (Data processing device) 40 Distribution board 41 Distribution circuit 100 Test module 120 Test module control board 121 Test module control circuit 130 Test unit 200 Reference module 210 Pull-out board 213 Memory socket 215 Lead cable 220 Output board 222 Output buffer (output circuit) 223 Distribution circuit 224 Output cable 240 System board 241 CPU 243 Memory socket 244 Bus slot 246A Bus bridge ( Memory control means) 1211 Address bit control unit 1212 Control bit control unit 1213 Control bit analysis unit 121 Data bit controller 1215 application judgment switching unit 1216 determination control unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01R 31/28 Y (72) Inventor Noboru 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Stock Company Hitachi Semiconductor Co., Ltd. (72) Inventor Yuji Wada 3-16-3 Higashi, Shibuya-ku, Tokyo Inside Hitachi Electronics Engineering Co., Ltd. (72) Kunihiko Miyahara 3-163-3 Higashi, Shibuya-ku, Tokyo Hitachi Electronics Engineering Co., Ltd. (72) Inventor Masaaki Mochizuki 3-16-3 Higashi, Shibuya-ku, Tokyo F-term in Hitachi Electronics Engineering Co., Ltd. 2G132 AA08 AA20 AB14 AC01 AE21 AE23 AJ02 AJ04 AL09 AL11 AL26 5B018 GA03 JA02 JA03 JA04 NA02 QA13 5L106 DD01 DD22 DD23 DD24 DD32 DD35 GG03

Claims (5)

[Claims] 1. A memory module operation device having at least a memory control means for reading and writing data by directly inputting and outputting signals to and from a reference memory module, and extracting input / output signals between the memory control means and the reference memory module to the outside. Signal extraction means, signal distribution means for distributing the input / output signals to a plurality, signal supply means for supplying an address signal and a write data signal in the distributed signals to a test memory module,
And a plurality of test module control means each having comparison means for comparing the read data signal in the distributed signal with the read data signal output from the test memory module; and A data processing device for counting the results of comparison by each comparing means, and a test system for a semiconductor memory module, comprising: 2. The test system for a semiconductor memory module according to claim 1, wherein said memory module operation device is a personal computer. 3. The semiconductor device according to claim 1, wherein said signal distribution means is configured to distribute the same input / output signal among a plurality of distribution destinations with a time lag. Test system for memory modules. 4. The signal extracting means includes: a memory socket to which a memory module can be mounted; a connection terminal having the same shape as a connection terminal of the memory module; and a signal line connecting the connection terminal and the terminal of the memory socket. A drawer board having a lead cable for drawing out, a connection terminal attachable to a bus slot for connecting a peripheral device to a computer, and an output having an output circuit for outputting a signal input through the lead cable to the outside The test system for a semiconductor memory module according to claim 1, further comprising a substrate. 5. A method of manufacturing a semiconductor memory module comprising a packaged semiconductor memory mounted on a substrate, comprising: an inspection step of performing a probe inspection on a wafer on which an integrated circuit of the semiconductor memory is formed; A process of cutting and packaging blocks that have passed the probe test, and a burn-in test on the packaged semiconductor memory,
First to measure DC items and setup hold
A test step, a mounting step of mounting the semiconductor memory that has passed the first test step on a substrate, and data verification by reading and writing data on the semiconductor memory module mounted using the test system according to claim 1. And a second test step of performing a function test.