CN112331251A - Test method of semiconductor memory - Google Patents
Test method of semiconductor memory Download PDFInfo
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- CN112331251A CN112331251A CN202011408393.1A CN202011408393A CN112331251A CN 112331251 A CN112331251 A CN 112331251A CN 202011408393 A CN202011408393 A CN 202011408393A CN 112331251 A CN112331251 A CN 112331251A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000010998 test method Methods 0.000 title claims abstract description 13
- 238000012360 testing method Methods 0.000 claims abstract description 74
- 238000011990 functional testing Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 27
- 238000004806 packaging method and process Methods 0.000 claims description 18
- 238000012795 verification Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 10
- 238000012858 packaging process Methods 0.000 claims description 6
- 230000003712 anti-aging effect Effects 0.000 claims description 5
- 238000013461 design Methods 0.000 claims description 3
- 238000000275 quality assurance Methods 0.000 claims description 3
- 238000004064 recycling Methods 0.000 claims description 3
- 230000002950 deficient Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 8
- 230000006870 function Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
Abstract
The invention discloses a test method of a semiconductor memory, and relates to the technical field of semiconductor memory test. The invention comprises a DC test, a functional test and an AC test, wherein the DC test verifies the voltage and current parameters of a semiconductor, the functional test verifies a series of logic functional operations and correctness thereof in a chip, and the AC test ensures that the chip can complete the logic operations within specific time constraints. The testing method of the semiconductor memory has higher detection precision on semiconductor hardware, has wider related range of detection links, can effectively reduce the error rate and improve the product yield.
Description
Technical Field
The invention relates to the technical field of semiconductor memory testing, in particular to a testing method of a semiconductor memory.
Background
A solid-state electronic device for storing data information, which is made by semiconductor integrated circuit technology, is composed of a large number of identical memory cells and input and output circuits, each memory cell has two different characteristic states '0' and '1' for storing different information, the semiconductor memory is an important component of computer, compared with magnetic memory, the semiconductor memory has the advantages of fast access speed, large storage capacity, small volume, etc., and the memory cell array is compatible with main peripheral logic circuit, can be made on the same chip, and greatly simplifies the input and output interfaces, therefore, in the aspect of computer high-speed storage, the semiconductor memory has completely replaced the past magnetic memory, and the main advantages of the memory are: firstly, a memory cell array and a main peripheral logic circuit are manufactured on the same silicon chip, and output and input levels can be compatible and matched with circuits outside the same chip, so that an interface between two parts of operation, control and storage of a computer can be greatly simplified; the data storing and reading speed is about three orders of magnitude faster than that of a magnetic memory, so that the operation speed of the computer can be greatly improved; the volume and cost of the memory are greatly reduced and lowered by using a large-capacity semiconductor memory, therefore, in the aspect of computer high-speed storage, the semiconductor memory completely replaces the past magnetic memory, is used as a semiconductor memory of a large-scale integrated circuit, is a 1-kilo-bit dynamic random access memory which is produced before and after 1970, reaches the storage capacity of 1 megabit per chip by the improvement of process technology until 1984, and can be divided into three categories of a Random Access Memory (RAM), a Read Only Memory (ROM) and a serial memory according to different functions, the capacity of the semiconductor memory is increased very fast by the development of the process technology of the semiconductor integrated circuit, the capacity of a single chip is increased to a megabit level, for example, a 16-megabit Dynamic Random Access Memory (DRAM) is commercialized, and 64-megabits and 256-megabits are developed;
the existing testing method of the semiconductor memory has a poor coverage for hardware detection in the semiconductor processing process, an error exists for the hardware detection, and the existing testing method has a certain limitation because the control degree of unqualified products is poor.
Disclosure of Invention
The invention aims to provide a method for testing a semiconductor memory, which solves the problems that the related range of the conventional method for testing the semiconductor memory to hardware detection in the semiconductor processing process is insufficient, the hardware detection has errors, the handling control degree of unqualified products is poor, and the like.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention relates to a test method of a semiconductor memory, which comprises a DC test, a functional test and an AC test, wherein the DC test verifies the voltage and current parameters of a semiconductor, the functional test verifies a series of logic functional operations and the correctness thereof in a chip, and the AC test ensures that the chip can complete the logic operations within specific time constraints.
The test method comprises the following steps:
the method comprises the following steps: cutting the wafer into independent circuit units, and independently packaging and testing the single unit;
step two: testing the cut independent circuit units once, wherein the testing direction is to verify the correctness of each circuit unit after packaging so as to meet the finishing index;
step three: performing device characteristic description on each independent circuit unit tested in the steps, and setting the limit value of the device working parameter range;
step four: performing secondary test on the wafer subjected to the device characteristic description, wherein the test direction is an anti-aging index;
step five: packaging verification is carried out after the test indexes are finished, and whether the chip is still intact after the packaging process is detected;
step six: and evaluating the packaging verification process in the fifth step to verify the correctness of the packaging verification process so as to further optimize the packaging verification link.
Preferably, the test method utilizes a test program to test the system hardware, and then provides a corresponding test result to determine whether the hardware meets the design requirements.
Preferably, the testing of the cut individual circuit units in the second step further includes a quality assurance test to ensure that there are no non-defective products.
Preferably, the method for testing the anti-aging index in the fourth step comprises a mode of expanding the temperature range.
Preferably, after the test result is obtained by the test method, hardware classification is performed according to the performance of the test result, so that the actual application field of the hardware is divided.
Preferably, the test system is composed of electronic circuits and mechanical hardware, and is an assembly of power supplies, measuring instruments, signal generators, pattern generators and other hardware items under the direction of the same main controller.
Preferably, the pins of the semiconductor device DUT are signal, power and ground, respectively, the signal pins include four types of input, output, tri-state and bi-directional, and the power pins include power and ground, which constitute a power supply loop, having a different circuit configuration than the signal pins.
Preferably, step seven: and fifthly, checking whether the chip is in good condition in the packaging process, recycling the failed chip, analyzing and finding out key factors of failure so as to enhance the reliability of the chip.
The invention has the following beneficial effects:
the testing method of the semiconductor memory has higher detection precision on semiconductor hardware, has wider related range of detection links, and can effectively reduce the error rate.
The method for testing the semiconductor memory can find the problem of influencing the product failure in time after the semiconductor memory is tested, can accurately solve the problem according to the related problems and effectively ensure the quality.
The test method of the semiconductor memory is simple to operate, low in use cost and high in popularization value.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart illustrating an operation of a method for testing a semiconductor memory according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention relates to a test method of a semiconductor memory, which comprises a DC test, a functional test and an AC test, wherein the DC test verifies the voltage and current parameters of a semiconductor, the functional test verifies a series of logic functional operations and correctness thereof in a chip, and the AC test ensures that the chip can complete the logic operations within specific time constraints.
As shown in fig. 1, the test method comprises the following steps:
the method comprises the following steps: cutting the wafer into independent circuit units, and independently packaging and testing the single unit;
step two: testing the cut independent circuit units once, wherein the testing direction is to verify the correctness of each circuit unit after packaging so as to meet the finishing index;
step three: performing device characteristic description on each independent circuit unit tested in the steps, and setting the limit value of the device working parameter range;
step four: performing secondary test on the wafer subjected to the device characteristic description, wherein the test direction is an anti-aging index;
step five: packaging verification is carried out after the test indexes are finished, and whether the chip is still intact after the packaging process is detected;
step six: and evaluating the packaging verification process in the fifth step to verify the correctness of the packaging verification process so as to further optimize the packaging verification link.
The test method utilizes a test program to test system hardware, and then provides a corresponding test result to judge whether the hardware meets the design requirement, the test system hardware is controlled by a computer running a group of instructions (test program), and during the test, appropriate voltage, current, time sequence and function states are provided for a DUT and the response of the DUT is monitored, so as to compare test values.
And step two, testing the cut independent circuit units further comprises quality assurance testing so as to ensure that no unqualified product exists.
And the method for testing the anti-aging index in the fourth step comprises a mode of expanding the temperature range.
After the test result is obtained by the test method, hardware classification is carried out according to the performance of the test result, and therefore the actual application field of the hardware is divided.
The test system consists of an electronic circuit and mechanical hardware, is an assembly of a power supply, a metering instrument, a signal generator, a pattern generator and other hardware items under the command of the same main controller, and is used for simulating the operation conditions which will be experienced by a tested device in application so as to find out unqualified products.
Pins of a semiconductor device DUT are respectively a signal, a power supply and a ground, and the signal pins comprise four types of input, output, tri-state and bi-directional; the input pin senses the voltage on the signal input channel and converts the voltage into 0 and 1 voltages identified by the internal logic; the output refers to a signal output channel which plays a buffer role between the internal logic of the chip and the external environment, and an output pin provides correct voltage of logic 0 or 1 and provides proper starting current; tri-state refers to a class of outputs that have the ability to turn off; the bidirectional finger is a pin which has input and output functions and can reach a high-resistance state; the power supply pin comprises a power supply and a ground, forms a power supply loop and has a circuit structure different from that of the signal pin.
Wherein, the seventh step: and fifthly, checking whether the chip is in good condition in the packaging process, recycling the failed chip, analyzing and finding out key factors of failure so as to enhance the reliability of the chip.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A test method of a semiconductor memory including a DC test, a functional test, and an AC test, characterized in that: the DC test verifies the voltage and current parameters of the semiconductor, the functional test verifies a series of logic functional operations and correctness thereof in the chip, and the AC test ensures that the chip can complete the logic operations within specific time constraints.
2. A method for testing a semiconductor memory according to claim 1, wherein the method comprises the steps of:
the method comprises the following steps: cutting the wafer into independent circuit units, and independently packaging and testing the single unit;
step two: testing the cut independent circuit units once, wherein the testing direction is to verify the correctness of each circuit unit after packaging so as to meet the finishing index;
step three: performing device characteristic description on each independent circuit unit tested in the steps, and setting the limit value of the device working parameter range;
step four: performing secondary test on the wafer subjected to the device characteristic description, wherein the test direction is an anti-aging index;
step five: packaging verification is carried out after the test indexes are finished, and whether the chip is still intact after the packaging process is detected;
step six: and evaluating the packaging verification process in the fifth step to verify the correctness of the packaging verification process so as to further optimize the packaging verification link.
3. The method as claimed in claim 2, wherein the testing method utilizes a testing program to test the system hardware and then provides a corresponding test result to determine whether the hardware meets the design requirement.
4. The method as claimed in claim 3, wherein the step two of testing the diced individual circuit units further comprises a quality assurance test to ensure non-defective products.
5. The method as claimed in claim 4, wherein the step four includes expanding the temperature range.
6. The method as claimed in claim 5, wherein after the test result is obtained, the hardware is classified according to performance according to the test result, thereby dividing the actual application field.
7. The method of claim 6, wherein the test system comprises electronic circuits and mechanical hardware, and is an assembly of power supplies, metrology instruments, signal generators, pattern generators and other hardware items under the direction of the same host controller.
8. The method as claimed in claim 7, wherein the pins of the semiconductor device DUT are signal, power and ground, respectively, the signal pins include four types of input, output, tri-state and bi-directional, and the power pins include power and ground, which constitute a power supply loop, having a different circuit configuration from the signal pins.
9. The method for testing a semiconductor memory according to claim 8, wherein the step seven: and fifthly, checking whether the chip is in good condition in the packaging process, recycling the failed chip, analyzing and finding out key factors of failure so as to enhance the reliability of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011408393.1A CN112331251A (en) | 2020-12-03 | 2020-12-03 | Test method of semiconductor memory |
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| CN202011408393.1A CN112331251A (en) | 2020-12-03 | 2020-12-03 | Test method of semiconductor memory |
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