KR100459867B1 - Pattern Generation Board Equipment - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generating substrate device for a semiconductor device test apparatus, and more particularly, an input power supply unit for supplying power from a power generation unit to the device, a clock generator for generating a desired clock frequency, and a clock phase. Phase Locked Loop, Programmable Logic Device (EPLD), and Double In-Line Memory Module (DIMM) slots for pattern synchronization, allowing pattern programming like ATE (Automatic Test Equipment) under nearly identical mounting conditions It is a pattern generator board device that designs its own processor in EPLD to enable memory pattern test.

The use of programmable logic devices (EPLDs) overcomes the limitations of chipsets in embedded test systems and allows the testing of multiple memory components and modules using one EPLD, and more memory modules and modules when using multiple EPLDs. Cost savings can be achieved with this device, which is able to test components simultaneously and is inexpensive.

Description

Pattern Generation Board Equipment {Pattern Generation Board Equipment}

The present invention is a pattern generating substrate device for a semiconductor device test apparatus, and in particular, by using a chip of a programmable logic device (EPLD) to enable a pattern program like an automatic inspection equipment (ATE), by configuring the same board as the actual environment The present invention relates to a pattern generator that can easily reproduce defects occurring in mounting.

1 is a block diagram illustrating a memory test board according to the prior art (Korean Patent Application Laid-Open No. 2000-0040293).

In order to test the memory module 10 on the memory test board, the input / output terminal 20 of the memory module, the output terminal 30 of the test equipment, and the input terminal 40 of the test equipment are commonly connected to the output node 50. In the write state of the memory module, data is output through the output terminal 30 of the test equipment. Then, the data is input through the input and output terminal 20 of the memory module, the signal output data through the input and output terminal 20 of the memory module in the read state of the memory module is input through the input terminal 40 of the test equipment is tested The device checks the memory module for normal operation by comparing the signal values.

At this time, the variable resistor 60 is connected to the output node 50 as a matching means, and the variable resistor 60 is connected to the terminal voltage source 70 so as to maintain the same voltage level as that of the output node 50. The signal applied to the node 50 is prevented from being attenuated. That is, the voltage level of the output node 50 is not changed to prevent distortion of data due to the addition of the variable resistor.

Although the present invention is evaluated in an actual use environment, when testing a large number of cells such as a memory, it takes a lot of time for cell testing and has a disadvantage in that the desired data cannot be accessed at a desired timing for an accurate test.

FIG. 2 is a block circuit diagram illustrating an interface board and a method for testing a semiconductor integrated circuit device using the same according to another conventional technology (Korean Patent Application Laid-Open No. 2001-0096954).

The CPU 220 is an Intel Pentium III processor, and the semiconductor device mounted on the interface board 100 is a synchronous DRAM (SDRAM). The clock signal CLK generated by the clock driver 270 is input to the CPU 220 and the chipset 280, respectively. The clock signal CLK is output from the chipset 280 and input to the interface substrate 100 through the CLK buffer 290. The clock signal supplied from the CLK buffer 290 to the interface substrate 100 is a reference clock signal for the operation of a semiconductor device mounted on the socket 160, for example, a synchronous DRAM semiconductor device.

The clock signal CLK input to the interface substrate is input to the clock distribution circuit 300 as the clock signal CLK through the resistor R1. Clock signal CLK is connected in parallel with ground via capacitor C1. The clock distribution circuit 300 receives one clock signal CLK and outputs several clock signals Y0-Y8 and Y9 simultaneously. The clock signal distribution circuit 300 uses a phase locked loop (PLL) technique so that the semiconductor device to be tested has a clock signal at the same timing as the environment in which it is actually used.

The register 400 allows control signals and the like of the semiconductor device to be tested to have the same timing margin as the environment in which the device is actually applied. The register circuit 400 is a kind of driver IC operating in a register mode. When the register circuit 400 receives an input signal and outputs an output signal, the register circuit 400 stretches the output signal longer than the input signal actually received.

The invention has the advantage of making the same pattern as when supplied in the actual use environment of the semiconductor device, but the circuit configuration is complicated and difficult to access the desired data at the desired timing by the memory controller called the chipset at the desired timing there was.

The present invention is to solve the above problems,

An object of the present invention is to implement a pattern generation algorithm using its own processor implemented in a programmable logic device (EPLD) by writing a program with its own test language and compiler.

Another object of the present invention is to design a unique processor for generating a pattern program so that the semiconductor device can be evaluated in the same environment as the actual use environment, and at the same time an automatic test is possible.

Still another object of the present invention is to reduce the cost by replacing expensive automatic test apparatuses while minimizing the defects occurring in the mounting by taking advantage of the mounting test and the automatic test.

1 is a memory test board in a conventional mounting environment.

2 is a schematic block diagram between a mounting component of a conventional main board and an interface board.

3 is an overall block diagram of a pattern generating substrate of the present invention.

* Description of the symbols for the main parts of the drawings *

310: pattern generating substrate 312: EPLD

314: input power supply unit 316: termination power supply unit

318: clock generator 320: flash memory

322 termination resistor 324 phase locked loop

326: DIMM Slot 330: server

332: RS232C interface 336: power generation unit

340: interface board 342: memory

360: test board

In order to achieve the above object, the present invention relates to a pattern generating substrate device for a semiconductor device test device.

The present invention relates to a programmable logic device (EPLD) having an input power supply and a pattern program that receives power from a programmable power generator and supplies power to the pattern generating substrate device, and a clock generator for sending a clock signal to the EPLD. It is connected to RS232C interface for communication with server, such as phase locked loop (PLL) which makes the clock signal to the EPLD and sends the program to the EPLD and receives the test result. It is a pattern generation board | substrate apparatus characterized by the above-mentioned.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 3 is a block diagram illustrating a pattern generation substrate according to the present invention, and is shown in connection with the interface board 340. A pattern generating substrate 310 using a chip of the EPLD 312, which has designed its own processor capable of executing a test program between the server 330 and the interface substrate 340.

The present invention is largely composed of a test board 360 part for generating a timing pattern and a server 330 part for compiling a user-written program and transmitting it to the test board to start a test and receive and analyze a result.

More specifically, the server 330 transmits the program written by the user to the test board 360 through the RS232C interface 332, and generates a test pattern for the memory test in the pattern generating substrate device 310 to output to the memory It is configured to receive the test result and deliver it to the server 330.

The pattern generating substrate device 310 of the present invention uses a programmable logic device 312 (hereinafter referred to as EPLD) instead of a chipset on a board configured in the same manner as in the actual environment.

The EPLD 312 is a chip that designs and embeds a program for generating a pattern algorithm. The EPLD 312 may read / write and adjust timing of a signal supplied to a semiconductor device.

That is, the EPLD 312 receives and executes a program from the server 330 and the server 330 which compiles its own test language, and generates a pattern to implement its own pattern algorithm for generating desired timing in memory. It is connected to the flash memory 320 as the EPLD (312) backup memory for storing the program, and to store the program.

The input power source 314 that receives the voltage (5V, 3.3V, 2.5V) from the programmable power generator 336 and supplies power to the EPLD 312 is not only an EPLD 312 but also a memory 342 (DUT). The clock generator 318 is supplied to all devices.

The programmable clock generator 318 adjusts the timing of the feedback signal input / output terminal and the clock signal, generates a real time clock, and supplies the generated clock to the EPLD 312 to have the same configuration as the mounting environment.

The phase locked loop 324 (PLL), which makes the phase difference between the clock signal and the feedback signal input from the EPLD 312 to zero, outputs the same signal through a dual in-line memory module (DIMM) slot 326. 340).

Since the DIMM slot 326 is composed of the JEDEC standard, the memory module can be inserted into the DIMM slot 326 to enable module testing, and can also be connected to an interface board 340 equipped with a socket to allow component testing.

The high-speed EPLD 312 used in the pattern generating substrate 310 uses a termination resistor 322 so that a signal fast enough to collide with the termination resistor 322 and act as a sponge to eliminate reflection. Absorbs the signal and minimizes the distortion of the signal through impedance matching to send the signal through the DIMM slot 326.

The termination resistor 322 conforms well to the characteristics of actual signal transmission, such as the pattern generating substrate 310 of the present invention, and has an impedance of about 10 to 100 ohms through the termination power supply 316.

The RS232C interface 332 transmits the test program from the server 330 to the EPLD 312 and passes the test result back to the server 330.

That is, the pattern generating substrate 310 is connected to the above components, so that the test can be performed through the entire memory, and also the program can be programmed using its own test language and compiler.

By designing its own processor that can execute this test program using EPLD 312, the semiconductor device can be evaluated by its test language and compiler in the actual use environment, and it is possible to test automatically using pattern program like ATE. In the case of using a plurality of EPLDs 312, a plurality of memory modules and components may be tested.

The above embodiments are intended to illustrate the present invention and the scope of the present invention is not limited to the above-described embodiments, but may be modified or modified by those skilled in the art within the scope of the present invention defined by the appended claims.

According to the present invention, using a programmable device (EPLD) instead of a chipset on the board configured in the same manner as the mounting environment, taking advantage of the mounting test device and the automatic test device (ATE), it is possible to pattern program to enable automatic testing like ATE Design your own processor to enable pattern testing in the context of mounting, reducing test time when testing many cells, such as memory, and reducing cost costs by using inexpensive programmable devices (EPLDs). Reduction has the effect of improving the productivity of the semiconductor device.

Claims (4)

A pattern generating substrate device for generating a pattern provided for automatically testing a semiconductor device, A programmable logic device (EPLD) with a processor implementing a test pattern algorithm for testing the semiconductor device; An input power supply unit supplying power output from the power generation unit of the EPLD; A clock generator for sending a clock signal to the EPLD; A phase locked loop (PLL) which generates the same timing clock signal as the clock signal output from the clock generator and sends it to the EPLD; A termination resistor for minimizing distortion of the signal by impedance matching in order to make the signal sent from the EPLD equal to a mounting environment; A termination power supply for supplying power to the termination resistors; And a DIMM slot to insert a memory to receive a clock signal of the phase locked loop and to transmit a signal through a termination resistor. The method of claim 1, The EPLD is a server that compiles its own test language and a program received from the server. The EPLD generates a pattern program for testing a semiconductor device input through a DIMM slot and has its own processor for generating a desired timing in a memory. An RS232C interface for communication with the server for testing the input device with the pattern program and including a flash memory which is a backup memory capable of storing the pattern program, and transmitting a program to the EPLD and receiving a test result. Pattern generating substrate device, characterized in that connected with. The method of claim 1, The phase locked loop (PLL) is a timing clock signal identical to a real environment, and minimizes skew and jitter of the clock signal. The method of claim 1, The DIMM slot conforms to the JEDEC standard, allows the memory module to be tested by inserting a memory module, enables component testing through an interface board equipped with a socket, and can be used throughout the memory device. Device.