JPS5658671A - Tester for logical circuit - Google Patents

Tester for logical circuit

Info

Publication number
JPS5658671A
JPS5658671A JP13557579A JP13557579A JPS5658671A JP S5658671 A JPS5658671 A JP S5658671A JP 13557579 A JP13557579 A JP 13557579A JP 13557579 A JP13557579 A JP 13557579A JP S5658671 A JPS5658671 A JP S5658671A
Authority
JP
Japan
Prior art keywords
test
parallel
circuit
logical circuit
ffs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13557579A
Other languages
Japanese (ja)
Inventor
Shigeru Takasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13557579A priority Critical patent/JPS5658671A/en
Publication of JPS5658671A publication Critical patent/JPS5658671A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To test the logical circuit speedily and readily by applying a test data in parallel through FFs to a logical circuit to be tested to which the ordinary input is inhibited in the test mode, as well as outputting the results in parallel.
CONSTITUTION: When the logical circuit 11 or the like is selected in a CPU26 or the like, a test mode signal from the CPU26 closes AND circuits 17 in a control circuit 13 for test, and consequently the input from a logical circuit 10 to the circuit 11 is inhibited. Then, the test data stored in a RAM22 are passed through OR circuits 19, stored in external parallel FFs 15 and applied to the circuit 11 in parallel. The test results are outputted from the circuit 11 in parallel, passed through a similar control circuit 14 for test and external parallel FFs 16, and stored in a RAM23. The parallel processing by comparing the contents in the RAMs 22 and 23 permits the test to be faster than the one-pass scan FF system, and the external FFs permit the test of a logical circuit for which one-pass can not be formed to be automatically performed. Thus, a logical circuit can be readily and speedily tested.
COPYRIGHT: (C)1981,JPO&Japio
JP13557579A 1979-10-19 1979-10-19 Tester for logical circuit Pending JPS5658671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13557579A JPS5658671A (en) 1979-10-19 1979-10-19 Tester for logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13557579A JPS5658671A (en) 1979-10-19 1979-10-19 Tester for logical circuit

Publications (1)

Publication Number Publication Date
JPS5658671A true JPS5658671A (en) 1981-05-21

Family

ID=15155014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13557579A Pending JPS5658671A (en) 1979-10-19 1979-10-19 Tester for logical circuit

Country Status (1)

Country Link
JP (1) JPS5658671A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63218882A (en) * 1985-10-23 1988-09-12 テキサス　インスツルメンツ　インコーポレイテツド Testable logic device with plurality of control/observation node
JPS643744A (en) * 1987-06-26 1989-01-09 Hitachi Ltd Lsi test method
JP2009093205A (en) * 2009-02-02 2009-04-30 Hinomoto Gosei Jushi Seisakusho:Kk Molecule model

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63218882A (en) * 1985-10-23 1988-09-12 テキサス　インスツルメンツ　インコーポレイテツド Testable logic device with plurality of control/observation node
JPS643744A (en) * 1987-06-26 1989-01-09 Hitachi Ltd Lsi test method
JP2009093205A (en) * 2009-02-02 2009-04-30 Hinomoto Gosei Jushi Seisakusho:Kk Molecule model

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