JPS5534313A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5534313A
JPS5534313A JP10607378A JP10607378A JPS5534313A JP S5534313 A JPS5534313 A JP S5534313A JP 10607378 A JP10607378 A JP 10607378A JP 10607378 A JP10607378 A JP 10607378A JP S5534313 A JPS5534313 A JP S5534313A
Authority
JP
Japan
Prior art keywords
bit
error detect
bit portion
worst pattern
data bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10607378A
Other languages
Japanese (ja)
Inventor
Koichi Aida
Toyoshi Yamada
Koji Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10607378A priority Critical patent/JPS5534313A/en
Publication of JPS5534313A publication Critical patent/JPS5534313A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To independently set the data bit portion and the error detect bit portion in the information accommodated in the memory, thereby perform the complete test by providing the change-over gate circuit at the output side of the error detect bit forming circuit.
CONSTITUTION: In the case of testing the memory device 1, the worst pattern as right data bit 4 is employed and it is stored as the information of the data bit 2. At this time, the error detect bit forming circuit 9 is controlled by the switching signal 8 and logic 1 is put into the respective bits as outputs without generating ECC signal as output thereof, thereby the worst pattern from the test bit is put out as output bit 13 of the change-over gate circuit 11 and the worst pattern can be stored also in the error detect bit portion 3. Accordingly, the data bit portion 2 of the memory 1 and the error detect bit portion 3 can store the worst pattern, so that the test under the severe conditions can be executed.
COPYRIGHT: (C)1980,JPO&Japio
JP10607378A 1978-08-30 1978-08-30 Memory device Pending JPS5534313A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10607378A JPS5534313A (en) 1978-08-30 1978-08-30 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10607378A JPS5534313A (en) 1978-08-30 1978-08-30 Memory device

Publications (1)

Publication Number Publication Date
JPS5534313A true JPS5534313A (en) 1980-03-10

Family

ID=14424410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10607378A Pending JPS5534313A (en) 1978-08-30 1978-08-30 Memory device

Country Status (1)

Country Link
JP (1) JPS5534313A (en)

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