JPS59216255A - Error detecting system of interruption stack area - Google Patents

Abstract

PURPOSE:To improve a maintenance property in case of generation of a parity error of a memory by executing separately a detection of an error in an interruption stack area, and a detection of an error generated in other area of the memory. CONSTITUTION:A data read out to a register 2 from stack areas N-P of a memory 1 is checked by a parity checking circuit 3. If a parity error exists, an error detecting signal is sent out to an AND circuit 5 and 6. At the same time, addresses N-P of the stack area send a data to a NOT circuit 4 and the AND circuit 5 from a terminal A. Accordingly, the AND circuit 5 becomes on, and sends out a parity error generating signal from a terminal B. Also, if a parity error is generated in other area than the stack area of the memory 1, since the address is other than N-P, the address is not sent out to the terminal A, and an output of the NOT circuit 4 becomes ''1''. Accordingly, the AND circuit 6 becomes on and sends out a parity error generating signal from a terminal C.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a computer system equipped with an interrupt stack area (an area of memory that handles data in a last-in, first-out manner) in memory, and particularly relates to a computer system that handles multiple interrupts. nest (
The error detection formula for the interrupt stack area (b ) Conventional technology and problems The computer processor writes/writes the interrupt stack area.
When a ROM is installed in the address area of a memory that can output uL, if a parity error occurs in the memory, the processor is stopped and the parity error is displayed, and a ROM is installed in the address area of the processor to handle the parity error. There is a method in which the information is processed by a program stored in the ROM. However, each of the conventional methods described above has the following disadvantages. In other words, the former has the disadvantage that the entire computer system is stopped, and the latter has the disadvantage that even if recovery processing is performed by the program in the ROM, when a parity error occurs in the stack area, the data in the stack area is unreliable. , there is a drawback that errors occur in error handling.

(C) Object of the Invention In order to eliminate the above-mentioned drawbacks, the object of the present invention is to separate the detection of parity errors in the stack area from the detection of parity errors in memory areas other than the stack area. The objective is to provide an error detection method for the interrupt stack area that improves the performance of the interrupt stack.

(d) Structure of the Invention The structure of the present invention is that in a computer system in which an interrupt stack area is provided in the memory, 1) Error detection in the J-input stack area and other functions of the memory (e) Embodiment of the Invention FIG. 1 does not show an embodiment of the present invention, but is a schematic diagram of a circuit. Is memory 1 a processor [! ;Include/j, IE
A stack area is provided at addresses N - 1) of address O-Z in memory that can be accessed. Figure 2 is a program routine that explains the present invention! ', j'l is a flowchart in the case where the input is performed. If there is an interrupt in the middle of the program routine, the heart will be interrupted.
l'z, - stores the processor status in the stack area, and processes the interrupts under control of the program. When the separation processing is completed, the bar 1-ware loads the processor status from the stack area and returns to the original program routine, but when loading the processor status, it generally loads the processor status from the stack area.

A parity error occurs in the storage area. That is, memory 1
The data read from the stack area NP to the memory buffer register 2 is checked by a parity check circuit 3, and if there is a parity error, an error detection signal is sent to AND circuits 5 and 6. Addresses N-P of the stack area are simultaneously connected to the terminals to NOT circuit 4 and AN.
The signal is sent to the D circuit 5. Therefore, the AND circuit 5 is turned on and a parity error occurrence signal is sent from the terminal B.

Since the output of the NOT circuit 4 is °°0'', the AND circuit 6 remains off. If a parity error occurs outside the stack area of memory 1, the address 1° is outside N-P12J, so the AND circuit 6 remains off. No address is sent to the terminal C, the output of the NOT circuit 4 becomes 1'', the AND circuit 6 is turned on, and a parity error occurrence signal is sent from the terminal C. In this case, AND circuit 5 remains off.

(f) As described in detail, the present invention eliminates the need to detect errors occurring in the stack area and other memory areas, since it is difficult to detect them separately. When an error occurs in an area, it indicates that it is difficult to return to the program routine. 1
It is possible to take the measures described in item 9, and it is possible to improve maintenance and Ill.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a circuit showing an embodiment of the present invention, and FIG. 2 is a flowchart 1--, which is 1+, when an interrupt occurs in a program routine explaining the present invention. Ru. 1 is a memory, 2 is a register, and 3 is a logic circuit.

Claims (1)

[Claims] In a computer system in which an interrupt stack area is provided in a memory, error detection in the interrupt stack area and error detection occurring in other areas of the memory are performed separately. Error detection method for interrupt stack area.