JPS5532208A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5532208A
JPS5532208A JP10259178A JP10259178A JPS5532208A JP S5532208 A JPS5532208 A JP S5532208A JP 10259178 A JP10259178 A JP 10259178A JP 10259178 A JP10259178 A JP 10259178A JP S5532208 A JPS5532208 A JP S5532208A
Authority
JP
Japan
Prior art keywords
address
memory
error
substitute
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10259178A
Other languages
Japanese (ja)
Other versions
JPS5751200B2 (en
Inventor
Taiji Nosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10259178A priority Critical patent/JPS5532208A/en
Publication of JPS5532208A publication Critical patent/JPS5532208A/en
Publication of JPS5751200B2 publication Critical patent/JPS5751200B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To eliminate the need of the replacement of a component of a main memory even if, a fault occurs to the memory, by providing an error memory and substitute memory.
CONSTITUTION: When an uncorrectable error occurs and error address Ej is detected, processor 5 writes "1" on disabling bit 12 of address Ej under the control of microprogram 4 and also writes "1" on substitute bit 11 of address Ej+1 while writing substitute address Aj of substitute memory 3 in address Ej+1. After the execution of arithmetic of Aj+2 to Aj and i+1 to i, the error bit in address (i) of error memory is set to "1" and error address Ej is stored. Therefore, the replacement of a component of the memory is unneded even if the main memory gets out of order.
COPYRIGHT: (C)1980,JPO&Japio
JP10259178A 1978-08-23 1978-08-23 Memory control system Granted JPS5532208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10259178A JPS5532208A (en) 1978-08-23 1978-08-23 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10259178A JPS5532208A (en) 1978-08-23 1978-08-23 Memory control system

Publications (2)

Publication Number Publication Date
JPS5532208A true JPS5532208A (en) 1980-03-06
JPS5751200B2 JPS5751200B2 (en) 1982-10-30

Family

ID=14331467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10259178A Granted JPS5532208A (en) 1978-08-23 1978-08-23 Memory control system

Country Status (1)

Country Link
JP (1) JPS5532208A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109311A (en) * 1980-10-27 1982-07-07 Gen Signal Corp Electronic interrupter
JPH0222080U (en) * 1988-07-25 1990-02-14

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109311A (en) * 1980-10-27 1982-07-07 Gen Signal Corp Electronic interrupter
JPH0222080U (en) * 1988-07-25 1990-02-14

Also Published As

Publication number Publication date
JPS5751200B2 (en) 1982-10-30

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