KR930004427B1 - Method of checking main memory unit - Google Patents

Abstract

The method for reducing the self-test time of main memory in a computer system comprises the steps of: loading the system program in the main memory when the power is on; producing the control signal to enter the multi-bit test mode; writing the whole data with a word unit into the main memory; executing the read operation with a word unit and detecting the error; executing the refresh cycle and loading the user program into the main memory and returning to the normal state.

Description

How to reduce self test time of main memory

1 is a flow chart of a conventional self-test method of main memory.

2 is a block diagram of a system to which the present invention is applied.

3 is a flowchart of a method for reducing a self-test time of a main memory device according to the present invention.

* Explanation of symbols for main parts of the drawings

1: MPU 2: RAC

3: ACG 4: DCSG

5: DC 6: main memory

The present invention relates to a method for shortening the long-term test time of a main memory device in a system, and more particularly, to a method for shortening the self-test time of a main memory device of a system using a test mode of a DRAM (Dynamic Random Access Memory).

In general, most devices that use a microcomputer or a microprocessor unit (MPU) to control or measure have a DRAM as main memory.

When the power is turned on for the operation of the system, all the devices in the system are reset and the system program stored in the ROM (Read Only Memory) is also reset, calling the first address of the system program and executing the commands written in the address. Run as At this time, some basic elements for system operation and abnormality of main memory composed of DRAM are checked.

1 is a flow chart of a conventional self-test method of the main memory. Referring to FIG. 1, a conventional method for confirming an abnormality of a main memory device composed of DRAMs is as follows.

When the power is turned on, the system program is loaded from the ROM into the main memory (10) and the write cycle of the DRAM is used to change the address from the LSB (Least Significant Bit) to the MSB (Most Significant Bit) or MSB to LSB in order. A write operation and an error search operation are performed (20, 30, 40, 50, 60), and a user program is loaded (70), and a program to be loaded and executed is executed (80, 90, 100).

However, since writing and reading of data is repeated in word units, the time required for self test is

Where tc is the sum of the time spent writing and reading the main memory and the data verification time.

Therefore, as the capacity of the main memory of the system increases, the self test time of the system also increases.

Disclosure of Invention The present invention devised to solve the above problem is to provide a method for shortening a self-test time of a main memory device of a system consisting of DRAM using a test mode of DRAM.

The present invention devised to achieve the above object is a micro process unit (MPU), an address control generator (ACG), a refresh address controller (RAC), a DRAM control signal generator (DCSG), a data controller (DC), and a DRAM array A method for reducing the self-test time of a main memory of a system including a main memory, comprising: a first step of loading a system program and generating a control signal for entering a multi-bit test mode and entering a multi-bit test mode; A second step of performing write operations on all data in word units while generating addresses in sequence, a third step of performing read operations in word units while generating addresses in order and searching for errors, and a refresh cycle (refresh) Cycle) to load the user program and return to the normal state.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a configuration diagram of a system to which the present invention is applied, 1 is a micro process unit (MPU), 2 is a refresh address controller (RAC), 3 is an address control generator (ACG), 4 is a DRAM control signal generator (DCSG), 5 denotes a data controller (DC), and 6 denotes a main memory device.

The system to which the present invention is applied is composed of an MPU 1, a RAC 2, an ACG 3, a DCSG 4, a DC 5, and a main memory 6, as shown in FIG.

The main memory device 6 is composed of a DRAM array, and the RAC 2 functions to generate an address for holding data of the DRAM array of the main memory device. The MPU 1 performs a function of searching using its own signature constant or externally given characteristic data and outputting the result, and the ACG 3 stores the address given by the MPU 1 in the main memory. A function of separating columns and rows into the DRAM array of the device 6 is performed. In addition, the DCSG 4 performs a function of reading and writing the DRAM array of the main memory 6 under the control of the MPU 1, and enters a signal required for main memory self-test, that is, a test mode of DRAM. It is a function to generate a control signal.

3 is a flowchart of a method for shortening a self test time of a main memory device according to the present invention.

When the power is turned on in the system, the system program is loaded into the main memory 6, and the control signal necessary for entering the multi-bit test mode is generated to enter the multi-bit test mode (200, 210). ).

As the normal write cycle enters, the LSB to MSB or the MSB to LSB writes the address in word order (220, 230), and then the LSB to MSB or MSB to LSB in order. While performing a read operation in word units while searching for air (240, 250, 260). If an error occurs in the error search step, an error flag is generated and the error search is stopped (270).

After the error search, a refresh cycle, which is the basic cycle of the DRAM, is rotated, and a user program (DOS) is loaded to recover the DRAM internal circuit from the set state to the multi-bit test mode and return to the normal state (280 and 290).

The present invention configured and operated as described above reduces the test time to 1/8 when using the main memory device composed of 4M DRAM, and reduces the test time to 1/16 when using the main memory device composed of 16M DRAM to shorten the self-test time of the main memory device. It works.

Claims (1)

Micro Process Unit (MPU) (1), Address Control Generator (ACG) (3), Refresh Address Controller (RAC) (2), DRAM Control Signal Generator (DCSG) (4), Data Controller (5), And a main memory device of the system comprising a main memory device (6) comprising a DRAM array; A first step of loading a system program, generating a control signal for entering the multi-bit test mode, and entering a multi-bit test mode, and a second step of performing write operations on all data in word units while generating addresses in order. A third step of performing a read operation in word units while generating an address in order, searching for an error, and a fourth step of turning a refresh cycle and loading a user program to return to a normal state. Method for reducing the self-test time of the main memory device, characterized in that.