JPH04241653A - Error correcting system - Google Patents

Abstract

PURPOSE:To lower the probability of occurring such a case that overlapping of one-bit errors results in a fatal two-bit error. CONSTITUTION:A used bank discriminating section 11 discriminates banks in a storing section used by a processor from the contents of requests in a request buffer 10. A bank busy managing section 15 manages the used state of each bank in the currently used storing section under the control of a main control section 14. A test request generating section 12 generates a test readout request to a vacant bank so that the request does not conflict with the access from the processor by discriminating the used state of each bank in the storing section from the outputted results of the discriminating section 11 and managing section 15. A write request generating section 13 generates a write request for correction when the section 13 detects a correctable error as a result of test readout.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an error correction method, in particular,
This invention relates to an error correction method for storage devices.

0002

[Prior Art] Conventionally, this type of error correction method includes a method in which corrective writing is performed when an error is detected during normal access, a method in which error detection and corrective writing is performed during a refresh cycle, and a patrol method. There is a method of periodically performing error detection and correction writing from a processor or the like.

0003

[Problems to be Solved by the Invention] The conventional error correction method described above may require a relatively long time from the occurrence of an error until the location of the error occurrence can be detected, and the generation of radiation may occur. In a bad environment such as when it is close to the source, there is a disadvantage that there is a high probability that a 1-bit error will turn into a fatal 2-bit error due to the duplication of 1-bit errors.

0004

[Means for Solving the Problems] The error correction method of the present invention includes a storage section consisting of two or more banks, a plurality of bank control sections that control the banks, and data between the plurality of bank control sections and a processor. A main control unit that controls transfer and each bank control unit and bank busy management unit, a request buffer that receives and holds requests from the processor, and determines the bank of the storage unit used by the processor based on the request contents in the request buffer. A bank busy management unit that manages the current usage status of each bank in the storage unit under the control of the bank usage determination unit and the main control unit, and a bank busy management unit that manages the usage status of each bank in the storage unit based on the output results of the bank usage determination unit and the bank busy management unit. A test request generation unit that monitors the situation and generates a test read request to an empty bank so as not to conflict with processor access, and a write request that generates a write request for correction when a correctable error is detected by test read. The generator includes a generating section.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In normal access from a processor, the storage device 1 receives request information such as a request, address, and command from the processor via the input terminal 2 and output terminal 3, and also transfers write data and read data. Request information input from the input terminal 3 is held in the request buffer 10, and when the main control unit 14 can execute the request, the request information is stored in the main control unit 14.
passed to.

The main control unit 14 includes bank control units 30 to 33 that decode and use commands of received requests.
It outputs addresses, control signals, write data, etc. to the bank controllers, and receives read data from the bank controllers 30 to 33 during reading. Further, the main control unit 14 controls the bank busy management unit 15 for busy management of each bank (0) to (3) 40 to 43 of the storage unit currently in use in response to a request.

The bank (0) to (3) control units 30 to 33 respectively store data in the banks (0) to (3) storage units 40 to 43 of the storage unit based on control signals from the main control unit 14. It performs writing, reading, and error detection/correction of read data, and outputs a report to the write request generating section 13 when a correctable error is detected. After receiving the report, the write request generating section 13 generates a write request for executing corrective writing and outputs it to the main control section 14 .

[0009] In the main control unit 14, the request buffer 1
The bank control unit (30 to 30) that detected the error interrupts the reception of request information from
33), and the bank control section receiving the control signal executes correction writing to each storage section.

On the other hand, when accessing from a processor, not all banks 40 to 43 of the storage section are always in use, and some banks are temporarily in a free state waiting for a request. In order to perform test reading to this bank so as not to conflict with processor access, the used bank determination unit 11 checks the request information in the request buffer 10 and determines which banks are not used by the processor, and then sends the test request generation unit 12 Output.

The test request generation section 12 generates a test request for a bank that will be free for more than the time required to execute the test read based on the output of the used bank determination section 11 and the value of the bank busy management section 15, and outputs it to the main control section 14. . now,
When the free bank is the bank (1) storage section 41, the main control section 14 outputs a control signal for test reading to the bank (1) control section 31. The bank (1) control unit 31 executes test reading of the bank (1) storage unit 41 according to the received control signal, checks the read data for errors, and issues an error report if a correctable error is detected. It is output to the write request generation section 13.

Upon receiving the report, the write request generation section 13 generates a write request for executing corrective writing and outputs it to the main control section 14. The main control unit 14 interrupts the reception of request information from the request buffer 10 and the test request from the test request generation unit 12, and controls correction writing to the bank control unit 3 where the error has been detected.
1, and upon receiving the control signal, the (1) control unit 31 executes correction writing to the bank (1) storage unit 41. The test read address is the test request generator 12
is generated by a method such as increment,
Each occurs corresponding to each bank.

[0013]

As explained above, the present invention immediately executes a correction write when a correctable error is detected during processor access, and also executes a test read to a free bank storage section to detect a correctable error. Immediately executing corrective writing upon detection has the effect of lowering the probability that a 1-bit error will overlap and become a fatal 2-bit error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

10 Request buffer 11 Used bank determination section 12 Test request generation section 13 Write request generation section 14 Main control section 15 Bank Busy Management Department

Claims (1)

[Claims] Claim 1: A storage unit consisting of two or more banks;
A main control unit that transfers data between each bank control unit and the processor and controls each bank control unit and bank busy management unit, a request buffer that holds requests from the processor, and a bank busy management unit that manages bank busy. , a used bank determination unit based on a request from the processor, and a test request generation unit that generates a test read request for a bank that is not used by the processor and is currently free based on the output results of the bank busy management unit and the used bank determination unit. and a write request generating section that outputs a correction write request to a main control section when a correctable error is detected.