JPS63308795A - Dynamic ram - Google Patents

Abstract

PURPOSE:To prevent the storage of the software error by a simple external control signal such as a refresh signal or the like by using an ECC circuit so as to detect and correct error of plural memory cells connecting to one word line to be driven in a DRAM during the refresh period. CONSTITUTION:A signal Ref14 is sent to a control circuit 13 during the refresh period. A decoder 6 selects a memory cell M11 by using a control signal to apply exclusive OR of M11-M13, the information of a horizontal parity cell H1 selected by the circuit 7 is detected by the circuit 11 for horizontal error. Similarly, the information of vertical parity cell V1 selected by a vertical parity selection circuit 8 is compared by a check circuit 12 to detect the vertical error. The error detection information in the vertical direction is held in the circuit 18, a correction circuit 16 compares the result of the check circuit 11 to correct the error and a write circuit 15 writes a signal to the cell M11. Similar processing is applied as to other memory cells M21, M31 and the operation is repeated for each refresh period to detect and correct the error by the ECC circuit periodically as to all memory cells.

Description

[Detailed description of the invention] Industrial applications The present invention relates to dynamic RAM.

Conventional technology In recent years, dynamic RAM (hereinafter referred to as DRAM)
Development is underway to increase capacity, but as memory cells become smaller, soft errors, where the accumulated charge in a memory cell is reversed by alpha particles incident on the cell, have become an important problem.

One method for reducing soft errors is error detection and correction (hereinafter referred to as ECC).
and Correction) circuit. Same-Ch
By adding an ECC circuit to the IP, it becomes possible to automatically detect and correct bit errors caused by soft errors.

The mainstream method for implementing an ECC circuit in a DRAM is to encode a plurality of data stored in memory cells located on the same word line. The basic configuration of a DRAM using such means is shown in FIG. Memory cell 3 connected to word line 1 driven during read operation and pit line 2 selected by select circuit θ
Error detection and error correction are performed on the data. If an error is detected, the corrected data is read from the input/output circuit 9, and the rewrite circuit 8 writes the corrected data into the memory cell 3 in which the data error has occurred. In this case, since reading is performed on any memory cell 3, error detection and error correction by the ECC circuit 7 are not performed periodically on all memory cells 3.

Problems to be Solved by the Invention In order to prevent the accumulation of soft errors, it is necessary to periodically perform error detection and error correction on all memory cells. Error detection and correction operations conventionally occur during data read or refresh cycles. However, since the data selected during the data read cycle is arbitrary, this method is inadequate in preventing the accumulation of soft errors in all bits. Also, normal D
During the RAM refresh cycle, each time one word line is selected, one piece of data is selected and an ECC operation is performed. Since it takes a considerable amount of time to perform this process, this is still disadvantageous in terms of preventing the accumulation of soft errors.

The present invention was made to solve this problem, and when a single word line is accessed during normal refresh, multiple pieces of data on the same word line are simultaneously selected.
The purpose of this invention is to provide a RAM capable of performing ECC operations.

Means for Solving the Problems In order to solve the above problems, the present invention provides a select method for selecting one piece of data from among the data of all memory cells connected to any one driven word line. It has a refresh control circuit that sends a selection signal to the select circuit for sequentially selecting multiple pieces of data during the refresh period, and periodically performs error detection and error correction for all 7 mol cells. It has a structure.

According to the above-described structure, the refresh control signal is sent from the refresh control circuit to the select circuit by applying a control signal from the outside, and the refresh control signal is sent from the refresh control circuit to the select circuit, and a plurality of memory cells on the same word line driven during the refresh cycle are connected to each other. Data is selected sequentially, and the ECC circuit performs error detection and error correction. If an error is detected, the rewrite circuit inserts the corrected data into the memory cell where the error occurred, so error correction and error detection can be performed periodically on the data in all memory cells. can.

Example Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, 1 is a word line, 2 is a bit line B1 to Bn
, 3 is a memory cell, 4 is a horizontal parity cell, 6 is a vertical parity cell, 6 is a column decoder, 7 is a select circuit for horizontal parity, 8 is a select circuit for vertical parity, 9 is a horizontal parity cell, select circuit, 1o is a vertical Parity cell select circuit, 11 horizontal parity check circuit, 12
1 is a vertical parity check circuit, 13 is a refresh control signal, 14 is a refresh signal, 16 is a rewrite circuit, 1
6 is an error correction circuit, 17 is an input/output circuit, and 18 is a data holding circuit. FIG. 2 shows an example of a memory cell 3, a horizontal parity cell 4, and a vertical parity cell 6 connected to the word line 1. A matrix as shown in FIG. 3 is made to correspond to the memory cell 3, and a horizontal/vertical parity method is applied.

The operation of the DRAM with ECC circuit configured as above will be explained below.

During refresh, an arbitrary word line 1 is driven, and all memory cells 3, horizontal parity cells 4, and vertical harness cells 6 connected to the word line 1 are refreshed.

During the refresh period, the refresh signal 14 is sent to the refresh control circuit 13 configured with a counter, for example, and the refresh control signal is sent to the column decoder 6, the horizontal parity select circuit 7, the vertical parity select circuit 8, and the horizontal parity cell select circuit. The signal is sent to the circuit 9, the vertical parity cell select circuit 10, and the data holding circuit 18. The column decoder 6 that received the refresh control signal
Data in a plurality of memory cells 3 is sequentially selected during the refresh period. When memory cell M11 is selected,
In the horizontal parity select circuit 7, the memory cell M112
The exclusive OR of M122M13 is performed, and the horizontal parity cell H1aL selected by the horizontal parity select circuit A is compared with the result by the horizontal harness check circuit 11 to detect errors in the horizontal direction. Similarly, the vertical parity select circuit 8 performs an exclusive OR of memory cells '11 + M211M31, and the result and the data of the vertical parity cell v1 selected by the vertical parity select circuit 8 are sent to the vertical parity check circuit 12. to detect errors in the vertical direction.

The vertical error detection data is held in the data holding circuit 18 and sent to the error correction circuit 16. Here, if an error is detected in the horizontal or vertical direction by comparing it with the horizontal error detection data from the horizontal parity check circuit 11, the error is corrected by the error 9 correction circuit 16, and the rewriting circuit 16, the corrected data is written into the memory cell M11.

Next, when memory cell M21 is selected by column decoder 6, a horizontal error is detected by similarly comparing the exclusive OR result of memory cell M21 + "221" 23 with the data of horizontal parity cell H2. do. The error p detection data in the vertical direction is held in the data holding circuit 18, and the error correction circuit 16 can compare the error detection data in both the horizontal and vertical directions. If an error is detected as described above, it is corrected and correct data is rewritten into the memory cell M21.

Subsequently, 1 is selected in the memory cell by the column decoder θ, and at the same time, a horizontal error 9 is detected by comparing the result of the exclusive OR of the memory cells M311M32pMss with the data of the horizontal parity cell H3. Error detection data in the vertical direction is held in the data holding circuit 18, and error detection data in both the horizontal and vertical directions is stored in the error correction circuit 1.
6 can be compared. Similarly, if an error is detected, corrected correct data is rewritten into the memory cells.

Therefore, error detection and error correction can be sequentially performed on a plurality of memory cells by the ECC circuit during the refresh period. This operation is shown in FIG. An arbitrary word line is selected by the RAS signal and the row address signal, and the data of all memory cells connected to the selected word line are transferred to the bit lines B1 to B1 . It is refreshed by being amplified and amplified. on the other hand,
The refresh signal Ref is sent to a refresh control circuit 13 composed of, for example, a counter. A refresh control signal is sent from the refresh control circuit 13 to the column decoder 6, and the column decoder 6 sequentially selects data on a plurality of bit lines B1 to B3.

On the other hand, horizontal harness cell select circuit 9 sends horizontal harness cell data to horizontal parity check circuit 11 via bit lines B10=B12, and horizontal error data is sequentially sent to error correction circuit 16. The data of the vertical parity cell is sent to the vertical parity check circuit 12 through the bit line B13, held in the vertical error data holding circuit 18, and sent to the error correction circuit 16, where it is combined with the horizontal error data described above. Comparison, error detection, and error correction are performed. For example, if an error is detected in the memory cell M31 connected to the bit line B3VC, the data is inverted and correct data is output from the error correction circuit 7. The corrected data passes through the rewrite circuit 16 and the column decoder 6, the data on the bit line B3 is inverted, and the data in the memory cell M31 in which the error has occurred is corrected.

By repeating this operation every refresh period, the ECC circuit can periodically perform error detection and error correction for all memory cells.

In this way, during the refresh period, the column decoder 6, the horizontal parity select circuit 7, the vertical parity select circuit 8, the horizontal harness cell select circuit 9, the vertical harness cell select circuit 1o, and the data retention By controlling the circuit 18, the ECC circuit can sequentially perform error detection and error correction on data in a plurality of memory cells during the refresh period.

In addition, in this embodiment, vertical error detection data is held in the data holding circuit 18, so there is no need to perform vertical error detection every time a memory cell is selected, so power consumption is reduced. There is little increase in the amount of damage, the inspection speed is fast, and it can be carried out efficiently.

Since error detection and error correction are performed on data in multiple memory cells during each refresh period, errors in each cell are It is possible to shorten the cycle of detection and error correction operations.

Furthermore, if error detection and error correction are performed on an appropriate number of memory cells during the refresh period, there is an effect that error detection and error correction can be performed while keeping the increase in dead time small. Therefore, accumulation of soft errors can be prevented and reliability of the DRAM can be improved.

Effects of the Invention As described above, the present invention provides all one word line connected to one driven word line during the refresh period in a DRAM.
Since the ECC circuit sequentially performs error detection and error correction on multiple mol cells, the accumulation of soft errors can be prevented by simple external control signals such as a can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an ECC circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a memory cell connected to the word line 1 in FIG. 1, and FIG. An explanatory diagram showing a matrix expanded horizontally and vertically, FIG. 4 is a timing diagram of the circuit operation in FIG. 1,
FIG. 6 is a block diagram of a conventional ECC circuit. 1... Word line, 2... Bit line B1
~Bn, 3...Memory cell, 4...Horizontal parity cell, 5...Vertical parity cell, 6
...Column decoder, 7...Horizontal parity select circuit, 8...Vertical parity select circuit, 9...Horizontal parity cell select circuit, 10. ... Vertical parity cell selection circuit, 11 ... Horizontal parity check circuit, 12 ...
... Vertical parity check circuit, 13 ... Refresh control signal, 14 ... Refresh signal,
16... Rewriting circuit, 16... Error correction circuit, 17... Input/output circuit, 18...
...Data retention circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure Ht ~ H3 - Horizontal parity Vt - V3 - One season parity Mr + ~ M

Claims (1)

[Claims] A select circuit selects one piece of data from among data of all memory cells connected to any one driven word line, and a select signal for sequentially selecting a plurality of pieces of data during a refresh period. It has a refresh control circuit that sends it to a select circuit, and an ECC circuit that performs error detection and error correction on one selected piece of data, and when an error is detected in the data, the corrected data is sent to the memory where the data error occurred. A dynamic RAM characterized by being equipped with a rewrite circuit for writing into cells.