JPH0831280B2 - Method and apparatus for semiconductor memory device refresh and data inspection - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention incorporates a self-error data detection and correction circuit (ECC circuit), inspects stored data of a specific memory cell for each refresh operation, and detects an error when the error is detected. The present invention relates to a semiconductor memory device having a patrol function of rewriting correct data.

2. Description of the Related Art Recently, semiconductor memory devices, especially MOS dynamic random access memory (D-RAM), have been integrated in 16K, 64K, 256
As it goes to K, 1M, the storage capacity per memory cell decreases, and as a result, the soft error occurrence rate due to α rays increases. A D-RAM incorporating a self-error data detection and correction circuit (ECC circuit) in order to relieve a bit error due to such a soft error is already known (see T. Mano et al. “Circuit”). Teqniques for a
VLSI Memory ", IEEE Jaurnal of Solid-state circuit
s, Vol SC-18, No.5, PP.463-469).

In a semiconductor memory device having a built-in ECC circuit, a plurality of cell data at a specific address of a memory cell array are classified into a horizontal group and a vertical group by a specific method, and parity check information of each horizontal group and each vertical group is parity checked. A so-called horizontal-vertical method of storing in a dedicated cell array is adopted. In such a system, when the data of a certain memory cell is read, the respective parities of the horizontal cell and the vertical cell belonging to this memory cell are calculated and stored in the calculated parity and the parity check cell array. The data read from the memory cell is corrected according to the result of comparison with the corresponding parity.

It is executed in synchronization with the refresh operation of the operation of the ECC circuit described above. That is, the ECC patrol is executed by the read-modify-write mode in which the data stored in the specific memory cell is inspected along with the refresh operation and correct data is rewritten when an error is detected. For example, for a plurality of memory cells arranged in a matrix, a refresh address counter sequentially specifies rows (word lines) to perform a refresh operation, and an ECC column address counter performs a column operation to perform an ECC patrol. Specify (bit line pairs) sequentially. In this case, if the refresh cycle is 8 ms and the bit width of one column is 1024 (1 Mbit RAM), the patrol cycle is about 8 s. That is, the ECC column address counter is incremented by +1 every refresh cycle. Therefore, one column (10
The correct data is written by checking the stored data (24 bits), and as a result, the ECC patrol of all memory cells of 1 Mbit RAM is refresh cycle × 1 row bit width 1024
= It takes about 8 seconds.

Problems to be Solved by the Invention In the above-described method of performing the ECC patrol in the refresh mode, the time required for the refresh operation is
There is a problem that the time required for the refresh operation in the D-RAM that does not include the C circuit is remarkably long, resulting in a remarkably long refresh overhead. This is because the refresh operation in the D-RAM that does not include the ECC circuit only gives the same initial voltage level to the memory cell at the time of writing by the word line selection by the refresh address counter and the operation of the sense amplifier thereafter. While it is not necessary to drive the output circuit, the write circuit, etc., the refresh operation that also performs the ECC patrol in the D-RAM with the built-in ECC circuit, in addition to the refresh operation described above, checks the stored data and drives the write circuit. Because it is necessary to do. During the refresh operation period, the normal read / write operation of the memory cell is performed.
This is a non-accessible time during which write access is not possible, that is, refresh overhead, and shortening such refresh overhead is a problem for improving the utilization efficiency of the storage device.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a refresh and data inspection method and device for a semiconductor memory device having a built-in ECC with a short refresh overhead.

In order to solve the above problems, the present invention performs a refresh operation in units of one refresh cycle in which a refresh cycle for refreshing a plurality of memory cells arranged in a matrix for each row is repeated for a bit width of one column. In the case where the bit width of one row is continuously repeated, when the refresh operation is performed, when the memory cells belonging to a certain row are refreshed, the reading for stored data inspection is performed on the memory cells belonging to a certain column. At the same time, the above-described operation of writing correct inspected data obtained in the previous refresh cycle to memory cells belonging to another column in a certain row during the refresh operation is sequentially performed over a plurality of refresh cycles. A method for refreshing a semiconductor memory device and a data inspection method are provided.

On the other hand, the present invention includes a plurality of memory cells arranged in a matrix, and further, in a unit of one refresh cycle in which a refresh cycle for refreshing the memory cells row by row is repeated for a bit width of one column. Refresh means for continuously repeating a refresh operation for one column bit width, column designating means for sequentially designating the memory cells every two columns, and a row refreshed by the refreshing means and designated by the column designating means. A storage data inspection circuit for reading out the storage data of the memory cell belonging to one of the two selected columns and inspecting it, and an inspected data storage means for storing the inspected data based on the output of this storage data inspection circuit. And the stored contents obtained during the previous refresh cycle stored by this inspected data storage means. Based on the above, there is provided an inspected data writing means for writing inspected data to a memory cell belonging to another column designated by the column designating means, the row being refreshed by the refreshing means. A refresh and data inspection device for a semiconductor memory device is provided.

Operation According to the above-mentioned means, it is not necessary to complete all the read data inspection and write operations of the inspection target column during the refresh operation, as long as the inspection is completed before the next refresh operation for the same row is performed. Because it ’s good, 1
The refresh operation period for each row is prevented from becoming long due to the ECC operation. In a really preferred embodiment, the write operation can be performed in the early stage of the refresh operation, that is, the refresh operation can be performed by the early write mode, and the data is rewritten after the read operation as in the conventional case. -It is different from the write mode, and it is not necessary to add the time required for writing for data correction.

Thus, in the present invention, two memory cells are selected while refreshing one row of the plurality of memory cells, and data is read from one of these memory cells and at the same time. For another memory cell,
Since the data is rewritten, the time required for error detection and data rewriting can be shortened.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing an embodiment of a semiconductor memory device having an ECC circuit according to the present invention. In FIG. 1, reference numeral 1 is, for example, a 1 Mbit memory cell array,
Here, a folded bit line structure is assumed. That is, as shown in FIG. 2, word line pair WL
_i (i = 0,1, ..., 1023) and bit line pair BL _j , ▲ ▼ _j (j
, 0, 1, ..., 1023), one memory cell MC is provided. In FIG. 1, 2 is a parity check cell array, 3 is a sense amplifier provided for each bit line pair, 4 is a column I / O switch circuit, and 5 is a memory cell array and a parity check cell array 2. A selector circuit, 6 is a row decoder / driver for selecting a word line, and 7 is a column decoder. An error detection circuit 8 is a horizontal parity check circuit for checking the parity of the horizontal cell data group, a vertical parity check circuit for checking the parity of the vertical cell data group, and a horizontal parity P _H read from the parity check cell array 2. And an exclusive OR circuit for detecting a match or a mismatch between the horizontal parity P _H ′ output by the horizontal parity check circuit, the vertical parity P _V read from the parity check cell array 2 and the vertical parity calculated by the vertical parity check circuit. It is composed of an exclusive OR circuit for detecting a match or a mismatch with the parity P _V ′, and an AND circuit connected to the two exclusive OR circuits. Therefore, when an error is detected in the read data, the error detection circuit 8 produces the output DET. As a result, the error correction circuit 9 performs error correction by inverting the read data D, and sends it to the subsequent stage. of course,
If no error is detected in the read data, the error correction circuit 9 sends the read data D, to the subsequent stage without inverting it.

In the read mode, the output data of the error correction circuit 9 is amplified by the amplification stage 10, which is sequentially controlled by the clocks φ ₁ , φ ₂ , and φ ₃ .
Output data Dout is sent out via 11 and 12, but in the refresh mode, clock φ ₁ ,
φ ₂ and φ ₃ are not driven, and as a result, the output data of the error correction circuit 9 is not sent to the outside. That is, in the refresh mode, the output data of the error correction circuit 9, that is,
Correct data is stored in the shift register 13 and sequentially written again in the memory cell array 1 via the column I / O switch circuit 4. In this case, the shift register
Reference numeral 13 has a capacity for one column of the memory cell array 1, for example, 1024 bits. Therefore, correct data in the shift register 13 is written in one column of the memory cell array 1 every refresh cycle.

A multiplexer 14 multiplexes external row address signals A _{0 to} A ₉ ( ₀ to ₉ ) from a row address buffer (not shown) and the address signal of the refresh address counter 15. In other words, the external row address signals A _{0 to} A ₉ ( ₀ to ₉ ) are supplied to the row decoder / driver 6 by the multiplexer 14 in the normal read / write mode, and by the multiplexer 14 in the refresh mode. The address signal of the refresh address counter 15 is supplied to the row decoder / driver 6.

A multiplexer 16 multiplexes the external column address signals A ₀ ′ to A ₉ ′ counters ( ₀ ′ to ₉ ′) from the column address buffer (not shown) and the address signals of the ECC address counter 17. That is, in the normal read / write mode, the external column address signals A ₀ ′ to A ₉ ′ ( ₀ ′ to ₉ ′) are supplied to the column decoder 7 by the multiplexer 16, and in the refresh mode,
The address signal of the ECC address counter 17 is supplied to the column decoder 7 by the multiplexer 16.

18 is a refresh mode control circuit, which is a control signal
By generating a C ₁ -C _6, a multiplexer 14, a refresh address counter 15, a multiplexer 16, ECC
The address counter 17, shift register 13, sense amplifier 3, and column I / O switch circuit 4 are controlled. That is, in the refresh mode, the multiplexer 4 selects the refresh address counter 15 and the multiplexer 16 selects the ECC address counter 1.
Select 7 to activate the sense amplifier 3. In addition, the refresh address counter 15
Is incremented by 1 and the shift register 13 is shifted in synchronism with it, and the column I / O switch circuit 4
Switch. Furthermore, the ECC address counter 17 is incremented by +1 each time the refresh operation of the bit width (1024) of one column is completed, that is, every one refresh cycle.

The data buses D, D in FIG. 1 are used not only in the normal read / write mode but also in the ECC patrol data read in the refresh mode.
On the other hand, the data buses D _ECC and _ECC are used for rewriting the ECC patrol data in the refresh mode. Further, in FIG. 1, a circuit for write control for a normal write mode is omitted.

FIG. 2 is a partial circuit diagram including the column I / O switch circuit 4 of FIG. In FIG. 2, each bit line pair has 2
A pair of column switches and an AND circuit are provided. For example, for the bit line pair BL _j , ▲ ▼ _j , the transistors Q ₁ , Q ₂ and the second
Are provided with transistors Q ₃ and Q ₄ as column switches and an AND circuit G, and bit line pair BL _j-1 , BL.
▼ _j-1 is provided with transistors Q ₁ ′ and Q ₂ ′ as first column switches, transistors Q ₃ ′ and Q ₄ ′ as second column switches, and an AND circuit G ′. In this case, the first column switch, for example
Q ₁ and Q ₂ are a bit line pair BL _j , and ▲ ▼ _j is a data bus D,
The second column switch, for example, Q ₃ , Q ₄ is for connecting the bit line pair BL _j , ▲ ▼ _j to the data bus D _ECC , _ECC .

In the normal read or write mode, the control signal C ₆ from the refresh mode control circuit 18 is set to the low level, so that the column decoder 7 causes the first column belonging to the bit line pair BL _j , ▲ ▼ _j , for example. Only the switch is driven, but in refresh mode,
Since the control signal C ₆ from the refresh mode control circuit 18 is set to the high level, the column decoder 7 causes, for example, the first column switch belonging to the bit line pair BL _j , ▲ ▼ _j and the previous bit line pair BL _{j. -1} , ▲ ▼ _j-1 second belonging to
Both column switches are driven simultaneously. As a result, correct data from the shift register 13 can be obtained for the memory cell at the column address immediately before the column address of the memory cell to be inspected in the refresh mode, that is, for the memory cell subjected to the previous refresh cycle inspection. Will be written.

Next, the refresh operation with the ECC patrol function by the circuit of FIG. 2 including FIG. 1 will be described. At the beginning,
10 belonging to bit line pair BL _j-1 , ▲ ▼ _j-1 by one refresh cycle consisting of 1024 refresh cycles
It is assumed that 24 memory cells have been tested, so that the correct data for these memory cells is stored in shift register 13. In the next refresh cycle, the refresh address counter 15 is incremented by +1 and the shift register 13 is shifted by 1 bit.
The address counter 17 is incremented by +1. In this case, the refresh address counter 15 and ECC for the address counter 17 are both 2 ^decimal cyclic counter. Next, when the refresh address counter 15 and the ECC address counter 17 are selected by the multiplexers 14 and 16 and both the sense amplifier 3 and the column I / O switch circuit 4 are driven (the control signals C ₅ and C ₆ are both high level). When all the memory cells connected to the word line WL ₀ are refreshed, the data from the memory cells connected to the word line WL ₀ and the bit line BL _j are selected. The data is read to the data bus D via the first column switches Q ₁ and Q ₂ . That is, the read operation as the ECC patrol function for this memory cell is performed. At this time, the cell to be refreshed is subjected to the horizontal / vertical parity check. However, the cell immediately before the column address (column address) of the cell is a target for writing the correct data in this cycle, and therefore holds the correct data. Not necessarily. Therefore, as the data used for the parity check, it is necessary to use not the read data from the cell itself but the corrected data stored in the register for the cell in the column before the first address. As a result,
When an error is detected in the read data of the memory cell, the error detection circuit 8 and the error correction circuit 9 perform error correction, and then correct data is obtained in the shift register 13.
Is stored in the first bit of. When no error is detected, the data is not corrected and the shift register 13 remains unchanged.
Is stored in the first bit of. At the same time, the control signal
The bit line pair BL _j-1 AND circuit G is opened for a high level of C _6, ▲ ▼ second column switch Q ₃ belonging to the _j-1 ', Q _4' respective bit lines by BL _j-1 , ▲ ▼ _j-1 is connected to the data bus D _ECC , _ECC . As a result, at the same time as the above-mentioned read operation as the ECC patrol function,
For the memory cell at the previous column address, that is, the memory cell connected to word line WL ₀ and bit line BL _j-1
A write operation is performed as an ECC patrol function. That is, the 1024th bit (last bit) of the shift register 13
From the data bus D _ECC , _ECC to the word line WL ₀ and the bit line BL _j-1 via the second column switches Q ₃ ′ and Q ₄ ′.
It is written to the memory cells connected to and, which ends the first refresh cycle.

Next, in the refresh cycle, the refresh address counter 15 is incremented by +1 and the shift register 13 is shifted by 1 bit, and the ECC address counter 17 is not incremented by +1. Next, the refresh address counter 15 and the ECC address counter 17 are selected by the multiplexers 14 and 16, and the sense amplifier 3 and the column I / O are selected.
When the switch circuits 4 are driven together, the refresh operation is performed on all the memory cells connected to the word line WL _0, and the memory cells connected to the word line WL ₁ and the bit line BL _j Data is read onto the data bus D via the selected first column switches Q ₁ and Q ₂ , that is, a read operation as an ECC patrol function for this memory cell is performed. As a result, correct data is stored in the first bit of the shift register 13. At the same time, the AND circuit G is opened due to the high level of the control signal C ₆ , and the bit line pair BL _j-1 , ▲ ▼ _j-1.
Each bit line BL _j-1 , ▲ ▼ _j-1 is connected to the data bus D _ECC , _ECC by the second column switch Q ₃ ′, Q ₄ ′ belonging to the memory cell at the previous column address, that is, A write operation as an ECC patrol function is performed on the memory cells connected to the word line WL ₁ and the bit line BL _j-1 . That is, the 1024th bit (final bit) data of the shift register 13 is transferred from the data bus D _ECC , _ECC to the word line WL ₁ via the second column switches Q ₃ ′ and Q ₄ ′.
To the memory cell connected to the bit line BL _j-1 and the second refresh cycle is completed.

When the above-described operation is repeated and 1024 refresh cycles are completed, the bit line pair BL _j and ▲ ▼ _j are connected to each other.
The ECC patrol for 24 memory cells ends.

In this way, in the refresh operation mode in the embodiment shown in FIGS. 1 and 2, the read operation as the ECC patrol function and the write operation as the ECC patrol function for the previous column address are simultaneously performed. .

FIG. 3 is a circuit diagram showing another embodiment of the semiconductor memory device of the ECC circuit according to the present invention, in which the column I / O switch circuit 4'is different from the column I / O switch circuit 4 of FIG.

The column I / O switch circuit 4'of FIG. 3 will be described with reference to FIG. 4. Only one pair of data buses are provided, and a pair of bit lines such as BL _j-1 and ▲ ▼ _j-1 has a transistor.
Q ₅ ′ and Q ₆ ′ are provided, and transistors Q ₅ and Q ₆ are provided to the bit line pair BL _j , ▲ ▼ _j . In the refresh mode, for example, the row decoder / driver 6 selects the word line WL ₀ and the column decoder 7 selects the bit line pair BL _j , ▲.
▼ _Assume that you have selected _j-1 . During the read operation (not the patrol operation), C ₆ is set to the high level, and the inverted signal ₆ thereof is set to the low level. As a result, the refresh operation without error correction on all the memory cells connected to the word line WL ₀ is performed, data from the memory cells connected to the word line WL ₀ and the bit line BL _j is Selected column switch Q ₁ , Q ₂
Read out to the data bus.

On the other hand, unlike the read operation without error correction, the refresh operation for performing the ECC patrol is periodically performed at intervals of, for example, 8 ms, and the control signal C ₆ is at a low level at this time.
₆ becomes high level, and the column decoder connects the data line to the cell of the column address that is one address before the error check target cell in refresh. Check the cell data for error checking from the read-only data bus for horizontal and vertical parity check of the ECC circuit (this is included in the selector circuit 5, and for 1 Mb, it has 32 horizontal and 32 vertical lines). Common data bus as it is sent to the circuit
Since it is not necessary to fetch data to D, D is used only for writing to the cell at the previous address. As a result, when an error is detected in the read data of the memory cell to be inspected, correct data is stored in the first bit of the shift register 13 after the error is corrected by the error detection circuit 8 and the error correction circuit 9. It When no error is detected, the data is not corrected and is stored in the first bit of the shift register 13 as it is. At the same time, the 1024th bit (final bit) of the shift register 13 is the second column switch from the data bus D _ECC and _ECC .
It is written in the memory cell connected to the word line WL ₀ and the bit line BL _j-1 via Q ₃ ′ and Q ₄ ′, that is, the cell one address before the cell to be inspected, whereby one refresh cycle is performed. finish.

Thus, also in the second embodiment shown in FIGS. 3 and 4, the same operation as that of the first embodiment shown in FIGS. 1 and 2 is performed.

Although the device having the folded bit line has been described in the above embodiments, it goes without saying that the present invention can be applied to the device having the open bit line.

Effects of the Invention As described above, according to the present invention, the refresh operation time for performing the ECC patrol function can be shortened, and therefore the refresh overhead can be shortened.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a semiconductor memory device having an ECC circuit according to the present invention, FIG. 2 is a partial circuit diagram including the column I / O switch circuit of FIG. 1, and FIG. FIG. 4 is a block circuit diagram showing an embodiment of a semiconductor memory device incorporating an ECC circuit according to the present invention, and FIG. 4 is a partial circuit diagram including the column I / O switch circuit of FIG. 1 ... Memory cell array, 2 ... Parity check cell array, 4 ... Column I / O switch circuit, 8 ... Error detection circuit (stored data check circuit), 9 ... Error correction circuit (stored data check circuit), 13 ... Shift register ( Checked data storage means), 17 ... Column decoder (column selection means).

Claims (2)

[Claims] 1. A refresh cycle for refreshing a plurality of memory cells arranged in a matrix row by row
When the refresh operation is continuously repeated for the bit width of one row with one refresh cycle repeated for the bit width of the column as a unit, when the memory cell belonging to a certain row is refreshed, the memory cell for the memory cell belonging to a certain column is stored. At the same time as reading for data inspection, correct and inspected data obtained in the previous refresh cycle is written to the memory cells in one row in the refresh operation and belonging to another column. A refresh and data inspection method for a semiconductor memory device in which operations are sequentially performed over a plurality of refresh cycles. 2. A refresh data inspection device for a semiconductor memory device comprising a plurality of memory cells arranged in a matrix, wherein a refresh cycle for refreshing the memory cells row by row is repeated for a bit width of one column.
One refresh operation in units of refresh cycle
Refreshing means that repeats continuously for the bit width of the row,
Column designating means for sequentially designating the memory cells every two columns, and storage data of memory cells belonging to one of the two columns designated by the column designating means, which is the row being refreshed by the refreshing means. A stored data inspection circuit for reading out and inspecting, an inspected data storage means for storing inspected data based on the output of the stored data inspection circuit, and a previous refresh cycle stored by the inspected data storage means. An inspected data write for writing inspected data to a memory cell belonging to another column designated by the column designating means, the row being refreshed by the refreshing means on the basis of the stored contents obtained in And a data inspection device for a semiconductor memory device, comprising: