JPS61117788A - Method and device for refreshing and data checking of semiconductor memory - Google Patents

Method and device for refreshing and data checking of semiconductor memory

Info

Publication number
JPS61117788A
JPS61117788A JP59237434A JP23743484A JPS61117788A JP S61117788 A JPS61117788 A JP S61117788A JP 59237434 A JP59237434 A JP 59237434A JP 23743484 A JP23743484 A JP 23743484A JP S61117788 A JPS61117788 A JP S61117788A
Authority
JP
Japan
Prior art keywords
column
data
correcting circuit
refreshing
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59237434A
Other languages
Japanese (ja)
Other versions
JPH0831280B2 (en
Inventor
Masao Taguchi
Yoshihiro Takemae
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59237434A priority Critical patent/JPH0831280B2/en
Publication of JPS61117788A publication Critical patent/JPS61117788A/en
Publication of JPH0831280B2 publication Critical patent/JPH0831280B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To shorten a refresh overhead by checking memory data of a memory cell of an optional row in a column in refreshing operation and writing already- checked correct data on a cell of other column.
CONSTITUTION: When an error is detected in read data, a detecting circuit 8 generates output DET, and thereby, a correcting circuit 9 inverts read data D, -D and makes error correction and sends out to the succeeding stage. In a reading mode, output data of the correcting circuit 9 is sent out to the outside through amplifier stages 10W12 controlled by clocks ϕ13. On the other hand, in a refreshing mode, ϕ13 are not driven, and accordingly, an output of the correcting circuit 9 is not sent to the outside. At this time, an output of the correcting circuit 9 is stored in a shift register 13, and correct data in the register 13 are written on one column of a memory cell array 1 at every refresh period through a column I/O switch.
COPYRIGHT: (C)1986,JPO&Japio
JP59237434A 1984-11-13 1984-11-13 Method and apparatus for semiconductor memory device refresh and data inspection Expired - Lifetime JPH0831280B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59237434A JPH0831280B2 (en) 1984-11-13 1984-11-13 Method and apparatus for semiconductor memory device refresh and data inspection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59237434A JPH0831280B2 (en) 1984-11-13 1984-11-13 Method and apparatus for semiconductor memory device refresh and data inspection

Publications (2)

Publication Number Publication Date
JPS61117788A true JPS61117788A (en) 1986-06-05
JPH0831280B2 JPH0831280B2 (en) 1996-03-27

Family

ID=17015298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59237434A Expired - Lifetime JPH0831280B2 (en) 1984-11-13 1984-11-13 Method and apparatus for semiconductor memory device refresh and data inspection

Country Status (1)

Country Link
JP (1) JPH0831280B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210026201A (en) 2019-08-29 2021-03-10 삼성전자주식회사 Semiconductor memory devices, memory systems including the same and methods of controlling repair of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5677985A (en) * 1979-11-26 1981-06-26 Toshiba Corp Semiconductor memory device
JPS5862891A (en) * 1981-10-09 1983-04-14 Fujitsu Ltd Memory rewrite system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5677985A (en) * 1979-11-26 1981-06-26 Toshiba Corp Semiconductor memory device
JPS5862891A (en) * 1981-10-09 1983-04-14 Fujitsu Ltd Memory rewrite system

Also Published As

Publication number Publication date
JPH0831280B2 (en) 1996-03-27

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term