JPS63214841A - Control memory error correcting control system - Google Patents

Abstract

PURPOSE:To prevent the limit of a clock cycle by generating the updating suppressing signal of a micro-instruction register, executing the correcting sequence, delaying one clock cycle, generating the action suppressing signal of an arithmetic circuit and releasing both signals after the error is corrected, when a correctable error is detected at a special field. CONSTITUTION:From a micro-instruction register 2, at the field including the next address information of the micro-instruction and an error correcting code, a correctable error is detected by an error detecting correcting circuit 3, end then, a second suppressing signal is generated from a suppressing signal generating circuit 4, the updating of the register 2, etc., is suppressed and an error correcting sequence is executed. Further, one clock cycle is delayed, a third suppressing signal is sent from a suppressing signal generating circuit 5, the updating of an arithmetic circuit 6 is suppressed, both suppressing signals are simultaneously released after the error correction is completed, the register 2 is updated and the action of the circuit 6 is restarted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprogram control device in an information processing device, and in particular, a function for detecting and correcting a correctable error and inhibiting operation of an arithmetic circuit when an error is detected. The present invention relates to an error correction control method for a control memory comprising:

[Conventional technology]

Conventionally, this type of control memory error correction control method detects correctable errors in all fields of a microinstruction, suppresses updating of the microinstruction register in the clock cycle in which the error is detected, and at the same time stops the operation of the arithmetic circuit. It is configured to suppress this.

[Problem that the invention seeks to solve]

In the case of the conventional control memory error correction pressure control method described above, a correctable error is detected in all fields of a microinstruction, and an operation inhibit signal is provided to inhibit the operation of the arithmetic circuit in the clock cycle in which the error is detected. is being sent.

However, in this case.

The operation inhibit signal for the arithmetic circuit has a large time delay (generally, the arithmetic circuit is a microlog).

(because of the physical distance from the RAM controller), this results in limited clock cycles for the microprogram controller.

[Means for solving problems]

The control memory error correction control method according to the present invention is as follows.

An address save register that sets the address corresponding to the microinstruction read from the control memory and set in the microinstruction register, and a branch that sets the branch address information sent from the arithmetic circuit controlled by the contents of the microinstruction register. Equipped with address save register.

When a correctable error is detected in a field containing next address information and an error correction code that are part of a microinstruction at the same time as the first inhibit signal caused by the arithmetic circuit is generated, the above-mentioned error is detected in the clock cycle in which the error is detected. Execute an error correction sequence at the same time as generating a second inhibit signal that inhibits updating of the microinstruction register, generate a third inhibit signal that inhibits the operation of the arithmetic circuit with a delay of one clock cycle, and after the error correction is completed. , after canceling the second inhibit signal, update the microinstruction register based on the contents of the address save register and branch address save register, and also cancel the third inhibit signal at the same timing as the release of the second inhibit signal. By doing so, the microinstruction after error correction is executed and the operation is restarted.

〔Example〕

Next, two embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The microprogram control device shown in FIG. 1 includes a control memory 1, a microinstruction register 2. Error detection and correction circuit 3. Inhibit signal generation circuit 4, 5° branch address save register 7, address save register 8. +1 counter9. Increment address register 10. +J turn address register 11, return address stack 12
．． Address selection circuit 13. Return address selection circuit 1
4° selection circuit 15. and a control circuit 16.

An error correction code based on a Hamming code is added to the microinstruction stored in the control memory 1, and the microinstruction is stored in the control memory 1 with this error correction code added.

The microinstruction read from the control memory l is then set in the microinstruction register 2.

This microinstruction contains next address information,
The contents of the microinstruction register 2 update the return address register 11 and the return address stack 12 and control the return address selection circuit 14, and the contents of the microinstruction register 2 determine the address of the next microinstruction to be executed. Control circuit 16
The address of the control memory 1 is determined by the address information from the address selection circuit 13 controlled by the address selection circuit 13 and branch address information to be described later, and microinstructions are read out from the control memory 1 one after another.

Microinstruction register 2 by error detection and correction circuit 3
When a correctable error is detected in the data set in the microinstruction register 2, the operation of the arithmetic circuit 6 is inhibited by an inhibition signal from the inhibition signal generation circuit 5, while the error detection and correction circuit 3 detects an error in the microinstruction register 2. After correcting the error, the inhibit signal is released. In this case, the operation inhibit signal sent to the arithmetic circuit 6 is limited to the field that controls the operation of the arithmetic circuit 6 to keep the nine-hour delay to a minimum. That is, when the error detection and correction circuit 3 detects a correctable error in the field that controls the operation of the arithmetic circuit 6,
A second deterrent signal is simultaneously sent from the deterrent signal generating circuit 4', and a third deterrent signal is simultaneously sent from the deterrent signal generating circuit 5.
Arithmetic circuit 6 in the clock cycle in which the error was detected. microinstruction register 21 branch address save register 7,
Address save register 8. After the increment address register 10, IJ turn address register 11°, and return address stack 12 are inhibited from being updated, and the error is corrected by the error detection and correction circuit 3, the error in the microinstruction register 2 is corrected as described above. conduct,
The second inhibition signal and the third inhibition signal are simultaneously released.

On the other hand, if the error detection and correction circuit 3 detects a correctable error in the field containing the next address information and error correction code of the microinstruction.

The second inhibition signal is sent from the inhibition signal generation circuit 4, and the microinstruction register 2. Address save register 8° Increment address register 10. Return address register 11. and updating of the return address stack 12 is suppressed, and l
After a clock cycle delay, the third inhibition signal is sent from the inhibition signal generation circuit 5, and the updating of the 9-branch address save register 7 and the arithmetic circuit 6 is inhibited.

By the way, as mentioned above, since the update of the arithmetic circuit 6 is inhibited by a signal delayed by one clock cycle, when the arithmetic circuit 6 updates a branch instruction, if the branch address information indicated by the processing result is lost. There is. Therefore, if the processing in the arithmetic circuit 6 is performed normally, but an error is detected in the microinstruction immediately after the branch instruction is executed in the computational circuit 6.

The selection circuit 15 selects the branch address save register 7. Then, based on the contents of the address save register 8 and the branch address save register 7, the microinstruction register 2 is updated, the third inhibition signal to the arithmetic circuit 6 is released, and the operation is restarted.

The above operation will be explained using the time chart of FIG. 2.

When a correctable error is detected in the field containing the next address information and error correction code of the microinstruction register 2, a second inhibition signal is sent from the inhibition signal generation circuit 4, and the operation of the error correction sequence is started. Since the next address information and the error correction code are not involved in controlling the operation of the arithmetic circuit 6, after the 7-lip flop of the arithmetic circuit 6 is updated, the third inhibition signal is output from the inhibition signal generation circuit 5 with a delay of one clock cycle. Sent out.

After the error in microinstruction register 2 is corrected, the second
The third inhibition signal is released and the microinstruction register 2 is updated, and after a delay of one clock cycle, the third inhibition signal is released and the operation is resumed.

Next, using the time chart in FIG.
The operation when a correctable error occurs simultaneously in the field containing the first inhibit signal caused by the microinstruction register 2, the next address information of the microinstruction register 2, and the error correction code will be described. in this case.

Since the micro-instruction with the error is not executed by the first inhibit signal, the third inhibit signal is quickly released by one clock cycle, and the micro-instruction after the error is corrected is executed.
Resume operation.

〔Effect of the invention〕

As explained above, in the present invention, when a correctable error is detected in a field that controls the arithmetic circuit of a microinstruction, an operation inhibit signal to the arithmetic circuit is sent in the clock cycle in which the error is detected, and When a correctable error is detected in the field containing the next address information and error correction code, an operation inhibit signal is sent to the arithmetic circuit at a timing one clock cycle later than the clock cycle in which the error was detected. , the time delay of the inhibit signal can be minimized, thus preventing the clock cycle of the microprogram controller from being limited.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation of FIG. 1. 1... Control memory, 2-... Micro instruction register. 3...Error detection and correction circuit, 4...Suppression signal generation circuit. 5... Inhibition signal generation circuit, 6... Arithmetic circuit, 7...
・Branch address save register, 8...Address save register, 9...+1 counter, 10...Increment address register, 11...Return address register, 12...Return address stack, 1
3... AS I'L/AS selection circuit, 14... Return address selection circuit, 15... Selection circuit, 16... Control circuit.

Claims (1)

[Claims] 1. A control memory that stores microinstructions, a microinstruction register in which data read from the control memory is set, an arithmetic circuit that operates according to the contents of the microinstruction register, and a control circuit that determines the address of the next microinstruction to be executed based on the contents of an instruction register; and a control circuit that adds and stores an error correction code to the microinstruction stored in the control memory, and the contents set in the microinstruction register. an error detection and correction circuit that performs error detection and correction based on the error detection and correction circuit and sets the corrected microinstruction in the microinstruction register; and when a correctable error is detected by the error detection and correction circuit, the operation of the arithmetic circuit is inhibited. an address save register that sets an address corresponding to a microinstruction set in the microinstruction register; and an address save register that sets an address corresponding to a microinstruction set in the microinstruction register; It has a branch address save register that sets branch information, and at the same time as the first inhibit signal generated by the arithmetic circuit is generated, a correctable error is detected in a field containing next address information and an error correction code that are part of the microinstruction. When detected, a second inhibit signal is generated to inhibit updating of the microinstruction register in the clock cycle in which the error is detected, and at the same time an error correction sequence is executed, and the operation of the arithmetic circuit is inhibited after a delay of one clock cycle. After the error correction is completed and the second inhibit signal is released, the microinstruction register is updated based on the contents of the address save register and the branch address save register, and the second inhibit signal is generated. A control memory error correction control system characterized in that a third inhibition signal is released at the same timing as the inhibition signal is released, thereby executing a microinstruction after error correction and restarting the operation.