JP2614934B2 - Micro program controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for error correction of a microprogram in information processing. The present invention relates to a microprogram control device in an information processing device controlled by a microprogram.

〔Overview〕

The present invention relates to a microprogram controller in an information processing device controlled by a microprogram, comprising: an error detection unit that detects an error by using an error code generated for a microinstruction and an address to be executed next to the microinstruction; In this way, the correctness of the execution order of the microinstructions is guaranteed, and the address error can be corrected before reading the next microinstruction to be executed.

[Conventional technology]

In general, error correction in a microprogram control device of this type of information processing apparatus includes information processing Vol.23 No.4
As shown in "Application of Error Detection and Correction Codes" (Eiji Fujiwara and Shigeo Kaneda, Information Processing Society of Japan), an ECC method of two-bit error detection and one-bit error correction is employed.

Conventionally, a microprogram controller employing the ECC system is provided with a control memory for adding an error correction code to a microinstruction word and storing it, as shown in Japanese Patent Publication No. 62-027417, for example, and further reading the control memory. Output,
There is a technique in which error correction means is provided for the output of the micro address register holding the read address of the content, and error detection and correction are performed on both the micro address register and the read output of the control memory.

According to this technique, an error is detected even when an address of the control memory different from the output of the micro address register is read, so that the contents read from the control memory can be guaranteed and controlled by the microprogram. The reliability of the information processing device is greatly improved.

[Problems to be solved by the invention]

In the above-described conventional microprogram controller, the error is detected based on the content read from the control memory and the output of the microaddress register holding the read address, so that the addition for updating the microaddress register is performed. If the read address of the control memory is erroneous due to a failure of the switch or the switch for selecting the next read address, the micro instruction is read from the control memory according to the erroneous read address, and the error is not detected. .

Further, when an error in the read address occurs at an early point in one machine cycle, and when the control memory is read in accordance with the error address, the output from the control memory matches the error address, so that no error can be detected as a result. There are drawbacks.

The present invention solves such a problem, and provides an apparatus that can guarantee the correctness of the execution order of microinstructions and correct an address error before reading a microinstruction to be executed. Aim.

[Means for solving the problem]

The present invention provides a control memory for storing a microinstruction not including a conditional branch instruction to which an ECC error correction code generated for the address of a microinstruction to be executed next is added, and a readout from the control memory. A micro address register for holding the address of the micro instruction,
A micro-instruction register for temporarily holding a micro-instruction read from the control memory, a decoder for decoding the micro-instruction held in the micro-instruction register and sending it to a computing unit, and performing error correction on the output of the micro-address register. A micro-program control device comprising an error correction circuit for performing an output of the micro-instruction register and the micro-address register instead of the error correction circuit, and correcting an error when an error is detected. An error detection / correction circuit for sending to the decoder is provided.

The error detection and correction circuit includes a unit that suppresses execution of a microinstruction when an error is detected, and the microaddress register and the microinstruction register detect an error in the content held according to an output of the error detection and correction circuit. It is desirable to include means for correcting.

[Action]

Enter the contents of the micro-instruction with the error correction code generated for the address of the micro-instruction to be executed next and the read address, and detect whether or not there is an error. The execution of the microinstruction is suppressed to correct the error. When the error correction is completed, the inhibition of the microprogram control is released and the control by the microinstruction is executed.

This makes it possible to guarantee the validity of the execution order of the microinstructions, correct the error of the address of the microinstruction before reading the next microinstruction to be executed from the control memory, and furthermore, It is also possible to detect and correct an incorrect address generation failure due to a failure mode of a circuit that generates an address read from the memory and continue the operation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. First
FIG. 2 is a block diagram showing the configuration of the embodiment of the present invention.

In the embodiment of the present invention, a control memory 1 for storing a microinstruction to which an error correction code generated for the address of a microinstruction to be executed next is added, and an address of the microinstruction read from the control memory 1 are stored. Micro address register 2 for holding, and micro instruction register 3 for temporarily holding a micro instruction read from control memory 1
And a decoder 9 for decoding the microinstruction held in the microinstruction register 3 and sending it to the arithmetic unit 10;
Further, as a feature of the present invention, the microinstruction register 3
And the output of micro address register 2 as input,
An error detection and correction circuit 4 that corrects the error when detected and sends it out of the decoder 9 includes means for suppressing the execution of the microinstruction when the error is detected. , Micro address register 2 and micro instruction register 3 have an error detection and correction circuit 4
Means for correcting an error in the content held in accordance with the output of.

The error detection / correction circuit 4 is connected to switches 6 and 8 via signal lines 40 and 41. The switch 6 is connected to the adder 5 and the micro address register 2, and the micro address register 2 is connected via the switch 7. It is connected to the error detection and correction circuit 4.

The error detection and correction circuit 4 is connected to the decoder 9 via a signal line 42, the microinstruction register 3 is connected to the switch 7 via a signal line 30, and the decoder 9 is connected to the switch 7 via a control signal 31. Connected to.

The control memory 1 stores a microinstruction and an error correction code generated for an address to be executed next to the microinstruction added to the microinstruction. The micro address register 2 is a read address of the control memory 1 + 1
Hold. When the microinstruction held in the microinstruction register 3 is a branch instruction, the switch 7 is connected to the signal line 30.
Is selected, and in the case of another instruction, the micro address register 2 is selected.

The adder 5 updates the address read from the control memory 1 and obtains the next address to be read. The adder 5 adds, for example, 1 to the output of the switch 7. The switch 6 normally selects the adder 5, and only when there is an error in the read address of the control memory 1 and the output of the control memory 1,
Select 40. The switch 8 normally selects the output of the control memory 1 and selects the signal line 41 only when the above error occurs.

The output of the switch 8 is sent to the micro instruction register 3. Further, the output of the microinstruction register 3 is decoded by the decoder 9, thereby generating a control signal 31 for controlling the switch 7 and a control signal for controlling the operation unit 10.

The error detection and correction circuit 4 operates using the above-described switch 7 and the micro instruction register 3 as inputs. When an error is detected by the error detection and correction circuit 4, the result of the error correction is input to the switch 6 and the switch 8 via the signal lines 40 and 41. At the same time, the error detection and correction circuit 4 outputs an operation inhibition signal via the signal line 42 to inhibit the operation of the decoder 9.

When the storage of the result of the error correction in the micro address register 2 and the micro instruction register 3 is completed, the inhibition of the micro program control due to the error is released, and the control by the micro instruction is performed.

Next, an error correction operation when an error in the execution order occurs in the microprogram control device of the embodiment of the present invention will be described. FIG. 2 is a timing chart showing an operation example of the microprogram control device according to the present invention. For simplicity of explanation, it is assumed that the micro address register 2 shown in FIG. 1 has an 8-bit configuration, the branch is not performed by the micro instruction, and the address is incremented by one. The following shows the execution procedure. The symbol H is 16
() Indicates a microinstruction word read from the control memory 1 by the address in ().

1. "00H" is stored in the micro address register 2 in advance.
Is set, and no error occurs in the error detection and correction circuit 4.

2. With respect to the address “00H” output from the micro address register 2, the microinstruction “(00H)” stored in “address 00H” of the control memory 1 is read out via the switch 7, and is read out via the switch 8. Is output to the microinstruction register 3. At the same time, the address output from the switch 7 is 1
Is updated to “01H” by the adder 5 that adds
To the micro address register 2 via

3. In the next machine cycle, the output “(00H)” of the switch 8 is stored in the micro instruction register 3 and the address “01” output from the switch 6 is stored in the micro address register 2.
H "is stored in the micro instruction register 3.
Is determined not to be a branch instruction by the decoding of the decoder 9, the switch 7 outputs the address "01H" of the micro address register 2 and the "01H" of the control memory 1 is output.
The microinstruction "(01H)" stored at the address is read and output to the microinstruction register 3 via the switch 8. At the same time, the output "01H" of the switch 7 is set to "02H" by the adder 5. And output to the micro address register 2 via the switch 6.

The error detection and correction circuit 4 receives the output “01H” of the switch 7 and the output “(00H)” of the microinstruction register 3 as inputs, confirms that there is no error, and checks the microinstruction “(00
H) ”is output to the arithmetic unit 10 and executed.

4. In the next machine cycle, “(01H)” is stored in the micro instruction register 3 and “02H” is stored in the micro address register 2 in the same manner as in step 3, and the micro instruction “(02H)” in the control memory 1 is switched. Output to the microinstruction register 3 via the unit 8. At this time, the adder 5 and the switch 6
It is assumed that "07H" is output to the micro address register 2 as a result of the occurrence of a 1-bit error with respect to the correct answer value "03H".

The error detection / correction circuit 4 receives the output “02H” of the switch 7 and the output “(01H)” of the microinstruction register 3 as input, confirms that there is no error, and executes the microinstruction “(00H)” to the arithmetic unit 10. I do.

5. In the next machine cycle, “(02H)” is stored in micro instruction register 3 and “07H” is stored in micro address register 2 in the same manner as in step 3, and micro instruction “(07H)” in control memory 1 is switched. Output to the microinstruction register 3 via the unit 8. Further, “08H” is output from the switch 6.

Here, the error detection and correction circuit 4 outputs the output “07H” of the switch 7.
Further, an error is detected using the output “(02H)” of the microinstruction register 3 as an input, and the address “07H” is corrected to “03H”. At the same time, the error detection and correction circuit 4 outputs an operation inhibition signal via the signal line 42 to inhibit the operation of the decoder 9. Further, the result of the error correction is output to the switch 6 via the signal lines 40 and 41 as "03H" and to the switch 8 as "(02H)". The microinstruction “(02H)” is not executed because the decoder 9 is suppressed.

6. In the next machine cycle, "(02H)" of the switch 8 is stored in the microinstruction register 3, and the address "03H" output from the switch 6 is stored in the micro address register 2. At the same time, the switch 8 inputs the micro instruction “(03H)” read from the control memory 1 to the micro instruction register 3
, And the switch 6 outputs the address “04H” updated by the adder 5.

The error detection and correction circuit 4 outputs the output “03H” of the micro address register 2 and the output “(02
H) ”, the decoder 9 releases the inhibition of the decoder 9 and outputs the microinstruction“ (02H) ”to the arithmetic unit 10 for execution.

〔The invention's effect〕

As described above, according to the present invention, by performing error detection and correction using a generated error code for a microinstruction and an address to be executed next to the microinstruction, the execution order of the microinstruction can be improved. The validity can be guaranteed, and the effect of correcting an address error before reading the next microinstruction to be executed from the control memory can be obtained. Furthermore, the AC characteristics in the circuit that generates the address to be read from the control memory can be obtained. There is an effect that the operation can be continued by detecting and correcting an incorrect address generation failure due to a failure mode such as a failure.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing chart showing an operation example when the micro address register in the embodiment of the present invention has an 8-bit configuration. 1 ... control memory, 2 ... micro address register,
3 ... micro instruction register, 4 ... error detection and correction circuit, 5 ... adder, 6, 7, 8 ... switch, 9 ... decoder, 10 ... calculator, 30, 40, 41, 42 ... ... signal lines, 31 ...
…Control signal.

Claims (3)

(57) [Claims] 1. A control memory for storing a microinstruction not including a conditional branch instruction to which an ECC error correction code generated for an address of a microinstruction to be executed next is added, and A micro-address register for holding the address of the read micro-instruction, a micro-instruction register for temporarily holding the micro-instruction read from the control memory, and a decoder for decoding the micro-instruction held in the micro-instruction register and sending it to the computing unit And an error correction circuit that performs error correction on an output of the micro address register.In the micro program control device, the output of the micro instruction register and the output of the micro address register are input instead of the error correction circuit. , Correct errors when they are detected A micro-program control device comprising an error detection and correction circuit for transmitting the error detection and correction signal to the decoder. 2. The microprogram control device according to claim 1, wherein said error detection and correction circuit includes means for suppressing execution of a microinstruction when an error is detected. 3. The microprogram control device according to claim 1, wherein said microaddress register and said microinstruction register include means for correcting an error in the held content in accordance with an output of said error detection and correction circuit.