JPS6114536B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram type computer control system.

In a microprogram type computer, an arithmetic algorithm is stored in advance in a microprogram memory, and the arithmetic processing is completed by sequentially reading out the algorithm. To improve calculation speed, a pipeline method is used in which the next instruction to be executed is read while a certain instruction is being executed. FIG. 1 shows the basic configuration of a pipelined microprogram computer, and FIG. 2 shows the timing of its operation. The outline of its operation is as follows.

When the microinstruction i read from the microprogram memory 2 in the previous cycle is set in the pipeline register 1, the address controller 3 operates according to the next address selection information, and the microinstruction i+1 to be executed next is read out. It can be done.
At the same time, the microinstruction i is sent to the arithmetic unit 4 and the instruction is executed. When execution of microinstruction i and reading of microinstruction i+1 are completed, microinstruction i+1 is set in pipeline register 1, and the next cycle begins.

In this method, the reading of the microprogram and the instruction are performed simultaneously, so the operating speed is increased, but when a branch is taken, the following problem occurs. That is, when branching due to a condition, the truth of the condition cannot be determined and the address of the next microinstruction to be executed cannot be determined unless the processing of the microprogram instruction currently being executed is completed.

For example, if there is a condition that if the operation result of microinstruction i+1 is zero, microinstruction n is executed in the next step, then microinstruction i
The next instruction to be executed until the execution of +1 is completed is
It is not clear whether it is microinstruction n or microinstruction i+2, so it is necessary to rest for one cycle. Therefore, when a large proportion of programs are branched depending on the result of executing a certain microinstruction, time loss becomes large. Several methods have been considered to reduce this time loss.

First, before the branch condition is determined, the result is predicted and the next microinstruction to be executed is read. In the previous example, before microinstruction i+1 is executed, microinstruction i+2 or microinstruction n
Predict and read out one of the following. However, in general, instructions that branch when the operation result is zero (BZ...
branch on Zero) and an instruction that branches when it is not zero (BNZ...branch on Not Zero), so it is difficult to know whether the next consecutive address (microinstruction i + 2) is the destination address (microinstruction n). do not have.

In addition, the microprogram memory is divided into multiple banks so that microinstructions for multiple branch destinations that may be executed next can be read simultaneously. There is a method of reading out micro-instructions, and when a branch instruction ends, selecting an instruction that meets the conditions to be executed next. However, this method has the drawback of increasing memory capacity and hardware cost.

The present invention has been made in order to eliminate such conventional drawbacks, and it provides a control bit for specifying a branch address so that the branch destination can be specified by software according to the program. The purpose of this invention is to provide a microprogram control method that improves the drawbacks of the branch address prediction method.

The present invention will be described in detail below with reference to the drawings.
FIG. 3 is a diagram showing an example program for explaining the basic concept of the control method of the present invention. As shown in this figure, R is set to 100 at the START address, and Decrease the value of R by 1 and obtain (A+
1) Consider the case of branching to a continuous address (address A+2) or a jump address (LOOP address) depending on whether or not R is zero at the address. Since the probability that R becomes zero at this time is 1/100, it is clear that there is a high possibility of branching to the LOOP number. Therefore, in terms of hardware, it is normally configured to branch to the LOOP address, and only when the value of R becomes zero,
If we decide to read a new microinstruction at address (A+2) without executing the instruction that has already been read, the loss will be 1 in 100. However, even if it branches depending on whether the value of R is zero or not,
BNZ (Branch on Not Zero: Branch if it is not zero) and BZ (Branch on Zero: Branch when it is zero)
There are 2 instructions, and whether to branch to a consecutive address or a jump address depends on the program. Therefore, if the branch address to be prefetched is unilaterally determined by hardware, a burden will be placed on the program when trying to create an optimal microprogram.

In a computer where the microprogram can be rewritten by the user, it is more flexible to have software control according to the program rather than prefetch control of branch addresses using hardware. Therefore, in the present invention, a prediction bit BAS that specifies a branch address is added to the microinstruction (branch instruction) in addition to the instruction code, so that the microprogram can perform prefetch control of the branch instruction. When the BAS value is 1, the microinstruction at the jump address is read ahead, and
When the BAS value is 0, microinstructions at consecutive addresses are prefetched.

FIG. 4 shows an embodiment of the specific configuration of the microprogram control system of the present invention, which includes a microprogram memory 10, a pipeline register 11, an instruction decoder 12,
address register 13, incrementer 14,
Subroutine register 15, multiplexer 1
6, comparator 17, and branch processing circuit 18
It consists of Here, the microprogram memory 10 is a memory for storing microinstructions, the pipeline register 11 is a register for holding instructions read from the microprogram memory 10, and the instruction decoder 12 is a memory for storing microinstruction codes. deciphering (decoding)
When using a branch instruction, which is a feature of the present invention, the predicted address is first detected using a bit (BAS) that predicts the branch destination included in the microinstruction. is selected, and then receives an execution result flag from an arithmetic circuit (not shown) and operates the multiplexer 16 again according to this and the instruction code (branch condition) to output the correct execution address. Furthermore, a signal indicating whether the predicted address matches the correct execution address is received from the branch processing circuit 18 (described later), and if the prediction is wrong, the contents of the pipeline register 11 are cleared and the instruction is executed. The address register 13 is a circuit that stops the execution of the memory and instructs to read the instruction at the correct address.The address register 13 is a register that holds the address when reading the memory and outputs the current address as its output.The incrementer 14 is a circuit that adds 1 to the current address and outputs a continue address as its output, a subroutine
Register 15 holds the return address when subroutine jump is performed.
The multiplexer 16, which outputs the subroutine return address as its output, uses a signal generated by decoding the microinstruction by the instruction decoder 12 to output the continue address, subroutine return address, and jump address. Comparator 17 is a circuit that compares the jump address and the current address by selecting one of the addresses (included in the instruction) to determine the next address. The branch processing circuit 18, which outputs a MATCH signal that is 1 if the address and the current address are equal, and 0 otherwise, is composed of logic gates.
This circuit determines whether the address predicted at the time of a branch instruction is the address to be actually executed, and sends the result to the instruction decoder 12.

Next, hardware related to branch instruction processing, which is a feature of the present invention, will be explained. with a branch instruction
If the value of BAS is 1, that is, the jump address is predicted, the comparator output MATCH indicates that the prediction was correct if the value of MATCH is 1, and the prediction was wrong if the value of MATCH is 0. That means that. Conversely, if the value of BAS is 0, that is, the continued address is predicted, the prediction will be incorrect if the value of MATCH is 1, and the prediction will be correct if the value of MATCH is 0. .

Therefore, the branch processing circuit 18 may perform an exclusive OR of the predicted bits BAS and MATCH, and send the output to the instruction decoder 12. In other words, the output indicates that the microinstruction that was predicted and read when it was "1" was incorrect.
When it is “0”, it indicates that the instruction was correct, so when the instruction decoder receives the signal “1”, it can control the execution of the incorrectly read microinstruction and read the correct microinstruction. It can be carried out.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a pipeline type microprogram computer, FIG. 2 shows the timing of its operation, and FIG. 3 shows an example of a microprogram including a branch instruction. Fourth
The figure is a specific circuit configuration diagram showing one embodiment of the present invention. 10...Microprogram memory, 11...
... Pipeline register, 12 ... Instruction decoder, 13 ... Address register, 14 ... Intermenter, 15 ... Subroutine register, 16 ... Multiplexer, 17
... Comparator, 18 ... Branch processing circuit.

Claims (1)

[Claims] 1. Store a branch instruction consisting of bits and instruction codes that predict a branch destination address or continuous address as the address of the microinstruction to be executed next,
A microprogram memory that reads a microinstruction corresponding to a given address, a pipeline register that temporarily holds the microinstruction read from this microprogram memory, and an operation that executes the microinstruction held in this pipeline register. a circuit, an address register that temporarily holds an address given to the microprogram memory, an incrementer that outputs continuous addresses obtained by incrementing the address held in this address register, and continuous addresses output from this incrementer. and a multiplexer that selectively outputs one of the branch destination addresses of the branch instructions read from the microprogram memory to the microprogram memory, and a multiplexer that instructs the multiplexer to select a continuous address or a branch destination address to the microprogram memory. In a microprogram control system, the instruction decoder is provided with an instruction decoder that executes the instruction according to the prediction bit of the branch instruction read from the instruction code and the instruction code and the execution result of the branch instruction by the arithmetic circuit. Compare the address selected again by the decoder and held in the address register with the branch destination address and MATCH
The instruction decoder includes a comparator that outputs a signal, and a logic gate that obtains the logic output of the MATCH signal output from the comparator and the prediction bit, and according to the logic output of the logic gate, the instruction decoder performs prediction for the pipeline register. A microprogram control method characterized by clearing selected microinstructions according to bits.