JPS62269235A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the increase of hardware by constituting the titled processor so that the generation of an address of the succeeding instruction can be executed without being awaited until a general register is updated by the preceding instruction which is not executed yet, and also, an updated data of the general register is generated by using an address generating device. CONSTITUTION:An instruction decoder DEC14 sets GR3, GR2, and '0' to an index register XR18, a base register BR19, and displacement register DR20, respectively, by sending a control signal to selectors 15-17. An address generating device AA21 adds values of the index register XR18, the base register BR19, and the displacement register DR21, respectively, and its value is written in GR2 of a preceding control general register file PGR13. Until such write is executed, GR2 of the preceding control general register file PGR13 is used by the succeeding instruction, instead of GR2 of a general register file GR12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device that reduces pipeline disturbances caused by general-purpose register contention during address generation.

[Conventional technology and its problems]

Conventionally, this type of information processing device using the /J e-line method detects that a general-purpose register used for address generation is updated by an unexecuted preceding instruction, and the general-purpose register is updated upon completion of the preceding instruction. It was necessary to delay address generation until

Further, as a technique for improving the delay in address generation described above, a data generation device is provided to precede the instruction execution, but this also requires a data generation device, which poses the problem of an increase in the amount of hardware.

[Failure to solve the problem]

According to the present invention, in an information processing device including a preceding control device, a storage device, and an arithmetic execution device, there is provided a means for detecting that an instruction does not require reading an operand from a storage device, and an instruction for updating a general-purpose register. and a means for detecting that.

When the conditions of each detection means are satisfied, an operation is executed using an address generation device that generates an address to be sent to the storage device. An information processing device characterized by including means for creating update data is obtained.
Ru.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a preceding control device 1. Storage device 2. It is equipped with an arithmetic execution device 3. In the preceding control device 1, 11 is an instruction register (I
R), 12 is a general-purpose register file (GR), 13 is a advance control general-purpose register file (PC; R), 14 is an instruction recorder (DEC), 18 is an index register (XR), 19 is a base register (BR), 20 is a displacement register (DR), and 21 is an address generator (AA).

15, 16, and 17 are respectively the above-mentioned XRI 8 and BR
19, is an input selector of DR20.

The advance control device 1 reads the command from the storage device 2.

The data is decoded, and if necessary, the operand address is determined by address calculation, the data is read from the storage device 2, and the operation code, operand, operation information, etc. are transferred to the operation execution device 3. The calculation execution device 3 performs calculations based on the information set by the preceding control device 1.

Performs alteration of various registers, status, or storage devices.

In the advance control device 1, a general register file (G
For a 1RX type instruction that reads its contents from R) 12, R2+R of general register file (GR) 12
Read out the index and base from 18.3 and store each in index register (XR). Set in pace register (BR) 19. At the same time, n displacement addresses specified by the instruction are set in the displanement register (DR) 20. This index register (XR)18. Base Rensta (BR)
)19. The address of the second operand is determined by adding the outputs of the displacement register (DR) 20 by the address generator (AA) 21. This address is sent to the storage device 2, the second operand is read out, and the second operand is sent to the arithmetic execution device 3. The first operand is read from R1 of the general register file (GR) 12.
The data is sent to the calculation execution device 3.

In the RR type instruction, the first . Second, the land can be obtained by reading out the general register file (GR) 12, so there is no need to read it out from the storage device 2.

At this time, the address generation device (AA) 21 is not used. The instruction decoder (DEC) 14 detects that the address generator (AA) 21 is not used because the instruction being decoded does not need to read operands from the storage device 2. Also, instruction decoder (DEC)
14 also detects that the instruction being decoded is an instruction that updates a general-purpose register. Instruction register (IR) 1
When the instruction No. 1 detects that the address generator (AA) 21 is not used and that it is an instruction to update a general-purpose register, the index register (XR) 18,
Pace register (BR)19. Input selector (SEL) of displacement register (DR) 20 15
, 16 and 17 are switched according to instructions from the instruction decoder (DEC) 14, and values different from those for RX type instructions are index register (XR) 18, pace register (BR) 19, and displacement register (DR). Set to 20.

Tosanru. The values set in these registers are sent to the address generator (AA) 21, and its output is written to the advance control general register file (PGR) 13K.

For example, set GR2+GR3 to the instruction register (IR) 11.
If there is an instruction to set R2, the instruction decoder (DEC) 14 outputs this instruction to the address generator (AA).
) 21 is not used and that it is an instruction to update a general-purpose register. Instruction decoder (DEC)
14 sends a control signal to selectors 15, 16 and 17 to set GR to index register (XR) 18.
3, GR2 is set in the base register (BR) 19, and 0 is set in the displacement register (DR) 20. The address generation device (AA) 21 includes an index register (XR) 18. The values of the pace register (BR) 19° and the displacement register (DR) 20 are added, and the resulting value is added to the advance control general-purpose register file (PGR).
) is written to GR2 of 13.

After this instruction is executed by the arithmetic execution unit 3, GR2-1-GR3 of the general-purpose register file (GR) 12 are stored in GR2.
is written, but until this writing is performed, GR2 of the advance control general register file (PGR) 13 is used in the subsequent instruction instead of GR2 of the general register file (GR) 12.

Also, if GR2 is referenced for address generation in the immediately following instruction, the address generation device (AA) 21
General purpose register file (PGR) 1
3 and selector (SEL) 15, 1
6 can also be set in the index register (XR) 18 and pace register (BR) 19.

In this embodiment, a advance control general-purpose register file (PGR) 13 is provided separately from the general-purpose register file (GR) 12, but this is because writing from the address generation device (AA) 21 competes with writing from the arithmetic execution device 3. If the general purpose register file (GR) 12 can write to two registers at the same time.

The advanced control general-purpose register file (PGR) 13 is not particularly necessary.

〔Effect of the invention〕

As explained above, two aspects of the present invention include means for detecting that the instruction does not require reading O-Land from a storage device, means for detecting that the instruction is an instruction for updating a general-purpose register, and each detection means. By using an address generation device that generates an address to be sent to the storage device when both of the conditions of Since update data for general-purpose registers is generated using

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Preliminary control device, 2... Storage device, 3... Arithmetic execution device, 11... Instruction register, 12... General-purpose renosta file, 13... Preliminary control general-purpose renosta file, 14...Instruction recorder+15+16+17・
...input selector, 18...index register,
19... Pace register, 20... Displacement register, 21... Address generation device Fig. 1

Claims (1)

[Claims] 1. In an information processing device equipped with a preceding control device, a storage device, and an arithmetic execution device, means for detecting that the instruction does not require reading an operand from the storage device, and the instruction is an instruction for updating a general-purpose register. and an address generating device that generates an address to be sent to the storage device when the conditions of each of the detection means are satisfied. An information processing device comprising: means for creating update data for a general-purpose register for address generation.