JPS6041146A - Data transfer control system - Google Patents

Abstract

PURPOSE:To reduce overhead by suppressing the writing operation of a block in a buffer storage device when data to be transferred start from the final word of the block. CONSTITUTION:When a transfer start signal for one block is energized, a decoder DEC22 is activated and an address in the buffer storage device is set up in an address register BSAR21. If the address indicates the final word of the block, an output line 11 of the decoder 22 is energized. Since an MFF23 is turned on by a move instruction, an AND is found out by an NAND circuit 24, a transfer cycle specification control signal MCYCLE inputted to an AND circuit 25 is blocked and the output signal MOVEIN is suppressed. Since the final word of the block is necessary data, the final word is transferred to a CPU through a bypass route and an OR circuit.

Description

Detailed Description of the Invention (al) Technical Field of the Invention In a data processing device having a buffer storage device, when the required data does not exist on the buffer storage device, the data is transferred from the main storage device to the buffer storage device. Regarding the method.

Background of the Technology In a data processing device having a buffer storage device, when a move instruction is executed, if there is no source operand data on the buffer storage device, the source operand data is transferred from the main storage device to the buffer storage device. However, the source operand data is generally data that does not take into account one block boundary of the buffer storage device.

Therefore, for example, if the above source operand data starts from the last word of a block, transferring the block one word at a time from the beginning would create a factor that increases the overhead during data transfer. , it was desired to consider an efficient transfer method.

Also, when a large amount of data is required by a central processing unit, etc., and the data is not available on the buffer storage device, and the block needs to be transferred from the main storage device to the buffer storage device, the data is transferred to the high-speed G. The block is typically transferred to a buffer storage device for transfer to a central processing unit;
At the same time as writing, data was transferred directly to the central processing unit via a bypass route. The present invention aims to make effective use of this bypass route.

(cl. Prior Art and Problems When operating a data processing device having a buffer storage device and accessing the buffer storage device, when the required data does not exist in the buffer storage device, in the conventional method, the data is moved from the block boundary. However, no matter where the data starts, it is transferred to the buffer storage device in units of blocks.

Therefore, all data in the block other than the required data is also transferred to the buffer storage device, which poses a problem of increased overhead in the data processing device.

Also, for example, even if the source operand data starts from the last word of a certain block, all the remaining words (specifically, 3 words x 8 bytes - 24 bytes) are transferred, so originally the central processing Data needed by the device is also replaced, which poses a problem of lowering the hint rate for the buffer storage device from the perspective of the central processing unit.

(d) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides a method for executing an instruction that requires a large amount of data, such as a move instruction, and transferring the data from the main memory to the buffer storage when the data is not present in the buffer storage. In order to reduce as much as possible the overhead that occurs when transferring data to a block, if the source operand data does not correspond to the first word of a block, the write operation to the buffer storage of that block is stopped, and the unnecessary write operation to the buffer storage is The purpose is to provide a method to reduce transfer cycles.

According to the present invention, in a data processing device having a buffer storage device, when one block does not exist in the buffer storage device, the block is transferred from the main storage device to the buffer storage device. When transferring, means are provided for detecting that the source operand to be transferred does not start from the first word of the block, and when a detection output is asserted by the detecting means, the above 1. This is achieved by providing a control method that inhibits transfer cycles from a device to a buffer storage device and prevents writing to the buffer storage device, thereby reducing wasteful transfer cycles to the buffer storage device and eliminating unnecessary It has the advantage of avoiding braces.

ffl Embodiment of the Invention When reading a large amount of continuous data, such as with a move instruction, the address is read in order from the youngest address, but when the source operand data is not on the buffer storage device,
It is necessary to transfer the data from the main memory to the buffer 1, a device.

The present invention was made by focusing on the fact that, for example, when the source operan 1 data starts from the last word of a certain block, other words in that block are never used in the above instruction. , when transferring the block from the main memory to the buffer memory, the write operation to the buffer memory is stopped and the data is transferred to the central processing unit to reduce the number of transfer cycles to the buffer memory, and the next This allows for immediate operation.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram explaining the present invention in detail, and FIG. 2 is a block diagram showing a transfer control circuit necessary for implementing the present invention.

In FIG. 1, 1 is a main memory (MS), 2 is a buffer storage (hereinafter referred to as BS), 21 is a buffer storage address register (BSAR), 3.4 is an OR circuit, and 5 is a bypass route. .

First, an instruction to transfer a large amount of source operand data such as a move instruction is executed in a central processing unit (hereinafter referred to as CPU) not shown, and an operand address is set in the address register (BSAR) 21 of BS 2. is accessed, but when the data does not exist on the BS2, the source operand data is transferred from the main memory (MS) 1 to the BS2.

The two source operant lists are made up of consecutive data in order from the lowest address, and are transferred from the main memory to the BS 2 in that order. At this time, the unit to be transferred at one time is 1 block (for example, 8
Each word (4 words - 32 bytes) is transferred to CBS 2J2 four times, one word at a time.

Then, in order to increase the transfer speed to the CPU, the transfer data is written to 1332, and at the same time, the bypass route 5
The data is controlled to be transferred directly to the CPU via the OR circuit 4.

In the present invention, when looking at a certain address block of the transfer data, for example, when the data to be transferred starts from the last word of the block, the other three words are irrelevant to the data transfer. Since the block is data, it is transferred from the above ↑, a unit W (MS) 1 to Bs2, but writing to BS 2 is suppressed, and only the last word is passed through the above bypass route 5.
It controls the transfer to Pu.

Figure 2 shows the control circuit. 2I is the same address register (BSAI?) as in Figure 1, and 22 is a decoder (BSAI?) that decodes the 2-bit internal address of one block.
DEC), 23 is a move flip-flop (MFF) indicating that an instruction to transfer a large amount of continuous data such as a move instruction is being executed, 24 is a NAND circuit, 2
5 is an AND circuit, and one of its inputs is the main memory (M
There is a control signal (M(:YCLE)) instructing a transfer cycle from S) 1 to BS 2, and when the output signal MOνEIN of the AND circuit 25 is present, a normal transfer operation is performed.

Now, the transfer start signal for a certain block is activated, the decoder (DEC) 22 is activated, and the buffer storage device address set in the address register (BSAR) 21 is set to the last word of the block, for example. , the decoder (DEC') 22
The output line indicated by 11 is energized.

At this time, the move flip flop (MFF) 23 is on, so the NAND circuit 24 performs an AND operation, and operates to block the control signal MCYCLE input to the AND circuit 25. Output signal M
OνEIN is inhibited.

However, since the last word of the above block is necessary data, bypass route 5. By controlling the data to be transferred to the CPU through the OR circuit 4, it is possible to perform efficient transfer control to the buffer storage device that meets the purpose of the present invention.

+g+ Effects of the Invention As explained in detail above, according to the present invention, when an instruction that involves a large amount of data transfer, such as a move instruction, is executed in a data processing device having a buffer storage device, the data is If the data does not exist in the storage device, the data will be transferred from the above (2) device to the buffer description 1.α device in blocks, but if the data corresponds to, for example, the last word of the above block, the block is buffer record 1
．． Since it is controlled not to write to device a,
The transfer speed recorded in the buffer storage device can be reduced,
Efficient data transfer control can be executed.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the present invention in detail, and FIG. 2 is a block diagram showing a transfer control circuit necessary to implement the present invention. In the drawing, 1 is the main memory (MS), 2 is ＼
Sofa storage device (BS), 21 is an address register (BSAR), 22 is a decoder (DEC),
23 is move flip flop (MFF), 5
Hano\Inogusuru rate. MCYCLE and MOVEIN represent control signals, respectively.

Claims (1)

[Claims] In a data processing device having a buffer storage device, when one source operand data does not exist in the buffer storage device and a block at that address is transferred from the main storage device to the buffer storage device, the source operand data does not exist in the buffer storage device. means is provided to detect that the word does not start with the word , and when the detection means obtains a detection result, the transfer cycle from the main memory to the buffer storage device is inhibited, and no writing to the buffer storage device is performed. A data transfer control method characterized by controlling as follows.