JPH0612622B2 - Dynamic memory refresh method - Google Patents

Description

The present invention relates to a dynamic memory refresh system, and more particularly to a microprocessor having a dynamic RAM refresh function (hereinafter, CPU with refresh function).
(Hereinafter referred to as ")" for refreshing a dynamic RAM in a system for continuous direct memory access (hereinafter referred to as "continuous DAM").

[Conventional technology]

When performing conventional refresh, a dedicated refresh controller 23 is used as shown in FIG. 2, or when a CPU with refresh function is used, an interface circuit as shown in FIG. 3 is used. In the case of the example of FIG. 2, an address signal 1 and a read / write control signal (hereinafter, control signal) from a microprocessor (hereinafter, CPU) or direct memory access controller (hereinafter, DMAC) 9), the refresh controller 23 selects the memory select signal 5-corresponding to the designated address.
One of the 1,5-2,5-3,5-4 is made active and the dynamic RAM 6-1, 6-2, 6-3, 6
-4 is selected. At this time, the lower order of the address signal 1 is output to the address line 8 and is set as address information in the dynamic RAM by the select signal 5. Next, the refresh controller 23 outputs the upper part of the address signal 1 to the address line 8 by a predetermined dimming and makes the strobe signal 18 active to perform the actual access (dynamic R).
(Read or write for AM is also specified, but omitted here). At the time of writing, the data on the data bus 22 is input to the dynamic RAM from the data bus I / F 21 through the write data signal, and at the time of reading, the data read from the read data signal 20 is transferred to the data bus I by the data ready signal 24. / F21
Output to the data bus 22. At the time of refresh, the refresh controller 23 outputs an address to be refreshed to the address line 8 and activates all the select signals 5-1, 5-2, 5-3, 5-4 (at this time, the strobe signal 18 is active). The dynamic RAM is not accessed because it must not be). CPU during refresh
Alternatively, since the data ready signal 24 is not output even if there is an access from the DMAC, the access is not performed until the refresh is completed.

In the case of the example in FIG. 3, the upper 2 bits of the address signal 1 enter the decoder 2 and the decode signals 3-1, 3-2
Any one of 3-3, 3-4 becomes active, and select signals 5-1, 5-2, 5-3, 5 through OR gates 4-1, 4-2, 4-3, 4-4. -4 becomes active and the dynamic RAMs 6-1, 6-2, 6
Any one of -3 and 6-4 is selected. Address signal 1 is sent to address line 8 via multiplexer 7.
The lower and upper bits of the signal excluding the upper 2 bits are output (this switching is performed by the address switching signal 11 from the timing circuit 10). When the strobe timing signal 12 becomes active, the strobe signal 1
8 becomes active, and the dynamic RAMs 6-1 and 6
The one selected by the select signal 5 out of -2, 6-3 and 6-4 starts the operation. When refreshing,
It is output onto the refresh address signal 1 from the CPU, added from the address 8 to the dynamic RAMs 6-1 6-2 6-3, 6-4 via the multiplexer 7, and the OR signal 4-is generated by the refresh signal 14.
Select signal 5-via 1,4-2,4-3,4-4
1,5-2,5-3,5-4 are all active,
The specified address is refreshed (at this time, the strobe signal 18 is prohibited by the refresh signal 14 so that actual read / write is not performed).

[Problems to be solved by the invention]

In the conventional dynamic RAM control circuit described above,
In the case of the example in FIG. 2, the requesting operation is performed by the CPU or DM.
Since it is asynchronous with the AC operation, C during refresh operation
When a dynamic access is generated from the PU or the DMAC, the CPU or the DMAC is kept waiting, and the access speed is lowered. Further, in the case of the example of FIG. 3, there is no asynchronous problem between the refresh and the access from the CPU or the DMAC, but when the continuous DMA is performed, the dynamic R which is not accessed.
In AM, data may be lost because refresh is not performed.

[Means for solving problems]

The refresh method of the dynamic RAM of the present invention is D
All dynamic RAM during MA and fresh
By providing a gate circuit for selecting a block and a gate circuit for inhibiting a strobe signal for access to all dynamic RAM blocks other than the dynamic RAM block that should be originally selected during DMA and at the time of refresh, the conventional drawbacks are solved. The feature is that it has been resolved.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a control circuit diagram of a dynamic RAM which is an embodiment of the present invention. In the address signal 1 from the CPU or the DMAC, the upper 2 bits are the decoder 2 and the lower bits are the inputs to the multiplexer 7. The decode signals 3-1, 3-2, 3-3, 3-4 output from the decoder 2 are supplied with the select signal 5-1 via the OR gates 4-1, 4-2, 4-3, 4-4. , 5-2, 5-3, 5-4 and the corresponding dynamic RAM blocks 6-1, 6-2,
Used to select 6-3 and 6-4. The multiplexer 7 outputs the lower half or upper half of the input of the multiplexer to the address line 8 in response to the address switching signal 11 output from the timing circuit 10 in response to the control signal 9 from the CPU or the DMAC. D
The AM mode signal 13 is logically ORed with the refresh signal 14 to become the forced select signal 15 and the OR gate 4-
It is one of the inputs 1,4-2,4-3,4-4. This is all dynamic RAM 6-1, 6-2, 6-3,
Dynamic RA selected by the decoder 2 via the inverter and used to select 6-4
It is used to generate select prohibition signals 16-1, 16-2, 16-3, 16-4 that prohibit access to other than M. The refresh signal 14 is the generation of the forced select signal 15 and the select inhibit signals 16-1 and 16.
Used to inhibit strobe enable signals 17-1, 17-2, 17-3, 17-4 as well as -2, 16-3, 16-4. The control signal 9 from the CPU or the DMAC is used to generate the address switching signal 11 and the strobe timing signal 12 for the dynamic RAM in the timing circuit 10 and also to determine the data transfer direction in the data bus I / F 21. To be Data is exchanged with the CPU and the DMAC by connecting the data bus 22 to the write data signal 19 and the read data signal 20 to the dynamic RAM via the data bus I / F 21.

In this configuration, the decoder 2 decodes the decode signals 3-1, 3-2, 3-3, 3- when accessed from the CPU.
Since one of the four becomes active and the forced select signal 15 is not active, the OR gates 4-1 and 4-
Select signals 5-1 and 5-through 2,4-3 and 4-4
One of 2,5-3,5-4 becomes active,
Any of the dynamic RAMs 6-1, 6-2, 6-3, 6-4 is selected. Further, the lower part of the address signal 1 is output to the address line 8 in the order of the lower half and the upper half, and the strobe / timing signal from the timing circuit 10 causes the strobe signals 18-1, 18-2, 18-.
3,18-4 become active and dynamic RAM
Access to any address of 6-1, 6-2, 6-3, 6-4 is performed (selection signals 16-1, 16-2, 16-2, 16-2, since both DMA mode signal 13 and refresh signal 14 are inactive). 16-3, 16-4
Are all inactive and strobe enable signals 17-1, 1
7-2, 17-3, 17-4 are all active). At the time of refreshing, the refresh address from the CPU is output to the address line 8 through the multiplexer 7, and the refresh signal 14 activates the forced select signal to activate the OR gates 4-1 and 4-.
Select signals 5-1 and 5-through 2,4-3 and 4-4
2, 5, 3 and 5-4 are all activated, and all the dynamic RAMs 6-1, 6-2, 6-3 and 6-4 are selected. At this time, the strobe patent signals 17-1, 17
-2, 17-3, 17-4 are prohibited by the refresh signal 14, so strobe signals 18-1, 18-2,
18-3 and 18-4 are not activated, and the dynamic RAM is refreshed. At the time of access from the DMAC, the forced selection signal 15 is activated by the DMA mode signal 13, all the dynamic RAMs are selected in the same manner as at the time of refresh, and the address information is output to the address line 8 at the same time as the access from the CPU. However, since the DMA mode signal 13 is active, the decode signals 3-1 and 3-from the decoder 2 are generated.
Select inhibit signals 16-1, 16-2, except for those corresponding to active ones among 2, 3, 3 and 3-4.
16-3 and 16-4 become active (one is inactive), and only for the dynamic RAM (one of 6-1, 6-2, 6-3, 6-4) selected by the decoder 2. Strobe signal (18-1, 18-2, 18
Any one of -3 and 18-4) is output for normal access, and at the same time, refresh operation is performed for other dynamic RAMs.

〔The invention's effect〕

As described above, the present invention is directed to a direct memory
By allowing normal access to the dynamic RAM block selected at the time of access and refreshing to the other dynamic RAM blocks, there will be no missed refreshes at the time of direct memory access. There is an effect that data can be retained even when it is not performed.
Moreover, there is no problem of asynchronousness because the operations of the CPU and the DMAC and the refresh are executed while maintaining a synchronous relationship.

[Brief description of drawings]

FIG. 1 is a control circuit diagram of a dynamic RAM according to an embodiment of the present invention, FIG. 2 is a conventional dynamic RAM control circuit diagram using a dedicated refresh controller, and FIG. 3 is a case where a CPU with refresh function is used. It is a conventional dynamic RAM control circuit diagram. 1 ... Address signal, 2 ... Decoder, 3-1 and 3-
2,3-3,3-4 ... Decode signals, 4-1 and 4-
2, 4-3, 4-4 ... OR gates, 5-1 and 5-2
5-3, 5-4 ... Select signals, 6-1, 6-2, 6
-3, 6-4 ... Dynamic RAM, 7 ... Multiplexer, 8 ... Address line, 9 ... Control signal, 10 ... Timing circuit, 11 ... Address switching signal, 12 ... Strobe timing signal, 13 ……
DMA mode signal, 14 ... Refresh signal, 15 ...
... Forced select signals, 16-1, 16-2, 16-3,
16-4 ... select prohibit signal, 17-1, 17-2,
17-3, 17-4 ... Strobe permission signal, 18, 1
8-1, 18-2, 18-3, 18-4 ... Strobe signal, 19 ... Write data signal, 20 ... Read data signal, 21 ... Data bus I / F, 22 ... Data bus , 23 ... Refresh controller, 24
...... Data ready signal.

Claims (1)

[Claims] 1. A plurality of dynamic memory blocks, first means for selecting a specific block from the plurality of dynamic memory blocks by a part of bits of an address, and remaining bits of an address in each memory block. A second means for commonly selecting the same area and a third means for sequentially and continuously reading / writing an area in one memory block selected by a designated address in response to the direct memory access mode. Means and fourth means for simultaneously detecting all the memory blocks other than the one memory block by detecting the direct memory access mode, and in the direct memory access mode, the read / write Normal read / write is performed on the target memory block and the remaining memory block Then, all the memory blocks are selected by using the fourth means, and the addresses given to the memory blocks to be read / written are given to these remaining memory blocks, so that the remaining memory blocks. A dynamic memory refresh method characterized by refreshing the internal area based on the addresses for direct memory access.