JP2511941B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, to a technique effectively used for an expansion memory device in a microcomputer system or the like.

[Conventional technology]

As image processing RAM for displaying characters and graphics on the screen of a CRT (cathode ray tube), for example, Nikkei McGraw-Hill, February 11, 1985, Nikkei Electronics, pages 219-
The serial access memory (dual port RAM) described on page 229 is known. This RAM connects data lines of a memory array to a data register in parallel via a switch circuit and outputs data serially between the data register and an external terminal. As a result, the storage information of the memory cells coupled to the selected word line is serially output, so that the pixel data synchronized with the raster scan timing of the CRT can be easily taken out. In this way, the dynamic RAM is used as a basis for multi-functionalization.

[Problems to be solved by the invention]

For example, in an 8-bit microcomputer system, the physical address space is limited to about 64K. For this reason, if the memory space is to be expanded, it is necessary to perform signal processing such as fetching as a memory address signal for expansion using the data signal. Therefore, when easily expanding the memory space, a floppy disk memory device or the like may be used. However, the use of the floppy disk memory device causes a problem that the system becomes large in size and cost and the access speed is slow. Therefore, the inventor of the present application has considered a novel semiconductor memory device in which serial access is performed like a disk memory based on the above RAM.

An object of the present invention is to provide a novel semiconductor memory device having a serial access function, in which any sector length can be designated.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
For a memory array in which memory cells are arranged in a matrix at the intersections of word lines and data lines, one sector address is assigned to a plurality of bits in the data line direction, and a sector length that specifies the sector address and the number of the plurality of bits. And a signal to a multiplying circuit, the output signal specifies the initial address of the memory array, and the access to the memory cell corresponding to the plurality of bits is substantially serialized in synchronization with a timing signal supplied from the outside. To do so.

[Work]

According to the above-mentioned means, the sector length can be arbitrarily set and the memory space of the system can be easily expanded like the disk memory.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. Although not particularly limited, each circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The semiconductor memory device of this embodiment is not particularly limited, but an address selection circuit for performing a serial access operation as described below is based on a dynamic RAM which is accessed in a unit of 1 bit (× 1 bit structure) as a basic structure. Is added.

Although not particularly limited, the memory array M- in FIG.
ARY has a storage capacity of 1024 × 1024 (about 1 Mbit). Therefore, 1024 X addresses and Y addresses are internally provided. The memory array M-ARY includes, but is not particularly limited to, a dynamic memory cell including an address selection MOSFET (insulated gate field effect transistor) arranged in a matrix and a capacitor for storing information. MO for address selection of the above memory cells
The SFET has its gate coupled to the corresponding word line and its drain coupled to one of the corresponding complementary data lines. That is, the data line is composed of a pair of complementary data lines (folded bit line or digit line system) arranged in parallel. The memory array M-
The ARY data line has a sense amplifier, an active restore circuit if necessary, as well as a known dynamic RAM.
A precharge circuit, a dummy cell and the like are provided (not shown).

The signal on the complementary data line in the memory array M-ARY is transferred to the data latch circuit FF via the switch circuit SW, although not particularly limited thereto. The switch MOSFET that constitutes the switch circuit SW is a transfer timing signal φ.
It is turned on by s to connect each complementary data line of the memory array M-ARY and the latch circuit FF.

In order to output the data held in the latch circuit FF serially or to supply the write signal serially to the latch circuit FF, each complementary holding signal D0,0 to Dn, n of the latch circuit FF is Data is transmitted / received to / from a common data line (serial input / output line) CD, ▲ ▼ via switch MOSFETs Q1, Q2 and Q3, Q4, etc. which are shown by way of example. The switch MOSFETs Q1, Q2 and Q3, Q4 are switch-controlled by an alternative selection signal formed by the shift register SR. In this embodiment, although not particularly limited, the output signal of the final stage of the shift register SR is fed back to the first stage circuit side in order to realize continuous serial input / output in sector units as described above. . As a result, the shift register SR performs a ring-shaped shift operation. An initial value (logic "1") is set in the shift register SR by the decode output signal formed by the Y address decoder YDCR. The shift register SR receives the shift clock signal φ generated by the timing control circuit TC based on the clock signal supplied from the external terminal CK, and shifts the selection signal (logic “1”).

The above serial I / O line CD, ▲ ▼ is the I / O circuit IOB
Is connected to the output terminal of the input circuit and the input terminal of the output circuit. The output circuit is put into operation during a read operation, and the input circuit is put into output high impedance. In addition, the input circuit is set to the operating state during the write operation, and the output circuit is set to the output high impedance state. As a result, data is output or input serially from the external terminal D.

The address buffer ADB takes in the sector address signal SA consisting of a plurality of bits in synchronization with the timing when the chip selection signal ▲ ▼ is set to the low level and supplies it to one input of the multiplication circuit AU. The buffer DLB takes in the sector length DL consisting of a plurality of bits in synchronization with the low level timing of the chip selection signal () and supplies it to the other input of the multiplication circuit AU. As described above, the memory array M-
When ARY has a storage capacity such as 1024 × 1024, for example, the sector address SA is a 10-bit address signal,
The sector length DL is also a 10-bit signal. by this,
The maximum sector length can be specified as 1024 bits.

Since the sector length DL does not usually need to be changed at each memory access, for example, a high level or low level signal is constantly supplied to the terminal according to the sector length DL. Therefore, this sector length DL is
In addition to the one supplied from the external terminal, one that forms the above-mentioned signal by selectively cutting with a fuse means made of, for example, polysilicon or the like, or by incorporating an EPROM,
You may make it write in it.

Of the multiplication result of 20 bits formed by the multiplication circuit AU, the lower 10-bit signal is used as the Y address signal AY and supplied to the Y address decoder YDCR. The upper 10-bit signal is used as the X address signal AX and is sent as the initial value of the address counter circuit ACOUNT.

The address counter circuit ACOUNT supplies the address signal AX to the X address decoder XDCR. The X address decoder XDCR decodes the address signal AX and performs a dummy word line selection operation in synchronization with a word line selection timing signal (not shown) according to the configuration of a predetermined word line and the memory array M-ARY. . As a result, the operation of selecting one word line is performed.

The Y address decoder YDCR decodes the address signal AY and forms an initial value (logic "1") for the shift register SR. For example, when the sector length DL is set to 256 bits, the lower-order address signal AY formed by the multiplication result will always carry out the address designation every 256 bits. Therefore, the Y address decoder YDCR has the leading bit 0 for the shift register SR.
The initial value is set to any one of (0th sector), 256 bits (1st sector), 512 bits (2nd sector), and 768 bits (3rd sector). Also,
When the data length DL designates 512 bits, the address signal AY formed by the multiplication result performs address designation every 512 bits. Therefore, Y
The address decoder YDCR performs the above initial value on either the first bit 0 (0th sector) or 512 bits (first sector) for the shift register SR. Further, when the data length DL specifies 1024 bits, the address signal AY formed by the multiplication result performs addressing every 1024 bits. Therefore, the Y address decoder YDCR always applies the above initial value to the first bit 0 (0th sector) of the shift register SR.

The timing control circuit TC receives the chip selection signal ▲ ▼, the write enable signal ▲ ▼, and the clock signal CK supplied from the external terminals, identifies the operation mode, and forms various timing signals according to them, although not particularly limited. To do. The timing signal includes a word line selection timing signal, a sense amplifier activation timing signal, and the like.

Although not particularly limited, the timing control circuit TC
Is provided with a counter circuit CCOUNT for detecting the serial output operation for one sector. This counter circuit
The initial value of CCOUNT is set by the sector length signal DL, and when a serial output operation corresponding to the specified sector length is detected by performing, for example, a down counting operation in synchronization with the clock signal CK, the control signal SG is input. Output circuit IO
It is supplied to B, and a signal indicating a sector delimiter is transmitted as described later in detail. During this period, generation of the clock signal φ for performing the shift operation is stopped (skipped), and the shift operation is interrupted. Further, in order to continuously access a plurality of sectors across a plurality of word lines, the timing control circuit TC generates the address step-up pulse φc for switching to the next word line selection. Supply to the address counter circuit ACOUNT. Terminal ▲
The ▼ sets its signal to the low level when the last sector is accessed. Therefore, the timing control circuit TC receives the overflow signal CA from the address counter circuit ACOUNT and generates the signal {circle over ()} from the count output of the counter circuit CCOUNT.

The refresh control timer RFTM has a time period necessary for refreshing and generates a refresh address stepping pulse and a refresh control signal REF, which are not particularly limited, but correspond to one rotation of a word line. As a result, the address counter circuit ACOUNT returns to the original address when the refresh operation is completed. In other words, the address specified by the refresh operation is not destroyed. Refresh control signal RE
F is supplied to the timing control circuit TC and generates an internal timing signal for the refresh operation. At this time, access from the outside is prohibited in the refresh mode.

Next, an example of the serial read operation of the semiconductor memory device of this embodiment will be described with reference to the timing chart shown in FIG.

At the timing when the chip selection signal ▲ ▼ changes from the high level to the low level, the buffers ADB and DLB are activated and the sector address SA and the sector length DL are fetched. The timing control circuit TC detects this when the chip select signal ▲ ▼ is changed from the high level to the low level and the write enable signal ▲ ▼ (as shown in the figure) is at the high level, and determines the read mode.

The multiplication circuit AU uses the sector address signal SA fetched above.
And the sector length signal DL are multiplied to supply the lower 10-bit address signal AY to the Y address decoder circuit YDCR. Y
The address decoder circuit YDCR decodes the address and specifies the start address (initial value setting) corresponding to the sector length DL in the shift register SR as described above. Also, the multiplication circuit AU
The upper 10-bit address signal AX output from is set as an initial value in the address counter circuit ACOUNT. The address signal set in the address counter circuit ACOUNT is directly supplied to the X decoder circuit XDCR. As a result, the operation of selecting the word line corresponding to the sector address is performed. The word line selecting operation and the sense amplifier SA amplifying operation are performed by a time-series timing signal generated from the timing control circuit TC. Then, after waiting for the amplification operation of the sense amplifier SA,
A data transfer timing signal φs is generated. As a result, the read signal for the one word line is transferred to the latch circuit.
Transferred to FF.

Waiting for this transfer operation, when the clock signal CK is supplied, the shift register SR starts the shift operation. For example, if the sector length DL is specified as 256 bits as described above, the sector address (0, 256, 5) specified in the shift register SR
12, 768), the selection signal is output in time series, so the holding signal of the corresponding latch circuit (corresponding to the data line) is output in time series in the input / output line. It Therefore, since the output circuit of the input / output circuit IOB is in the operating state in the read mode,
The data D0 to D255 are serially output in synchronization with the clock signal CK. When the above-mentioned serial output operation is started, the timing control circuit TC generates an address advance pulse φc. As a result, the address counter circuit ACOUNT performs a +1 step operation and outputs an address signal corresponding to the next word line. As a result, the X decoder circuit XDCR starts the selecting operation of the word line corresponding to the next address and the amplifying operation of the sense amplifier (not shown).

In the above serial output operation, the counter circuit CCOUNT
Counts the clock signal CK and counts the number of output data. When this count output becomes 0 (256-bit down counting operation), the signal SG is generated and the supply of the clock signal φ supplied to the shift register SR is interrupted (skip). The input / output circuit IOB outputs a predetermined information bit in synchronization with the clock signal CK.
In the figure, a 2-bit signal is output as indicated by hatching. The 2-bit signal is output to a memory interface circuit (not shown) as a signal corresponding to a gap signal in the floppy disk memory device indicating a sector delimiter.

As a result, the interface circuit confirms the output for one sector. For example, when reading is continued, the clock signal CK is simply transmitted.

For example, when the 256 bits are read from the third sector (768) at the beginning as described above, the timing control circuit TC outputs the output signal (S
G) and the lower address AY, the data transfer timing signal φs is generated while the sector gap signal is being output. As a result, the read signal corresponding to the next selected word line is transferred to the latch circuit FF.

Therefore, the supply of the clock signal CK causes the shift register SR to feed back the selection signal (logic "1") from the last bit to the first bit, so that the 0th sector automatically corresponding to the next word line. It is possible to read 256-bit data corresponding to. Also, in parallel with this serial output operation, the timing control circuit TC
Generates an address advance pulse φc. As a result, the address counter circuit ACOUNT performs a +1 step operation and outputs an address signal corresponding to the next word line.
As a result, the X decoder circuit XDCR starts the selecting operation of the word line corresponding to the next address and the amplifying operation of the sensor amplifier (not shown).

In the serial output operation corresponding to the next word line as described above, the counter circuit CCOUNT counts the clock signal CK and counts the number of output data. When this count output becomes 0 similarly to the above, the signal SG is generated and the supply of the clock signal φ supplied to the shift register SR is interrupted (skip). The above-mentioned input / output circuit IOB uses the clock signal CK to transfer the previously specified information bit in the same manner as above.
Output in synchronization with. As a result, the interface circuit confirms the output for one sector. For example, when reading is continued, the clock signal CK is simply transmitted. When the reading of four sectors corresponding to one word line is completed by the same operation, the data transfer operation and the selection switching of the next word line are performed in the same manner as above.

With this, it is possible to automatically read up to the final sector by simple memory control in which the clock signal is continuously supplied only by designating the start sector address.

Although not shown, in the write operation, when the chip select signal ▲ ▼ is set to the low level, the write enable signal ▲ ▼ is set to the low level. As a result, the timing control circuit TC determines the write mode.
Also in this write operation, the selection of the word line and the data transfer operation of the latch circuit are similarly performed. After that, the write signal is serially supplied in synchronization with the clock signal CK. Therefore, in the latch circuit FF, the read signal held in order from the bit designated by the shift register SR is replaced with the write signal.

At the time of write operation, the timing control circuit TC
Similar to the case of the read operation, the shift operation of the final stage in the shift register SR is detected from the address signal AY formed from the multiplication result and the count output of the counter circuit CCOUNT, in other words, the highest address is When the input of write data to the assigned latch circuit FF is determined, the sense amplifier is deactivated and the data transfer timing signal φs is generated. As a result, the signal held by the latch circuit FF is written in parallel to the selected memory cell. As described above, the storage information corresponding to the word line selected for the latch circuit FF is read once because when the second and subsequent sector addresses are specified, the lower sector is also read. This is because it is necessary to hold the information such as This allows serial writing from the first to third sectors.

After the writing, the word lines are switched and the same read operation is performed to the same latch circuit as described above, and then the serial input operation to the latch circuit FF is performed. Even in this case, the reason why the latch circuit FF is read is to hold the information of the subsequent sectors when the last sector to be written is finished in the second and subsequent sectors.

In the memory access as described above, the timing control circuit TC uses the carry signal CA from the address counter circuit ACOUNT for accessing the last sector and the counter circuit.
Judging from the count output of CCOUNT, the end signal ▲ ▼
To low level.

When the sector length is in byte units, eight semiconductor storage devices may be connected in parallel. This is the same as the case where a memory device of x8 bit (1 byte) is configured by a x1 bit dynamic RAM.

The operation and effect obtained from the above embodiment is as follows. (1) For a memory array in which memory cells are arranged in a matrix at intersections of word lines and data lines, one sector address is assigned to a plurality of bits in the data line direction, and the sector address and the number of the plurality of bits are set. And a sector length signal for specifying the sector length signal, which specifies the initial address of the memory array from the output signal, and synchronizes the access of the memory cell corresponding to the plurality of bits with a timing signal supplied from the outside. And make it serial. As a result, the sector length can be arbitrarily set, and the memory space of the system can be easily expanded like the disk memory.

(2) Since the above memory array is basically capable of random access, there is no waiting time caused by a rotating operation like disk memory, and a designated sector can be selected immediately, enabling high speed access. The effect of becoming is obtained.

(3) Since the memory device can be entirely configured by the semiconductor memory device including the interface circuit, it can be configured by a mounting substrate such as a printed circuit board, and an effect that miniaturization and cost reduction can be realized can be obtained.

(4) Since there is no mechanical part like the flop disk memory, it is possible to obtain an effect that high reliability and high durability can be realized as a memory device.

(5) By inserting the signal indicating the inter-sector into the serial output data, it is possible to obtain the effect of facilitating the memory management in the interface section.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the specific configuration of the memory array M-ARY may be configured by a plurality of memory mats in order to shorten the data line length and the word line length. In response to this, a plurality of shift registers are provided. According to such a configuration, the selection operation of the word lines and the shift register and the control of the shift operation are performed so as to perform the operation substantially similar to that of the above embodiment. Further, the shift register can be replaced with a counter circuit and a decoder circuit as in the word line selecting operation. Further, the multiplication circuit may have any specific configuration.

In FIG. 1, the sector length can be arbitrarily designated in addition to the one obtained by equally dividing the number of bits in the data line direction by 2 ^N as in the above embodiment. In this case, one sector may be designated across two word lines. Therefore, during the access to one sector, the interval is the data transfer time to the latch circuit FF in the read operation and the word line selection operation switching and the data transfer time to the latch circuit in the write operation. Will need to be set.

Further, the serial access to the memory array may be performed by omitting the data latch circuit and performing an operation similar to the page mode or column static operation in the dynamic RAM. In this case, since the interval is provided every time the word line is switched, the access operation is delayed, but the internal circuit is simplified accordingly.

The memory array M-ARY may be composed of static memory cells. In this case, since the refresh operation as described above becomes unnecessary,
Higher-speed access is possible. Further, it may be a read-only memory such as an EPROM or a mask ROM.

The present invention can be widely used in various information processing systems as a semiconductor memory device having a serial memory access function in units of a plurality of bits.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, for a memory array in which memory cells are arranged in a matrix at the intersections of word lines and data lines,
One sector address is assigned to a plurality of bits in the data line direction, and the sector address and a sector length signal designating the number of a plurality of bits are supplied to a multiplication circuit,
An initial address of the memory array is designated from the output signal, and the memory cells corresponding to the plurality of bits are accessed substantially serially in synchronization with a timing signal supplied from the outside. As a result, the sector length can be arbitrarily set, and the memory space of the system can be easily expanded like the disk memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing an example of its operation. M-ARY ... Memory array, SW ... Switch circuit, FF ...
… Latch circuit, SR …… Shift register, ADB …… Address buffer, DLB …… Buffer, AU …… Multiplication circuit, ACOUN
T ... Address counter, XDCR ... X address decoder, YDCR ... Y address decoder, RFTM ... Refresh timer, TC ... Timing control circuit, CCOUNT ... Counter circuit, IOB ... I / O circuit

Claims (2)

(57) [Claims] 1. A memory array in which memory cells are arranged in a matrix at intersections of word lines and data lines, a multiplication circuit which receives a sector address and a sector length, and generates first and second address signals, A first decoder which forms a first selection signal for selecting the word line by a first address signal; a second decoder which forms a second selection signal by the second address signal; and the data A latch circuit connected to the line via a first switch circuit; a second switch circuit having one end coupled to the latch circuit and the other end coupled to an input / output line for serial access; The initial value is set by the second selection signal, and the shift register that sequentially operates the second switch circuit according to the timing signal is synchronized with the external clock and before. And a timing control circuit for generating the timing signal in which an interruption period is provided for each number of bits of the sector length and for generating a signal indicating a sector delimiter for each number of bits of the sector length. Storage device. 2. The semiconductor memory device according to claim 1, wherein the memory cell is a dynamic memory cell.