JPS58169248A - Control system of program counter provided with input condition selector - Google Patents

Abstract

PURPOSE:To continue processing securely from a state existing right before a DMA request when DMA processing ends, by providing an FF for holding a plural-bit flag for conditional branching to be inputted to a selector, and stopping a clock to the FF by the output of a delay circuit for permitting the DMA processing. CONSTITUTION:A program counter 1 with an input condition selector is connected to an ROM4 stored with a program and this counter 1 is provided with an ROM2, FF3, and selector 5. Further the FF10 which inputs the plural-bit flag for conditional branching to the selector 5 and an AND circuit 11 for controlling the clock to the FF10 are provided. When the DMA request is generated, a DMA permitting signal outputted from the delay circuit 9 is applied to the circuit 11 to stop the clock to the FF10 by the output of the circuit 11, and the flag for conditional branching before the DMA is performed is held in the FF10 to continue the processing securely from a state existing before the DMA request.

Description

[Detailed description of the invention] (-Technical field of the invention) Program counter control with input condition selector *J) Direct memory access (hereinafter referred to as DMA)
0 To) Technology background Input condition selector regarding a program counter control system with an input condition selector that reliably holds the 7 lags for conditional branching of the augend bit input to the selector in the state immediately before the DMAt' request at the time of request The attached program counter is a program counter that uses the input card selector attached order circuit, which the applicant of the present patent applied for in 1957, as a program counter.
The outline of the sequential circuit with input condition selector consists of a read-only memory (hereinafter referred to as ROM) and 7 lip-flops (hereinafter referred to as FF), and the FF4D output is the output of the current state.
Input this and the input conditions of multiple bits to the ROMK,
A selector for selecting a predetermined one bit from among the input conditions of the plurality of bits, and a means for outputting a selection signal for making this selection, to the sequence circuit whose output becomes the output of the next state. Provide a ROMK, select the light 1 bit in the ROM
The capacity of the ROM can be reduced by changing the input conditions. The present invention relates to a control system for this program counter with input condition selector.

(a) Prior art and problems Figure 1 is a block diagram of the main parts of the control circuit of a conventional program counter with input condition selector, and Figure 2 is a time chart of each part of Figure 1. Clock, (6
) is the DMA request signal, 0 is the output of FF8, 0 is the transfer to FF3, (g) is the program address (input to ROM4), the program instruction output (output of ROM4),
Q is a multi-bit conditional branch flag, 0 is a DMA permission signal, 1 in the figure is a program counter with input condition selector, 2 is ROM, 3.8 is FF%, 4 is ROM containing the program, 5 is a selector, 6 is an AND circuit, 7
is a knot circuit, 9 is j! #1 shows the circuit 0 In this circuit, Figure 82 @O like < D MAI! When a request signal comes, FF
The output of 8 is like 0 after half a cycle (11 in the DMA processing bottle)
0 This signal, which is the output of 1m, and the AND circuit 8&
From C, 0) like (FF3 to hemata-7JP?801
7], F) + 2) < ROM4 output NO・0PE
RATION command, pro NO, 1, NO, 2, N
O, 3 is the program address NO, 1, NQ 2.
No, 3K compatible, NOP is No-OPEfLA'
Indicates l'ION. Since the transfer to FF3 stops, the multi-bit conditional branch flag that is the output of selector 5 becomes (
As shown below, DMA permission is available and immediately before DMA execution,
NO, 4O stops due to the situation 0ΩONα2. NQalNo.
, 4 is output after the execution time of the l instruction is changed by the program address extension 9.
When the process is completed, Riyotsuku is sent to FF3 and continues to operate from the position immediately before DMA execution. However, DMA'jl
i! During the line, the flag for conditional branching of multiple bits of No. 4 may change if the front stop is stopped.
When the DM processing is finished, the operation must continue from the state immediately before the DMA execution, but there is a drawback that the operation is different and cannot be continued. An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a program counter-controlled system with an input condition selector that can reliably continue operation from the state immediately before DMA execution after completion of DMA processing. Structure: In order to achieve the above-mentioned object, the present invention includes a programmable flop control circuit with an input condition selector, which is equipped with a tree flop that holds a flag for branching to a plurality of pins input to the selector. The clock to the flip-flop is stopped at the output of the universal circuit that grants DMA permission, and the 0IId + branch flag immediately before the DMA'4 line is held so that it does not change during DMA execution. ! I#Mold.

(O Examples of the Invention Below, one implementation of the present invention will be explained according to the drawings with MK. Third
The figure shows a program control circuit 01 with an input condition selector according to an embodiment of the present invention! block diagram of the division, the 4th WJ is the 3rd
In the time chart of each part in the figure, (to) the pin, (to) the DMA permission signal, and (QaFFt.

This is the clock.

Items in the figure that have the same functions as those in Figure jlE1 are indicated by the same symbols.
O indicates an FF, and 11 indicates an AND circuit.

The only difference between FIG. 3 and FIG. 1 is that FF10 holds a multi-bit conditional branch flag, and a rounding AND circuit 11 is provided to control FF10.
The normal operation is the same as the explanation in Figure 1.
tI shown in MA permission signal @? Outputs a DMA permission signal! Output tube of delay circuit 9, 710 in AND circuit 11,
(As shown in Q (, stop clock to FF10 now, FFI
By holding the conditional branch flag of multiple bits immediately before the DMA execution in step O, the conditional branch flag does not change during the DMA execution.

Therefore, continuation processing can be reliably executed after the DMA processing is completed.

(ω) Effects of the Invention As can be made clear in more detail, the present invention has the effect of being able to reliably continue processing from the state immediately before the DMA request after the completion of the first-flight processing.

[Brief explanation of drawings]

Figure 1 is a four-dimensional diagram of the main parts of the control circuit of a conventional daily gram counter with input condition selector, Figure 2 is a time chart of each part in Figure 1, and Figure 3 is the input. Program counter with condition selector, 2iiROM, 3, 8.1
0 is FF, 4 is 80M% containing the program, 5 is selector, 6゜11 is AND circuit, 7 is NOT circuit, 9
is a delay circuit. Fig. 1 Fig. 2 (D) FF3a ri D-tsuku (H) C1MA11F signal available Fig. 3

Claims (1)

[Claims] When a direct memory access is requested, the output of the first flip-flop holding this signal stops the clock to the program counter, disables the instruction indicated by the program counter, and outputs the first flip-flop. In a program counter control circuit with an input φ selector that uses the output of a delay circuit that delays the output as a direct memory access permission signal, a second O7 lip 7 that holds a multi-bit conditional branch flag is input to the selector.
A program counter control method with a manual condition selector that is equipped with a 0 knob and stops the clock to the second 7 lip-flop by the output of the cough delay circuit when a direct memory access is requested.