JPH0728644A - Data processor - Google Patents

Abstract

PURPOSE:To report misprogramming which breaches the restrictions of the number of nests of subroutine calls to the outside by enabling a call and a return instruction and shortening the length of a microprogram, decreasing the physical size of a memory, and further monitoring the number of nests of the subroutine calls of the microprogram stored in the memory. CONSTITUTION:The output of an instruction register 102 is connected to a program counter 110 and a storage means 104 for storing an address is added to the program counter 101. Further, a circuit 121 which monitors the nesting state of the subroutine calls is provided. Consequently, a branch instruction is actualized and the length of the microprogram can be shortened. The misprogramming which breaches the restrictions of the number of nests of the subroutine calls can be reported to the outside, so the burden on a programmer is lightened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit having a built-in memory.

[0002]

2. Description of the Related Art In a conventional data processing apparatus, as shown in FIG. 2, an address counting means 110 (hereinafter referred to as a program counter) is provided in an address signal line group 117 of an instruction information storage means 101 (hereinafter referred to as a memory). Connected, memory 1
01 outputs an instruction signal corresponding to the address signal line group 117 to the instruction storage unit 102 (hereinafter referred to as an instruction register), and the instruction register 102 is a register or an arithmetic operation target of the instruction stored in the memory 101. It was configured to send data to a processing device or the like. The control signal generation circuit 109 is a circuit that generates control signals 111 to 114 and 103 for controlling the operations of the program counter 110 and the instruction register 102.

However, in the above-mentioned conventional technique, the program counter 110 has only a memory address increment function, so that the instructions on all the memories 101 are always executed without branching until the count up to the final address. Therefore, the first problem is that the microprogram, which is a group of instructions stored in the memory 101, becomes long when performing complicated processing, and the physical size of the memory becomes large.

Further, even if the first problem is solved by improving the hardware capable of executing a branch instruction, the length of the program is reduced when the same process is used a plurality of times in the program. There is a second problem that the physical size of the memory 101 becomes large because it is proportional to the number of times of processing in the program.

Further, there is a third problem that the data processing device malfunctions when the nesting number of the subroutine in the microprogram exceeds the storage capacity of the address temporary storage means.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to change the information of the program counter by a program and store the return address after the end of the jump process. Is to reduce the physical size of. A further object of the present invention is to monitor the nesting number of the subroutine calls of the microprogram stored in the memory and output the error occurrence output signal to the outside so that programming mistakes that violate the constraint of the nesting number of the subroutine calls can be performed externally. There is a place to inform.

[0007]

The above-mentioned object is to provide a command information storage means for storing command information, a command storage means for receiving and storing the command information, and a control signal group according to output data of the command storage means. In a data processing device comprising a control signal generating circuit for generating a signal and an address counting means for receiving an output signal of the control signal generating circuit as a reference clock and counting the reference clock to determine an address of the instruction information storage means. This is achieved by providing a path for transferring a part of the output signal of the instruction storing means to the address counting means.

Further, the above object can be achieved by providing at least one address temporary storage means controlled by a control signal from the control signal generation circuit according to arbitrary instruction information of the instruction storage means.

The above object is further achieved by providing an address temporary storage means with a monitoring circuit which is controlled by a control signal from the control signal generating circuit according to arbitrary instruction information in the instruction storage means.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 3 to 15. FIG. 1 is a diagram showing an embodiment of the present invention. The memory 101 includes the address signal line group 11
It has 10 address terminals connected to 7 and 16 memory output terminals connected to the first output signal line group 118 (hereinafter referred to as memory output signal line group). That is, the memory 101 corresponds to a read-only memory of 1024 words × 16 bits. Instruction register 102
Takes in command information from the memory 101 via the first signal line group 118 (hereinafter referred to as memory output signal line group), and the take-in timing is determined by the control signal inputted from the tenth control terminal 103. The instruction register 102 transfers a part of the instruction information held by itself to the program counter 110 and a general-purpose register not shown in the figure via the first control signal line group 107, and the second control signal line group. The signal is supplied to the control signal generation circuit 109 via 108. The program counter 110 stores the count value in the address temporary storage means 1 via the second output signal line group 119.
The address temporary storage means 104 can return the count value temporarily held to the program counter 110 via the third output signal line group 120.

FIG. 3 is a diagram showing an embodiment of the program counter 110 shown in FIG. The program counter 110 is composed of 10 blocks when the first storage unit 301, the half adder 302, and the second storage unit 303 are considered as one block. The first storage unit 301 is composed of the circuit shown in FIG. In the fifth storage unit 401 shown in FIG. 4, the terminal C is L
When OW, the terminals D and M are conductive, that is, the terminal D
The signal applied to the terminal M is directly output from the terminal M, and when the terminal C is HIGH, the signal output from the terminal M before that is held. Second storage means 303
Is composed of the circuit shown in FIG. The fifth storage means 501 and 502 described in FIG. 5 operate in the same manner as the fifth storage means 401 described in FIG.
An example of the half adder 302 is as shown in FIG.

FIG. 7 is a diagram showing one embodiment of the instruction register 102 shown in FIG.
The storage means 701 of FIG. The fifth storage means 701 is the fifth storage means 40 described in FIG.
Performs the same operation as 1.

FIG. 8 is a diagram showing one embodiment of the address temporary storage means 104 shown in FIG. 1, and is composed of ten second storage means 801. The second storage unit 801 operates in the same manner as the second storage unit 303 shown in FIG.

FIG. 9 shows the monitoring circuit 1 described in FIG.
21 is a diagram showing an example of No. 21. FIG. The up / down counting means 901 in FIG. 9 is a 2-bit binary counter, and
The A terminal outputs the lower bits and the DB terminal outputs the upper bits. The first control terminal 123 is the up / down counting means 9
01 reset terminal, HIGH, DA terminal, D
Both outputs of the B terminals are LOW, and when LOW, they operate as a counter. When the clock is input to the CU terminal, the up / down counting means 901 is incremented and the CD
It is decremented when a clock is input to the pin. Therefore, in terms of the function of the monitoring circuit 121, the input signal of the second control terminal 105 is an execution signal for transferring data from the program counter 110 to the address temporary storage means 104, and the input signal of the third control terminal 116 is Since the execution signal is an execution signal for returning data from the address temporary storage means 104 to the program counter 110, if the capacity of the address temporary storage means 104 is only one layer, the DB terminal will not be HIGH at all. And therefore the DB
The terminal can be regarded as the error occurrence output terminal 122.

In order to explain the embodiment of FIG. 1, the instruction code shown in FIG. 10 is defined, and the operation of each instruction will be described with reference to the microprogram 0 shown in FIG. 11 as an example.
And FIG. 14 will be described. However, "#n" of the OTHER #n instruction described in FIG. 10 is a number, and the corresponding microcode is a code that does not conflict with the JMP instruction, the CALL instruction, and the RET instruction.

FIG. 12 is a timing chart when the OTHER #n instruction is executed. The operation will be described from time T0.

In this example, the fourth, fifth and third control terminals 115, 111 and 116 are LOW and H, respectively.
Program counter 1 in IGH and LOW states
Numeral 10 increments the address of the memory 101 by one when the sixth control terminal 112 falls. Time T0 to T1
At this time, the ten first storage means 301 in the program counter 110 (hereinafter, referred to as the first storage means group 301, and when other storage means also indicate a plurality of storage means, are referred to as storage means group) Address information 0 held before that
02H is incremented at the rising edge of the sixth control terminal 112 to form 003H, and new data 003H is held and output to the address signal line group 117 (A0 to A9). The memory 101 receives the new address information 003H, and outputs hexadecimal data 0000H (hereinafter referred to as data 0000H), which is a microcode of the OTHER1 instruction stored in the corresponding area, to the memory output signal line group 118 (D0 to
Output to D15).

At time T2, the seventh control terminal 113 rises to apply HIGH to the A terminal of the half adder 302. The half adder 302 includes the data (A0) stored and held in the first storage unit 301 and the seventh control terminal 113.
The data "1" given from is added, and the addition result S
0 to the D terminal of the second storage means 303, and carry result S1
To the A terminal of the half adder of the upper block. The operation of the half adder 113 is the same in the other 9 blocks, and as a result, the data stored and held in the first storage unit group 301 is incremented by 1 to the second storage. Inform the means group 303. Furthermore, the rising of the seventh control terminal 113 causes the second storage means group 3
The L terminal of 03 becomes HIGH, and the second storage means group 30
3 is in the data write enable state.

At times T3 and T4, the half adder group 3 is driven by the falling and rising operations of the eighth control terminal 114.
The data incremented from 003H to 004H in 02 is written via the D terminal of the second storage unit group 303. At this time, a signal is also input to the ninth control terminal 106 at the same timing as the eighth control terminal 114, but since the second control terminal 105 is in the LOW state, no data is stored in the address temporary storage means 104. Not written.

At times T6 to T7, the tenth control terminal 103
As a result, the instruction register 102 stores the data 0000H which is a microcode corresponding to the instruction OTHER1 held in the memory 101. The control signal generating circuit 109 receives the second output signal line group 108, decodes the data 0000H issued from the memory 101, and outputs the fourth signal.
Control terminal 115 in the LOW state, the fifth control terminal 111
And the LOW state of the third control terminal 116 are continued.

Times T8, T9, T10, T11, T12, T13,
The operations at T14 and T15 are the same as those at times T0, T1, T2, T3, T4, T5, T6 and T7 in FIG. 12, respectively.

FIG. 13 is a timing chart when the JMP instruction is executed.

Times T16, T17, T18, T19, T20, T2
Operations at 1, T22, and T23 are the same as those at times T0, T1, T2, T3, T4, T5, T6, and T7 in FIG. 12, respectively. However, the control signal generation circuit 109 at time T22
Receives a JMP command from the second output signal line group 108,
The data 0410H issued from the memory 101 is decoded, the fourth control terminal 115 is set to HIGH, the fifth control terminal 111 is set to LOW, the third control terminal 116 is set to LOW, and the first control signal line group is set. Data writing from 107 to the first storage unit group 301 is permitted. Also JMP
In the instruction, the branch destination address 010H is given as data to the first control signal line group 107.

At times T24 and T25, the sixth control terminal 112
The address 010H is written from the first control signal line group 107 to the first storage means group 301 due to the change of the signal of the signal No.
To 010H.

Times T26, T27, T28, T29, T30, T31
The operation of time is time T2, T3, T in FIG.
4, same operation as T5, T6, T7. This makes it possible to process the instruction at the branch destination address thereafter.

FIG. 14 is a timing chart when the CALL instruction is executed.

In the CALL instruction, the program counter 11
The operation of 0 is the same as the JMP instruction, but from time T42 to T45.
At the time, an operation of sending the count data of the program counter 110 to the address temporary storage means 104 is added.

At time T42, the control signal generating circuit 109
In response to the result of decoding the data 0820H being the CALL instruction, the second control terminal 105 is changed to HIGH,
The second storage means 801 in the address temporary storage means 104 is set in the input permission state.

At times T43 and T44, the ninth control terminal 106
The data 012H on the second output signal line group 119 is written in the address temporary storage means 104 due to the change in the signal of
The value of the third output signal line group 120 is fixed to 012H. As a result, it becomes possible to refer to the return address when the RET instruction is performed.

FIG. 15 is a timing chart when the RET instruction is executed.

The operation from time T48 to T63 is time T16 in FIG. 13 except time T54 to T57 which will be additionally described below.
~ Same operation as T31.

At times T54 and T55, the control signal generation circuit 10
9 receives the second output signal line group 108 and receives the memory 101
The data 0C00H issued from is decoded, the fourth control terminal 115 is LOW, the fifth control terminal 111 is LOW,
By controlling the third control terminal 116 to be HIGH, data writing from the third output signal line group 120 to the first storage means group 301 is permitted.

At times T56 and T57, the sixth control terminal 112
Data 012H on the third output signal line group 120 is written to the first storage means group 301 by the change of the signal of
Therefore, the memory output signal line group 117 changes the address 021H.
To 012H. Therefore, the CAL that was previously executed
It is possible to return to the address next to the L instruction.

Next, using the instruction code defined in FIG. 10,
It will be described with reference to FIGS. 16, 17 and 18 based on a specific programming example.

FIG. 16 shows an example of programming in the conventional data processing device shown in FIG. The program counter 110 counts up to 3FFH and then returns to 000H. Since there is no branch instruction, the entire program area will be used.

In FIG. 17, the output signal line group from the instruction register is connected to the program counter in FIG.
It is a programming example when it is modified so that the P instruction can be used. Since the JMP instruction can be used, the same operation as that of FIG. 15 can be realized in 21 lines.

FIG. 18 shows that the OTHER #n instruction, by connecting the output signal line group from the instruction register to the program counter in FIG. JMP
Not only the instruction but also the CALL instruction and the RET instruction can be used, and the same operation as that in FIG. 16 can be realized in 17 lines. However, it is possible to use the CALL instruction further in the series of processes called by the CALL instruction, depending on the specifications of the storage capacity of the address temporary storage means 104, but there is a limitation and the state of the address temporary storage means is changed. The need arises to monitor.

The operation of the monitor circuit 121 will be described. When the CALL instruction is executed, time T in FIG.
When the second control terminal 105 rises at 42, the up / down counting means 901 becomes a state having an increment function. 9th control terminal 1 at time T43, T44
A clock is input to 06, and up / down counting means 90
1 is incremented and the nesting number of the subroutine call is counted up. When the CALL instruction is executed and the nesting number is 1 when the CALL instruction is executed, the up / down counting means 901 counts up to 2H and the error occurrence output terminal 122 changes from LOW to HIGH. Therefore, the monitoring circuit 121 informs that there is a programming error in the program that violates the constraint of the nesting number of subroutine calls. When the RET instruction is executed, FIG.
As the third control terminal 116 rises at time T54, the up / down counting means 901 becomes in a state having a decrement function. At times T59 and T60, the clock is input to the ninth control terminal 106, the up / down counting means 901 is decremented, and the nesting number of the subroutine call is counted down. When the CALL instruction has not been executed and the nesting number is 0 when the RET instruction is executed, the up / down counting means 901 changes to 3H, and the error occurrence output terminal 12
2 changes from LOW to HIGH, so that the monitoring circuit 12
1 indicates that there was a programming mistake in the program that violates the constraint on the number of nesting of subroutine calls. When the JMP instruction and the OTHER #n instruction are executed, the second control terminal 105 and the third control terminal 116
Both remain in the LOW state, the up-down counting means 901 does not change. After all, the up / down counting means corresponds to counting the nesting number of subroutine calls in the microprogram. The error occurrence output terminal is LOW when the counting state of the up / down counting means 901 is 0H, 1H and HIG when the counting state is 2H, 3H.
Output H.

In the above embodiments, the case where the number of the address temporary storage means is one has been described, but it is also possible to realize the case of two or more, and the nesting of the subroutine call can be performed by the number of the provided address temporary storage means. . However, the internal circuit of the monitoring circuit also requires the number of up-down counting means and decoders corresponding to the nesting number. FIG. 19 shows an embodiment in which two address temporary storage means are used.

The memory size is 1024 words.
The present invention is not limited to X 16 bits, and can be realized for data processing devices of other memory sizes.

[0041]

According to the present invention, a branch instruction can be realized by connecting the output signal line of the instruction register to the program counter, and as a result, the length of the microprogram can be shortened and the program counter can be shortened. By providing the address temporary storage means at the address, the call and return instructions can be realized, and as a result, the same processing can be made into a subroutine, so that the length of the microprogram can be shortened, and thus the physical size of the memory can be reduced. Have an effect. Furthermore, by providing a monitoring circuit, the nesting number of subroutine calls of the microprogram stored in the memory can be monitored and the error occurrence output signal can be output to the outside, so programming errors that violate the nesting number of subroutine calls can be prevented. It also has the effect of reducing the burden on the program creator by informing the user.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional data processing device.

FIG. 3 is a diagram showing an embodiment of an address counting means shown in FIG.

FIG. 4 is a diagram showing an example of a first storage unit shown in FIG.

5 is a diagram showing an embodiment of a second storage means shown in FIG. 3 and a second storage means shown in FIG. 8. FIG.

FIG. 6 is a diagram showing an example of a half adder described in FIG. 3;

FIG. 7 is a diagram showing an embodiment of an instruction storage unit shown in FIG.

FIG. 8 is a diagram showing an embodiment of an address temporary storage means shown in FIG.

FIG. 9 is a diagram showing an embodiment of the monitoring circuit shown in FIG. 1.

10 is a diagram showing an example of instruction codes that can be defined on the hardware of FIG.

11 is a diagram showing an example of a micro program for explaining the operation of the instruction code defined in FIG.

12 is a diagram showing the timing of each signal when the OTHER # n instruction defined in FIG. 10 is executed.

13 is a diagram showing the timing of each signal when the JMP instruction defined in FIG. 10 is executed.

14 is a diagram illustrating the execution of the CALL instruction defined in FIG.
It is the figure which showed the timing of each signal.

FIG. 15 is a diagram showing the timing of each signal when the RET instruction defined in FIG. 10 is executed.

FIG. 16 is a diagram showing an example of a microprogram created only by an OTHER #n instruction.

FIG. 17 is a diagram showing an example of a microprogram created by an OTHER #n instruction and a JMP instruction.

FIG. 18: OTHER #n instruction, JMP instruction, CAL
FIG. 9 is a diagram showing an example of a microprogram created by an L instruction and a RET instruction.

FIG. 19 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

101 command information storage means 102 command storage means 103 tenth control terminal 104 address temporary storage means 105 second control terminal 106 ninth control terminal 107 first control signal line group 108 second control signal line group 109 control Signal generating circuit 110 Address counting means 111 Fifth control terminal 112 Sixth control terminal 113 Seventh control terminal 114 Eighth control terminal 115 Fourth control terminal 116 Third control terminal 117 Address signal line group 118th 1 output signal line group 119 2nd output signal line group 120 3rd output signal line group 121 monitoring circuit 122 error occurrence output terminal 123 1st control terminal 301 1st storage means 302 half adder 303, 801 Second storage means 401, 501, 502, 701 Fifth storage means 402, 403, 404, 503, 602, 02,9
03 2-input AND circuit 405 3-input AND circuit 504, 904 Inverter circuit 601 Exclusive OR circuit 901 Up-down counting means

Claims (3)

[Claims] 1. A command information storage means for storing command information, a command storage means for receiving and storing the command information, and a control signal generation circuit for generating a control signal group according to output data of the command storage means. An output signal of the instruction storage means in a data processing device configured to receive an output signal of the control signal generation circuit as a reference clock and count the reference clock to determine an address of the instruction information storage means. And a path for transferring a part of the data to the address counting means. 2. The data processing device according to claim 1, further comprising at least one address temporary storage means controlled by a control signal from said control signal generation circuit according to arbitrary instruction information of said instruction storage means. A data processing device characterized by the above. 3. The data processing device according to claim 1, further comprising: an address temporary storage means with a monitoring circuit, which is controlled by a control signal from the control signal generation circuit according to arbitrary instruction information of the instruction storage means. A data processing device characterized by the above.