JP3424430B2 - Processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction cache device for an information processing device such as a personal computer.

[0002]

2. Description of the Related Art In recent years, information processing apparatuses such as personal computers have been required to realize moving image processing and three-dimensional graphics processing in order to realize video conference systems, easy-to-understand presentation systems, and more powerful games. It is rising. Conventionally, these processes were often performed using dedicated hardware. When a new algorithm is developed due to the lack of flexibility when using dedicated hardware, it is necessary to redesign the hardware, and in order to execute multiple different processes, There was a problem that the number of hardware corresponding to the type was required. Therefore, recently, there is an increasing tendency to implement these processes by using programmable hardware such as a processor.

However, since these processes handle a huge amount of data, many arithmetic processes are required to realize these processes. Therefore, improving the processing performance of the processor is an essential condition.

To improve the processing performance of the processor,
There are means such as improvement of clock frequency and simultaneous execution of plural processes. In recent years, the degree of integration of LSIs has improved, and it has become easy to implement a plurality of processing units in one LSI. That is, the performance of the processor can be improved by simultaneously executing a plurality of processes using a plurality of processing units. When a plurality of processes are executed in parallel, there is a problem of process dependency. This will be described with reference to FIG.

FIG. 1 shows an example of processing executed by the processor. In this figure, each process is supposed to be sequentially executed one by one from the top. Arrows represent substitution. For example, the process 0 is the value of the variable B and the variable C.
Is added and the result is assigned to the variable A. Since the value of the variable A is obtained as a result of performing the process 0, the process 1 cannot be executed before the execution of the process 0 is completed. Therefore, processing 0 and processing 1 cannot be executed in parallel. On the other hand, the variables B and C used by the process 2 do not depend on the result of the process 1. Therefore, the processing 1 and the processing 2 can be executed at the same time. In this way, when a certain program is executed in parallel by a plurality of processing units, it is necessary to check whether or not parallel processing is possible and the dependency relation between the processing.

As a method for executing a plurality of processes in parallel,
The superscalar method is currently the mainstream.
Generally, a processor using the superscalar method
One process is represented by one command. With this method,
When a process is executed, some instructions are stored in a buffer, an instruction that can be executed in parallel is searched in the buffer, and these are executed at the same time. In this case, the range in which an instruction that can be executed in parallel can be searched for is limited by the capacity of the buffer. For this reason, even if the processes can be originally executed in parallel, it may not be possible to detect that they can be executed in parallel due to the limitation of the buffer capacity, and thus the processes may not be executed in parallel. In addition, since hardware for detecting instructions that can be processed in parallel is required, problems such as an increase in hardware scale occur.

As a method to counter this, a method which is currently receiving attention is a very long instruction word (hereinafter, VLIW: Very).
Long Instruction Word). This is a method in which the compiler examines the dependencies between the processes at the time of compilation, collects the processes that can be executed in parallel into long instruction words, and inputs them to the processor. For example, in a 4-parallel VLIW processor, 1
The instruction is composed of four fields, and the position of the field and the processing device to be processed have a one-to-one correspondence.
When the width of one field is 32 bits, the length of one instruction is a fixed length of 128 bits. As described above, since the length of one instruction is much longer than that of the conventional processor, the VL
The name is IW.

In this method, since software detects processing that can be executed in parallel, it is possible to search for instructions that can be executed in parallel from a wider range than in the superscalar method, and execute more processing in parallel. Is possible.

In the VLIW processor, when the degree of parallelism of processing is low and valid processing cannot be assigned to all instruction fields, in order to keep the instruction length constant, the instruction fields to which valid processing cannot be assigned are kept. The unprocessed field (hereinafter, NO
P: Abbreviated as No Operation).

Generally, a program has a portion having a high degree of parallelism and a portion having a low degree of parallelism. A large number of NOPs are inserted in the portion where the degree of parallelism is low, which increases the program size. As the program size increases, the efficiency of using the instruction cache decreases, and the hit rate of the instruction cache decreases. Also,
There is also a problem that the amount of data increases when an instruction is transferred from the main memory to the processor.

In order to solve this problem, Japanese Unexamined Patent Publication (Kokai) No. 5-2
Japanese Patent No. 576887 describes a method in which a superscalar method and a VLIW method are selectively used depending on the parallelism of processing. That is, in this system, the superscalar system is used in the processing part having low parallelism, and the VLIW system is used in the part having high parallelism.

However, this system requires hardware for detecting parallelism in order to realize the superscalar system, as compared with pure VLIW, which causes problems such as an increase in hardware scale and an increase in design period. Occur.

[0013]

In order to solve this problem, in the present invention, the NOP is deleted when the program is stored in the main memory and the instruction cache.
Restore the NOP on the way of transferring the instruction from the instruction cache to the processing unit. Attribute information is added to each instruction in order to restore the deleted NOP, and this is used to restore the instruction before compression.

In this system, when the instruction field and the attribute information having different sizes are placed at consecutive addresses, the start address of each instruction is determined when the total of the instruction field length and the attribute information length is not an integral multiple of 1 byte. Since there is no start from a byte boundary, updating the program counter becomes complicated.

[0015]

In order to solve this problem, in the present invention, the instruction space is composed of a set of a plurality of instruction fields and a set of attribute information corresponding to each instruction field one to one. It is divided into units called blocks, and attribute information is managed for each block.

By using the present invention, even if the total of the instruction field length and the attribute information length is not an integral multiple of 1 byte, it is possible to arrange the instruction field so that it starts from a byte boundary. Thereby, the control of the program counter can be simplified.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Instruction compression by a processor according to the present invention will be described with reference to FIGS. Figure 2
Is an original instruction sequence to be compressed, FIG. 3 is an instruction sequence after compression, FIG. 4 is an instruction space configuration, and FIG. 5 is a block configuration.

First, the instruction compression method will be described by taking the instruction sequence of FIG. 2 as an example. In this figure, each rectangle (900a, 900b, ...) Is an instruction field. In this embodiment, each instruction field has a fixed length of 32 bits. Four command fields in one horizontal row are 1
Compose an instruction. For example, four instruction fields 900a-d constitute one instruction, which are executed simultaneously.

Process n (n = 0 to 12) in the figure is an instruction field indicating a process such as an operation. NOP is an unprocessed field in which no processing is performed. In the processor of this embodiment, the position of the instruction field in the instruction determines the processing device that processes the instruction field. That is, the instruction field located in the nth field in the instruction is processed by the nth processing unit. Therefore, the position of the instruction field must be maintained in order for the instruction to execute correctly. The NOP is used to insert into the instruction field where there is no valid operation to hold the position of the instruction field.

In this embodiment, the instruction compression is performed N times from the instruction sequence.
This is done by deleting the OP. However, if the NOP is simply deleted from the original instruction sequence, the deleted NO
The original instruction sequence cannot be restored at the time of execution because the location to restore P is unknown. Therefore, in this embodiment, when the NOP is deleted, the attribute information including the field number and the final flag is created and added in a one-to-one correspondence with the instruction field. Delete NOP from the instruction sequence in FIG.
The one to which the attribute information is added is shown in FIG.

The field number is information indicating which number field in the instruction before compression the corresponding instruction field is. If the field number is n, the corresponding instruction field exists at the position of the field n of the instruction before compression. That is, the instruction field will be processed by the processor n. For example, since the field number of the process 0 is 0, the process 0 is located in the field 0 in the original instruction sequence and is processed by the processor 0. The number of bits of the field number per instruction field is determined by the number of processing units. If the field number is i bits, a maximum of 2 i processing units can be handled. In this embodiment, the bit width of the field number is 3 bits. Therefore, it is possible to handle up to eight processing units.

The final flag is information indicating whether the corresponding instruction field is the final field in the instruction. If the final flag is 1, the corresponding instruction field is NO
It is the final field in the instruction after P is removed. For example, since the final flag 920a of the process 0 is 1, the next process 1 is included in another instruction.

By using these two pieces of attribute information,
The instruction sequence before compression can be restored from the instruction sequence after compression. In this method, in order to restore the original instruction from the compressed instruction sequence, attribute information corresponding to the instruction field is necessary in addition to the instruction field.

Generally, the width of data handled by the information processing device is 2 to the nth power bit. Therefore, the bit width of the memory for storing the data is also n corresponding to 2
Data can be stored efficiently by taking power. Considering that the instruction and the data are stored in the same memory, it is preferable that the minimum unit of instruction access is 2n bits.

However, if attribute information is added to an instruction field having a bit width of 2 to the nth power, the total width of the two will not be 2 to the nth power bit. In this embodiment, when the 32-bit instruction field and the 4-bit attribute information are combined,
It is 36 bits, not 2 to the nth power. For this reason, if one word is stored in a memory whose power is 2 n, the start of an instruction is not aligned with a boundary of 2 n bits, and updating of the value of the program counter becomes complicated.

Therefore, in the present invention, as shown in FIG. 4, the space for storing instructions is divided into units called blocks, and attribute information is added in block units.
To solve this problem.

In this figure, reference numeral 800 is an instruction space in which instructions executed by the processor are stored. Command space 800
Is divided into blocks 810. In this embodiment,
The size of the block 810 is 256 bytes, and the beginning of the block 810 is always aligned on a 256-byte boundary.

The structure of each block is shown in FIG. The block 810 is composed of an area 820 for storing attribute information and an area 830 for storing an instruction field. The attribute information 820 is in the block offsets 00h to 1Fh, and the instruction field 830 is in the block offsets 20.
It is stored in the portion of h to FFh. In addition, "h" at the end of the numerical value indicates that the numerical value is a hexadecimal number. The first 4 bytes of the attribute information 820 is an unused area, and the attribute corresponding to each instruction field is stored in the remaining 28 bytes. In the present embodiment, since the attribute field per instruction field is 4 bits, 56 pieces of attribute information are stored per block. The instruction field 830 is 228 bytes, and 56 32-bit instruction fields are stored.

Next, a hardware configuration for realizing this embodiment will be described with reference to FIGS. FIG. 6 is a diagram showing a configuration of a portion related to instruction supply in the processor 1 and a main memory 2. In this figure, parts not related to instruction supply are omitted.

In FIG. 6, 1 is a processor, 2 is a main memory, and 1
0 is an instruction cache tag storage unit, 20 is an instruction cache attribute storage unit, 30 is an instruction cache instruction field storage unit, 40 is a hit determination circuit, 50 is an attribute analysis circuit, 60 is a select circuit, and 70 is a cache control circuit. ,
Reference numeral 80 is a command supply control circuit, and 90a to 90d are processing devices.

First, each circuit in the figure will be described. Unless otherwise specified, signals are positive logic and H level is 1
The L level corresponds to 0. Also, in principle,
The circuit operates in synchronization with the rising edge of the clock. That is, the state transitions when the clock changes from the L level to the H level. To avoid complicating the figure, although not shown, the clock signals are connected to all circuits.

The main memory 2 stores instructions executed by the processor 1 and data operated when the instructions are executed. The instruction and the data may be stored in the same memory as shown in this figure, or may be stored in another memory. In this embodiment, a part of the main memory 2 is a read-only memory (hereinafter referred to as R
OM) and the rest is readable / writable memory (hereinafter abbreviated as RAM).

When the power is turned on, the program stored in the ROM is executed. The ROM is a non-volatile element, and the stored contents are retained even when the power is turned off. All programs executed by the processor 1 can be stored in the ROM, but if it is desired to have more processing freedom, the ROM of the main storage 2 can be changed from the external storage connected to the processor 1 to the ROM. It is also possible to store the program for transferring the program to the part and execute the program to transfer the program from the external storage device to the main memory 2.

In this embodiment, the width of the data connecting the processor 1 and the main memory 2 is 128 bits.

The instruction cache is composed of three types of memories including a tag storage unit 10, an attribute storage unit 20, and an instruction storage unit 30. The structure of the tag storage unit 10 is shown in FIG. 7, the structure of the attribute storage unit 20 is shown in FIG. 8, and the structure of the instruction storage unit 30 is shown in FIG. In this embodiment, a cache having a direct map structure is assumed, but the present invention does not depend on the cache structure. Therefore, other configurations such as 4-way set associative are possible.

The tag storage unit 10 is composed of a memory 11 of 19 bits × 64 words and a selector 12. 1
00 is write data to the memory 11, and is composed of an address tag 100a and a valid bit 100b. Hereinafter, the description with the subscript of the alphabet will be the generic one with the alphabet. Address tag 1
00a has an 18-bit width, and effective bit 100b has a 1-bit width. Reference numeral 106 is read data, which is composed of an address tag 106a and a valid bit 106b. The address tag 106a is 18 bits wide and the effective bit 106b is 1 bit wide. Reference numeral 102 denotes a signal used when writing to the tag storage unit 10, and the write address 1
02a and a read / write signal 102b. When the read / write signal 102b is set to H, the memory 1
Read access is made to 1, and write access is made to L. Reference numeral 111 is a read address. The write address 102a and the read address 111 are selected by the selector 12 and given to the memory 11. The control of the selector 12 is performed by the read / write signal 102b. The output of the selector 12 is the read / write signal 1
When 02b is H, it is the read address 111, and when 02b is L, it is the write address 102a.

The operation of the memory 11 is as follows.

If the read / write signal 102b is at the H level at the rising edge of the clock, the memory access is a read access, and the contents of the memory at the address designated by the read address 111 are output to the read data 106.

If the read / write signal 102b is at the L level at the rising edge of the clock, the memory access is a write access, and the content of the write data signal 100 is written to the memory at the address specified by the write address 102a. Be done.

The tag storage unit 10 stores an address tag of 18 bits per entry and a valid bit of the entry of 1 bit. The number of entries is 64. The content stored in the tag storage unit 10 is used for cache hit determination. That is, when the hit determination is performed, a read access is made to the tag storage unit 10. Further, when the content of the cache is updated, a write access for writing new tag information occurs in the tag storage unit 10.
In normal instruction access, since hit determination is required once for each instruction, the tag storage unit 10 is accessed once. However, when an instruction that spans two blocks is executed, two accesses are required. There is a need to do.

The attribute storage unit 20 includes a memory 21 of 16 bits × 896 words, a selector 22, and a data width conversion circuit 2.
It consists of three. Reference numeral 101 is write data to the attribute storage unit 20 and has a 128-bit width. Reference numeral 201 denotes write data to the memory 21, which is composed of attribute information corresponding to four consecutive instruction fields. 1
Since the attribute information per instruction field is 4 bits (field number 3 bits and final flag 1 bit), the width of the write data 201 is 4 bits × 4 = 16 bits. In the present embodiment, the field number is 3 bits in consideration of simplification and expandability of the description, but if the number of processing devices is limited to 4, the width of the write data 201 is reduced to 12 bits. It is also possible to do so. In this way, the write data 101 and the memory 21 for the attribute storage unit 20 are stored.
Since the width of the write data 201 to the write data is different, the data width conversion circuit 23 is used to absorb this. 10
Reference numeral 7 is read data, which has the same configuration as the write data 201 and has a 16-bit width. Reference numeral 103 is a signal used when writing to the attribute storage unit 20, and is composed of a write address 103a and a read / write signal 103b. When the read / write signal 103b is set to H, read access to the memory 21 is performed, and when set to L, write access is performed. Reference numeral 111 is a read address. Write address 103a and read address 111
Are selected by the selector 22 and given to the memory 21. The selector 22 controls the read / write signal 10
3b. The output of the selector 22 is the read address 11 when the read / write signal 103b is H.
When it is 1 or L, it becomes the write address 103a.

The operation of the memory 21 is similar to that of the memory 11. However, the inside of the memory 21 is configured so that four consecutive pieces of attribute information can be read from an arbitrary address position.

The instruction field storage unit 30 is composed of a memory 31 of 128 bits × 896 words and a selector 32. Reference numeral 101 is write data to the memory 31, and is composed of four consecutive instruction fields. The width of the write data 101 is 32 bits × 4 = 12
It is 8 bits. Reference numeral 108 is read data, which has the same configuration as the write data 101 and has a 128-bit width. Reference numeral 104 denotes a signal used when writing to the instruction field storage unit 30, and the write address 104
a and a read / write signal 104b. When the read / write signal 104b is set to H, read access to the memory 31 is performed, and when set to L, write access is performed. Reference numeral 111 is a read address. The write address 104a and the read address 111 are selected by the selector 32 and given to the memory 31. Selector 3
The control No. 2 is performed by the read / write signal 104b. The output of the selector 32 is the read / write signal 104b.
Is H, the read address 111, and L is the write address 104a.

The operation of the memory 31 is similar to that of the memory 11. However, the inside of the memory 31 is configured to be able to read four consecutive instruction fields from an arbitrary address position.

In each block, the block offset is 0.
In the area of 0h to 1Fh, since the attribute is stored, the command field does not exist. Therefore, by not mounting a memory in this portion of the instruction field storage unit 30, the chip area required by the instruction field storage unit 30 can be reduced. That is, in order to configure a cache memory capable of storing 64 pages, originally, 64 pages ×
256 bytes = 16 kilobytes of memory is required.
This corresponds to a memory of 128 bits × 1024 words.

However, in practice, the capacity of the instruction field storage unit 30 has an in-block offset of 00h to 1Fh.
64 pages x 22 because the attribute storage part of
8 bytes = 14 kilobytes is good. this is,
This corresponds to a memory having a structure of 128 bits × 896 words. Similarly, the capacity of the attribute storage unit 20 that has a one-to-one correspondence with the instruction field storage unit 30 can be reduced.

The hit determination circuit 40 has the contents of the address tag 106a and valid bit 106b read from the tag storage unit 10 of the instruction cache and the value 1 of the program counter.
11 is a circuit for checking whether an instruction to be executed next is stored in the instruction cache. FIG. 10 shows a configuration example of the hit determination circuit 40. Hit determination circuit 4
0 is composed of a comparator 41 and a NAND circuit 42. Comparator 40 has two 18-bit wide inputs, 106a
And 111a. 111a is the upper 18 bits of the value 111 of the program counter and is called the tag portion. If the two inputs also match 18 bits, the comparator 41
Output 200 becomes H level. If even one bit is different, the output 200 becomes L level. N
The AND circuit 42 is a 2-input NAND gate, and the cache miss signal 109, which is the output of the NAND circuit 42, becomes the L level only when the two inputs 200 and 106b are both at the H level. With other combinations of inputs, the cache miss signal 109 becomes H level.

Next, the principle of hit determination will be described with reference to FIG. As shown in FIG. 11, the value of the program counter is composed of three fields of a tag section 111a, an entry selection section 111b, and an offset 111c. The tag portion 111a is 18 bits wide and the entry selection portion 111b is 6 bits wide. The tag section 111a and the entry selection section 111b are used for hit determination. The entry selection unit 111b is used to select an entry to be accessed from the tag storage unit 10 of the instruction cache. That is, the entry selection unit 111
The value of b becomes the read address to the tag storage unit 10.
The instruction supply control circuit 80 reads the address tag value 106a and the valid bit value 106b of the selected entry in the tag storage unit 10. The read address tag value 106a, valid bit value 106b, and tag portion value 111a of the program counter are the hit determination circuit 4
Input to 0. If the address tag value 106a and the program counter tag portion 111a are not equal, or
When the value 106b of the valid bit is 0, the cache has missed, and the cache miss signal 109 output from the hit determination circuit 40 becomes H level. In other cases, the cache is hit and the cache miss signal 1
09 becomes L level.

The attribute analysis circuit 50 is a circuit which uses the attribute data read from the attribute storage section 20 of the instruction cache to generate a control signal for controlling other circuits.
The structure of the attribute analysis circuit 50 is shown in FIG. In this figure, 5
Reference numeral 1 is a select signal generation circuit, and 52 is an instruction length calculation circuit. Further, 107 is attribute information for four instruction fields read from the attribute storage unit 20, and the field number 10
7a and end flag 107b.

Reference numeral 114 is a control signal for the select circuit 60, 1
Reference numeral 17 is a signal representing the instruction length of the instruction currently being executed.

The select signal generating circuit 51 is a circuit for generating a control signal 114 for controlling the select circuit 60 from the field number value 107a and the end flag value 107b. The insertion of the deleted NOP is also performed here. This circuit can be configured as a combinational circuit.

The instruction length calculation circuit 52 uses the value 1 of the end flag.
This is a circuit for obtaining the instruction length 117 (the number of instruction fields forming the instruction being executed) from 07b. The calculated instruction length 117 is used to update the program counter. The instruction length calculation circuit 52 is composed of a combination circuit, and its truth table is as shown in FIG. In this table, the first final flag 107b-0 is an end flag corresponding to the instruction field at the address pointed to by the program counter. Second final flag 107b
-1 is an end flag corresponding to the instruction field next to the instruction field at the address pointed to by the program counter. The same applies to the third and fourth. X is
It indicates that either 0 or 1 is acceptable. A combination in which the instruction length 117 is Err is an error. This combination does not occur in normal programs.

The select circuit 60 is a circuit for distributing the four instruction fields read from the instruction field storage unit 30 of the instruction cache to the corresponding processing device by using the control signal 114 generated by the select signal generation circuit 51. . The configuration of the select circuit is shown in FIG. 61 in this figure
a to d are selectors. The selectors 61a to 61d are composed of combinational circuits. In this figure, NOP is NOP
It indicates that the instruction code corresponding to is output.

The command supply control circuit 80 is a circuit for controlling the command supply. The configuration of the instruction control circuit 80 will be described with reference to FIG. In this figure, 81 is a program counter, 82 and 83 are selectors, 84 is an adder, 85 is an attribute skip circuit, and 86 is a process execution control sequencer.

The process execution control sequencer 86 is a circuit for determining whether to execute or stop the process, and has two states of execution and stop. The initial state of the process execution control sequencer 86 is the stopped state. At this time, the processing device 90 does not execute the process. The processor 90 cannot access the instruction cache during the filling operation of the instruction cache or the invalidation of the instruction cache. In this way, when the execution of the process cannot be continued, the process execution control sequencer 86
Shifts to the stopped state. On the contrary, when the instruction cache fill operation is completed or the instruction cache invalidation processing is completed, the processing execution control sequencer 86 shifts to the execution state. The state of the execution control sequencer 86 is reflected in the process execution signal 110. That is, the processing execution signal 110 is at the L level in the stopped state, and the processing execution signal 110 is at the H level in the execution state.
It becomes a level.

Next, a method of updating the program counter 81 will be described with reference to FIGS. 16
9 is a flowchart showing a method for updating the program counter 81. The program counter 81 is also updated in synchronization with the clock. When the process execution control sequencer 86 is in the stopped state, the program counter 81 is not updated (700). This processing is performed by the selector 83. The output of the selector 83 is switched by the processing execution signal. If the processing execution signal is at H level, instruction length 1
17 is output, and if it is at L level, 0 is output. That is, in the stopped state, the value added to the program counter 81 in the adder 84 becomes 0, and the program counter 81 holds the previous value. If the process execution control sequencer 86 is in the execution state, it is checked whether the instruction currently being executed is a branch instruction (701).
This is done by examining the content of the branch execution signal 113a output from the processing unit 90. If the value of the branch execution signal 113a is H, the instruction currently being executed is a branch instruction. If the instruction being executed is a branch instruction, the branch destination address 11 is sent to the program counter 81.
3b is substituted (702). This process is performed by the selector 82
Done in. When the branch execution signal 113a is H, the output of the selector 82 is the branch destination address 113b output from the processing unit 90, and when the branch execution signal is L, the output 220 is the output 221 of the attribute skip circuit 85. If it is not a branch instruction, the instruction length of the instruction currently being executed is added to the value of the program counter 81 (703).
This is done in adder 84. As a result of the addition, when the address pointed to by the program counter 81 does not point in the instruction field 830 but in the attribute information 820, the program counter 81 further sets 20h (1
32) is added in the case of 0-base number. This is executed by the instruction skip circuit 85. The instruction skip circuit 85 is an adder that adds 0 or 20h. Which is added is determined by the output 222 of the adder.

By updating the program counter by the above method, the attribute area of each block can be skipped and only the instruction field can be executed.

The configuration of the instruction cache control circuit 70 is shown in FIG.
7 shows. In this figure, 71 is a fill control circuit, 72 is an invalidation circuit that invalidates all entries in the instruction cache,
73 is a selector. Further, 109 is a cache miss signal output from the hit determination circuit 40, and 116 is an initialization signal. Reference numeral 112 is a signal indicating the operating state of the cache control circuit 70, and a cache fill in-progress signal 112a indicating that cache fill is being executed,
It is composed of an invalidation signal 112b indicating that the invalidation of the cache is being executed. The instruction cache control signals 102 to 104 are signals for performing write access to the instruction cache, such as a write address and a read / write signal, and the control signal 24 from the fill control circuit 71.
1 and the result of switching the control signal 241 from the invalidation circuit 72 by the selector 73 are output. The invalidating signal 112b is used for switching the selector. Reference numeral 105 is an address and control signal used when reading an instruction from the main memory.

The fill control circuit 71 is a circuit for reading an instruction for one block and the attribute corresponding to the instruction from the main memory 2 when the instruction to be executed next does not exist in the instruction cache. The fill control circuit 71 starts the fill operation when the cache miss signal 109 becomes H level. In the fill operation, one block of instruction and attribute data is read from the main memory 2, and the attribute storage unit 2 of the instruction cache is read.
0 and the operation of storing in the instruction field storage unit 30. At this time, the value of the tag storage unit 10 of the instruction cache is also updated. The tag storage unit 10 is updated by the entry selected by the line selection unit 111b in the program counter.
This is done by writing the tag section 111a in the program counter to the address tag section 106a and writing 1 to the valid bit 106b.

The invalidation circuit 72 is a circuit for invalidating all entries in the instruction cache when the power is turned on. The invalidation circuit 72 includes a counter for designating an entry to be invalidated and a control signal generation circuit. The counter is 6 bits wide. Initialization signal 116
Is set to H level, the counter value is 0 to 6
Change up to 3. By writing 0 to the valid bit 106b of the entry selected by this counter value,
Invalidates all cache entries. During the invalidation process, the invalidation signal 112b is at the H level.

The processing device 90 is a circuit that interprets the contents of a given command field and performs processing according to the contents. In this embodiment, there are four processing devices inside the processor 1. However, the number of processing devices is not limited to this. The configuration of the processing device 90 will be described by taking the processing device 90a as an example. The other processing devices 90b to 90d have the same configuration. The configuration of the processing device 90a is shown in FIG. The processing device 90a includes an instruction register 91a and a processing execution unit 92a. Instruction register 91a
Is a register for storing an instruction field to be executed by the process execution unit 92a. The width of the instruction register 90a is 32 bits, which is equal to the width of the instruction field. The processing device 90a operates in synchronization with the clock. Therefore, when the clock changes from the L level to the H level, the value of the processing execution signal 110 causes the processing execution unit 92a to change.
Is determined. At this time, the process execution signal 110
Is high, the process execution unit 92a executes the process specified by the instruction field stored in the instruction register 91a. If it is at the L level, the process execution unit 92a does nothing. The operation content of the process execution unit 92a departs from the essence of the present invention and will not be described here. The four process execution units 92a to 92d do not have to have the same configuration. For example, one processing execution unit can be used for integer arithmetic processing, and another processing execution unit can be used for floating point arithmetic processing. Further, each processing device can process a branch instruction. When the branch processing occurs, the branch execution signal 113a is set to H as the branch information 113.
At the same time as setting the level, the branch destination address is output to the branch destination address signal 113b.

Next, the operation of the entire processor 1 will be described.

Before the processor 1 starts its operation, initialization processing is necessary. The initialization is started by setting the initialization signal 116 to the H level. The initialization signal 116 is set to the H level by the initialization signal generation circuit 95 when the power is turned on and the reset switch 97 is pressed. After a certain period of time, the initialization signal 116 automatically returns to the L level.

A configuration example of the initialization signal generation circuit 95 is shown in FIG.
Shown in. In this figure, 96 is a resistor, 98 is a capacitor, and 9
7 is a reset switch, 99 is an inverter, and a signal 116 is an initialization signal. Immediately after the power is turned on and immediately after the reset switch 97 is pressed, no electric charge is stored in the capacitor 98, so that the potential difference across the capacitor 98 is 0 volt. Therefore, the input value of the inverter 99 becomes L level and the initialization signal 116 is set to H level. After that, when the reset switch 97 is released, the capacitor 98 is charged with electric charge through the resistor 96, and the potential difference between both ends increases. As a result, the input voltage of the inverter 99 rises with time. When the input voltage of the inverter 99 becomes higher than the threshold value, the output of the inverter 99 is inverted and the initialization signal 116 becomes L level. Although not shown, the initialization signal 116 is connected to all circuits in principle, in order to avoid complication of the drawing.

When the initialization signal 116 goes to H level, the flip-flops inside the processor 1 are initialized to predetermined values. After that, the initialization process is started. The instruction control system invalidates the instruction cache as an initialization process. During the invalidation processing, the processing device 90
Is in a stopped state. When the invalidation process ends, the invalidation signal becomes L level, the processing device 90 starts operating, and the execution of the instruction starts from a predetermined address.

At the time of instruction execution, the instruction supply control circuit 80 addresses the instruction caches 10, 20, 30 with the address 1
11 is output, and the tag information 106 is read from the tag storage unit 10, the attribute information 107 is read from the attribute storage unit 20, and the command field 108 is read from the command field storage unit. The read tag information 106 is input to the hit determination circuit 40, and the hit determination circuit 40 determines the hit of the instruction cache. If the instruction cache is hit, the instruction field 108 is distributed by the select circuit 60 to the processing unit 90 to be processed. At this time, the processing execution signal 110 becomes H level, and the processing unit 90 performs processing according to the contents of the given instruction field.
At this time, the value of the program counter 81 is also updated, and the next instruction is executed in synchronization with the rising edge of the next clock.

If the instruction cache misses,
The cache control circuit transfers one block of instruction field and attribute information from the main memory 2 to the instruction cache. During the transfer, the cache fill signal 112a is at the H level, so the execution of the instruction is interrupted. When the transfer is complete,
The instruction cache is in a hit state, and thereafter, the processing is performed in the same manner as when the instruction cache is hit. When the execution of the instruction is suspended, the content of the program counter 81 is not updated and the previous value is held.

[0068]

In the processor using the present invention, attribute information is added to the instruction field, and even if the total length of both is not an integral multiple of 1 byte, the start address of each instruction field is aligned on a byte boundary. Therefore, the update of the program counter can be simplified.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of processing executed by a processor.

FIG. 2 is an explanatory diagram showing an example of an instruction sequence before compression.

FIG. 3 is an explanatory diagram showing an example of an instruction sequence after compression.

FIG. 4 is an explanatory diagram showing the structure of an instruction space.

FIG. 5 is an explanatory diagram showing a configuration example of a block.

FIG. 6 is a block diagram of a processor and a main memory according to the present invention.

FIG. 7 is an explanatory diagram of a tag storage unit of an instruction cache.

FIG. 8 is a block diagram of an attribute storage unit of an instruction cache.

FIG. 9 is a block diagram of an instruction field storage unit of an instruction cache.

FIG. 10 is a block diagram of a hit determination circuit.

FIG. 11 is a block diagram showing an example of a hit determination method.

FIG. 12 is a block diagram showing a configuration example of an attribute analysis circuit.

FIG. 13 is an explanatory diagram showing an operation example of an instruction length calculation circuit.

FIG. 14 is an explanatory diagram showing a configuration example of a select circuit.

FIG. 15 is a block diagram showing a configuration example of an instruction supply control circuit.

FIG. 16 is a flowchart showing an example of a program counter updating method.

FIG. 17 is a block diagram of a cache control circuit.

FIG. 18 is a block diagram showing a configuration example of a processing device.

FIG. 19 is an explanatory diagram showing a configuration example of an initialization signal generation circuit.

[Explanation of symbols]

810 ... Block, 820 ... Area for storing attribute information,
830 ... An area for storing an instruction field.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyokazu Nishioka 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Stock Company, Hitachi, Ltd. System Development Research Institute (72) Toru Nojiri, 1099, Ozen-ji, Aso-ku, Kawasaki, Kanagawa Company Hitachi, Ltd. System Development Laboratory (72) Inventor Yoshifumi Fujikawa 1099, Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Company Hitachi, Ltd. System Development Laboratory (72) Inventor, Koji Hosoki, 1099, Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Company Hitachi Ltd. System Development Laboratory (56) Reference JP-A-7-182169 (JP, A) JP-A-8-161169 (JP, A) JP-A-7-105003 (JP, A) JP-A-9- 16471 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/30-9/42 G06F 12/08

Claims (6)

(57) [Claims] 1. A process is executed according to the contents of a given instruction.
The instruction processing means to execute and the address of the instruction to be executed
Pointer storing means for storing a pointer for storing, and an instruction
External storedStorage deviceCommand to processing means
An instruction supply means for supplying,Storage deviceSourced from
Command storing means for temporarily storing the stored command.
Including,Store in contiguous or adjacent address space of the storage device
A set of instructions composed of a plurality of instructions,
Each instruction of the plurality of instructions corresponds to the set of instructions.
Including information for instructing the instruction processing means to execute the command
The set of attribute information and
Take it into the payment method, A mechanism for limiting the updatable range when updating the pointer
By providingOf the set of commands and the set of attribute information
The aboveorderSet ofIt is possible to perform
The processor to do. 2. An instruction processing means for executing a process according to the contents of a given instruction, a pointer storage means for storing a pointer for pointing the address of the instruction to be executed, and an external storage device in which the instruction is stored. From an instruction supply unit for supplying an instruction from the storage device to the processing unit, and an instruction storage unit for temporarily storing the instruction supplied from the storage device , and stored in a continuous or adjacent address space of the storage device.
A set of instructions composed of a plurality of instructions,
Each instruction of the plurality of instructions corresponds to the set of instructions.
Including information for instructing the instruction processing means to execute the command
The set of attribute information and
Each command of the plurality of commands is loaded into the storage means and the attribute information is used.
By giving the instruction to the instruction processing means to be executed ,
A processor characterized in that processing can be executed in parallel. 3. The processor according to claim 1, wherein both the instruction set and the attribute information set have a fixed length. 4. A set of instructions, the processor according to claim 1 or 2 number of instructions is always constant included. 5. A pointer for designating an address of an instruction in the storage device and a pointer for designating an address in the instruction storage means are the same, and the instruction stored in either of them is accessed. 3. The processor according to claim 1, wherein a mechanism for address translation is unnecessary. 6. An instruction and attribute information even if the instruction storing means for storing the instruction and the instruction storing means for storing the attribute information are provided independently and the instruction storing means having only a single read port is used. 3. The processor according to claim 1, wherein the processor and the processor are simultaneously accessed.