JPH11249961A - Data transfer device and data transfer control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer device which increases the data transfer speed in a DMA controller by simplifying not only the constitution but also an access from the DMA controller to a bus, and a data transfer control method for the above data transfer device. SOLUTION: A data transfer device 100 comprises a CPU 110, a main memory 120, an I/O interface 130, a DMA controller 140, a bus line 150 to which these components are connected and through which a control signal, a data signal, an address signal, etc., are inputted and outputted, and a cache memory 160 which is set between the DMA controller 140 and the bus line 150 and interferes in input/output data processing of the DMA controller 140.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device, and more particularly, to a data transfer device for efficiently controlling a DMA controller.

[0002]

2. Description of the Related Art Conventionally, this type of data transfer apparatus is composed of a main storage device and a CPU for realizing high-speed operation, particularly for realizing high-speed operation / processing and data transfer. Also, the main storage device and the CPU
As described in the PCI bus specification, a bus line connecting the buses realizes a high-speed burst transfer function on the bus line and adds a burst transfer function to the main storage device, thereby enabling data transfer in the data transfer device. The transfer speed has been increased.

In the data transfer device disclosed in Japanese Patent Application Laid-Open No. 4-365157, a cache memory and a data buffer are provided in a DMA controller, and the cache memory or the data buffer is provided in response to a data transfer request from the DMA controller. The speed of data transfer has been increased by extracting data from the data buffer.

[0004]

In any of the above-mentioned conventional data transfer apparatuses, since no consideration is given to the burst transfer between the DMA controller and each component device, single-byte data is transferred from the DMA controller to the bus. When the access occurs, there is a problem that the bus use efficiency is increased and the operation of the entire data transfer device is delayed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a simple configuration and a simplified DMA access by a DMA controller.
It is an object of the present invention to provide a data transfer device capable of speeding up data transfer in a controller and a data transfer control method of the data transfer device.

[0006]

According to a first aspect of the present invention, there is provided a main memory comprising a plurality of RAM chips for temporarily storing processing results and the like; A CPU for outputting a read / write execution request to a memory controller; a DMA controller for executing data transfer with the main memory without intervention of the CPU; a DMA controller for executing the transfer of data with the main memory; And the above-mentioned DM
The configuration includes an A controller and a cache memory installed between the bus lines.

In the invention according to claim 1, the DMA controller does not receive the intervention of the CPU when there is a request from the CPU to read / write data from / to the main memory. Execute data transfer with. At this time, the same data transfer is performed with the same DMA.
This is executed via a cache memory provided between the controller and the bus line.

[0008] The invention according to claim 2 is based on claim 1.
In the data transfer device described in the above, when the DMA controller reads data from the main memory, when the data to be read is present in the cache memory, the cache memory stores the data in the cache memory. The configuration includes a cache memory control unit that outputs data to the DMA controller.

[0009] In the invention according to claim 2 configured as described above, the cache memory control means includes the D memory.
When the MA controller reads data from the main memory, if the read data exists in the cache memory, the MA controller outputs the data in the cache memory to the DMA controller.

Further, according to a third aspect of the present invention, in the data transfer device according to any one of the first and second aspects, the cache memory control means includes the DMA controller.
When the controller outputs data to the bus line, the controller writes the data to the cache memory.

[0011] In the invention according to claim 3 configured as described above, the cache memory control means includes the D memory.
When the MA controller outputs data to the bus line, the data is written to the cache memory.

Further, according to a fourth aspect of the present invention, in the data transfer device according to any one of the first to third aspects, the cache memory control means is configured to execute the cache control when the operation of the DMA controller is completed. All data in the memory is output to the bus line.

[0013] In the invention according to claim 4 configured as described above, the cache memory control means includes the D memory.
When the operation of the MA controller is completed, all data in the cache memory is output to the bus line.

According to a fifth aspect of the present invention, in the data transfer apparatus according to any one of the first to fourth aspects, the cache memory control means receives a data output request from the DMA controller. When the data exists in the storage area of the cache memory, the data is not output to the bus line.

[0015] In the invention according to claim 5 configured as described above, the cache memory control means, having received the data output request from the DMA controller, determines whether the data exists in the storage area of the cache memory. The same data is not output to the bus line.

Further, according to a sixth aspect of the present invention, in the data transfer device according to any one of the first to fifth aspects, the cache memory control means includes setting data relating to data transfer set in the DMA controller. Address editing means for rewriting the starting address number of the storage area with the address number of the storage area of the cache memory.

[0017] In the invention according to claim 6, the address editing means stores a start address number, which is setting data relating to data transfer set in the DMA controller, in an address of a storage area of the cache memory. Can be rewritten into numbers.

Further, according to the present invention, a cache memory is provided between a DMA controller and a bus line, and data is output from the DMA controller to another memory connected to the bus line. Stores the same data in the cache memory,
When there is data input to the MA controller, the data in the cache memory is searched, and when the same data as the data input exists in the cache memory, the same data is output to the DMA controller. . That is, the present invention is not necessarily limited to a physical device, and is also effective as a method.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a data transfer device according to a first embodiment of the present invention. In FIG. 1, a data transfer device 100 has a CPU 110 that reads program data stored in a memory, executes calculations, inputs and outputs data, and controls other components, and a storage circuit that stores data therein. The main memory 120 stores input / output of internal data designated by an address from an external circuit and input data in the same storage circuit, and inputs / outputs data to / from an external device of the data transfer apparatus 100. I to notify that there is data from the external device
An I / O interface 130; a DMA controller 140 that reads data from the main memory 120 and the I / O interface 130 according to instruction data from the CPU 110 and writes data to the main memory 120 and the I / O interface 130; A bus line 150 to which elements are connected and for mutually inputting and outputting control signals, data signals, address signals, etc .;
A cache memory 160 is provided between the MA controller 140 and the bus line 150 and intervenes in input / output data processing of the DMA controller 140.

FIG. 2 is a block diagram showing the cache memory 160. In the figure, the cache memory 160 is a storage circuit 16 having a storage block 161 composed of a plurality of unit data handled by the CPU 110 and the main memory 120 as a storage unit.
An address comparison circuit 163 connected to the storage circuit 162 and the DMA controller 140 and comparing the address of the data written in the storage block 161 with the address output from the DMA controller 140; The data transfer control circuit 164 is connected to the circuit 163 and controls data transfer in the cache memory 160.

Next, the operation of data transfer between the DMA controller 140 and the cache memory 160 will be described with reference to a flowchart in FIG. First,
The CPU 110 makes various predetermined settings for the DMA controller 140. The same setting is performed in three registers of an address ADR1 which is a data transfer source address, an address ADR2 which is a data transfer destination address, and a counter CO which is a data transfer byte number (step S200). When this setting is completed, the CPU 1
10 outputs a transfer start command to the DMA controller 140 (step S205). Here, it goes without saying that the CPU 110 may be another bus master from the viewpoint that the CPU 110 also has an access right to the bus line 150.

The DMA controller 140
Receives the transfer start command from the CPU 110, and initializes the contents of the cache memory 160 (step S206). The initialization means that all the states of the storage blocks 161 in the cache memory 160 are set to the INVALID state. In addition,
The INVALID state means that data can be written to the storage block 161 by invalidating the data stored in the storage block 161.

Next, it is determined whether the data transfer process is a read access process (step S207). If the data transfer process is a read access, a read access data transfer process is executed (step S300). If the data transfer process is a write access, a write access data transfer process is executed (step S400).

When these data transfer processes are completed, the state of the storage block 161 of the cache memory 160 is confirmed, and the storage block 161 in the DIRTY state is checked.
Performs a burst write on the bus line 150 (step S210). Here, the DIRTY state is
From the DMA controller 140 to the storage block 1
61 indicates that data has been written, and indicates that data has not been written back. As described above, the data transfer processing in the DMA controller 140 ends (step S211).

Next, FIG. 4 is a flowchart showing the contents of the data transfer control executed by the cache memory 160 for the read access data transfer processing in step S300 in FIG. The address comparison circuit 163 acquires the data related to the read access output from the DMA controller 140 and confirms the content (step S305). It is determined whether the address to be accessed in this data is for the main memory 120 (step S31).
0). If this address is for the main memory 120, the process of the loop 360 is executed.

In this process, first, the state of the storage block 161 is obtained, and the address is compared with the address on the storage block 161. Here, an address that matches the above address is stored in the storage block 16.
1 and the same storage block 161
If it is in the VALID state or the CLEAN state (step S315), a read access including the address is output on the bus line 150 (step S32).
0). Here, the CLEAN state refers to a state in which the access data from the DMA controller 140 has been written back.

The above-mentioned storage block 161
Of the address and the above-mentioned address and the same storage block 161
In the comparison of the above addresses, if an address that matches the above address does not exist in the storage block 161, and the storage block 161 is in the DIRTY state (step S325), the write access including the address is performed by the bus line 150. (Step S3)
30) After the end of the write access, a read access including the same address is output onto the bus line 150 (step S335). When step S320 and step S335 are completed, the data input from the bus line 150 by the read access in these steps is stored in the storage block 161.
The state of the storage block 161 is set to the CLEAN state (step S340).

Further, the above-mentioned storage block 16
1 and the address and the same storage block 16
In the comparison of the addresses on the first and second addresses, an address that matches the above address exists in the storage block 161, and the storage block 161 is in the DIRTY state or the CL state.
When the EAN state is set (step S345) and when the step S340 is completed, the storage block 1
The data at the address corresponding to the address related to the read access from the DMA controller 140 existing on the memory controller 61 is output to the DMA controller 140 (step S346).

With the above processing, the unit data transfer of the read access processed by the DMA controller 140 is completed. Since this process is performed the number of bytes set in the counter CO, which is the number of data transfer bytes, the counter CO is decremented (step S35).
At the same time as 0), the address ADR1 and the address ADR2 are incremented to specify the next set address (step S355). In addition, the loop 360
Executes a loop process until the counter CO becomes smaller than 0.

Next, FIG. 5 is a flowchart showing the contents of the data transfer control executed by the cache memory 160 for the write access data transfer processing in step S400 in FIG. The address comparison circuit 163 acquires the data relating to the write access output from the DMA controller 140 and confirms the contents (step S405). In this data, it is determined whether the address to be accessed is for the main memory 120 (step S41).
0). If this address is for the main memory 120, the process of the loop 460 is executed.

In this process, first, the state of the storage block 161 is obtained, and the address is compared with the address on the storage block 161. Here, an address that matches the above address is stored in the storage block 16.
1 and the same storage block 161
If it is in the VALID state or the CLEAN state (step S415), a read access including the address is output on the bus line 150 (step S42).
0).

The above-mentioned storage block 161
Of the address and the above-mentioned address and the same storage block 161
In the comparison of the above addresses, if an address that matches the above address does not exist in the storage block 161 and the storage block 161 is in the DIRTY state (step S425), the write access including the address is performed by the bus line 150. Output above (step S4
30) After the end of the write access, a read access including the same address is output onto the bus line 150 (step S435).

When the steps S420 and S435 are completed, the data input from the bus line 150 by the read access in these steps is stored in the storage block 161, and the state of the storage block 161 is set to the CLEAN state. (Step S440).

Further, the above-mentioned storage block 16
1 and the address and the same storage block 16
In the comparison of the addresses on the first and second addresses, an address that matches the above address exists in the storage block 161, and the storage block 161 is in the DIRTY state or the CL state.
When the EAN state is set (step S445) and when the step S440 ends, the storage block 1
The data output by the DMA controller 140 is written to an address corresponding to the address related to the write access from the DMA controller 140 existing on the memory 61 (step S446).

With the above processing, the unit data transfer of the write access processed by the DMA controller 140 is completed. Since this process is executed the number of times set in the counter CO which is the number of data transfer bytes, the counter CO is decremented (step S45).
Along with 0), the address ADR1 and the address ADR2 are incremented to specify the next set address (step S455). Also, the loop 460
Executes a loop process until the counter CO becomes smaller than 0.

As described above, the DMA controller 14
When the cache memory 160 is provided on the bus line 150 connecting the main memory 120 to the main memory 120, all accesses performed in the data transfer access output from the DMA controller 140 are performed via the cache memory. All the accesses are realized by data transfer by burst access. Therefore, the speed of the data transfer process of the DMA controller 140 can be increased.

In this embodiment, since the read access to the address ADR1 always exists on the storage block 161 of the cache memory 160, the read access is not output to the bus line 150.
Further, the speed of the data transfer process of the DMA controller 140 can be increased.

[0038]

As described above, the present invention simplifies the access to the bus from the DMA controller and burst-transfers the data stored in the cache memory onto the bus. Can be provided.

According to the second aspect of the present invention, D
When the data accessed by the MA controller exists in the cache memory, the data in the cache memory is output to the DMA controller, so that the data does not flow on the bus, so that the data transfer in the DMA controller is further speeded up. It becomes possible.

Further, according to the invention of claim 3,
By writing the data used by the DMA controller to the cache memory, the hit rate can be improved when the same data is reused.

Further, according to the invention of claim 4,
When the access to the bus line in the DMA controller is completed, the data in the cache memory is output, so that the consistency between the internal data and the external data in the cache memory can be maintained.

Further, according to the invention of claim 5,
If the same data as the data that has already been written to the cache memory by the DMA controller is output from the DMA controller again, it is determined that there is consistency with the outside, and this data is not output on the bus line. As a result, since data does not flow on the bus, it is possible to further speed up data transfer in the DMA controller.

Further, according to the invention of claim 6,
Because you can directly specify the storage area of the cache memory,
Since it is not necessary to determine the presence or absence of the address of the data requested to be transferred from the DMA controller in the same cache memory, it is possible to further speed up the data transfer in the DMA controller.

Further, according to the seventh aspect of the present invention,
By simplifying the configuration and simplifying the access from the DMA controller to the bus, it is possible to provide a control method of a data transfer device that can speed up data transfer in the DMA controller.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data transfer device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a cache memory included in the data transfer device.

FIG. 3 is a flowchart showing processing contents of data transfer control executed by the cache memory.

FIG. 4 is a flowchart showing processing contents of read access data transfer as the data transfer control.

FIG. 5 is a flowchart showing processing contents of write access data transfer as the data transfer control.

[Explanation of symbols]

 Reference Signs List 100 data transfer device 120 CPU 130 I / O interface 140 DMA controller 150 bus line 160 cache memory

Claims (7)

[Claims] 1. A main memory constituted by a plurality of RAM chips and temporarily storing processing results and the like; a CPU for outputting a read / write execution request to a memory controller of the main memory; A DMA controller for executing data transfer with the main memory without intervention, a bus line connecting the DMA controller, the main memory, and the CPU, and a DMA line between the DMA controller and the bus line; A data transfer device comprising a cache memory. 2. The data transfer device according to claim 1, wherein when the DMA controller reads data from the main memory, the data to be read is the same as the cache memory. When the data exists in the cache memory,
A data transfer device comprising a cache memory control means for outputting to a controller. 3. The data transfer device according to claim 1, wherein said cache memory control means is configured to output said data when said DMA controller outputs data to said bus line. A data transfer device for writing the data to the cache memory. 4. The data transfer device according to claim 1, wherein the cache memory control means deletes all data in the cache memory when the operation of the DMA controller ends. A data transfer device for outputting to the bus line. 5. The data transfer device according to claim 1, wherein said cache memory control means receives a data output request from said DMA controller and stores said data in said cache memory. A data transfer device that does not output the same data to the bus line when the data transfer device exists in the storage area. 6. The data transfer device according to claim 1, wherein said cache memory control means includes: a first address number which is setting data relating to data transfer set in said DMA controller; A data transfer device comprising an address editing means for rewriting an address number of a storage area of the cache memory. 7. A cache memory is provided between a DMA controller and a bus line. When data is output from the DMA controller to another memory connected to the bus line, the data is transferred to the cache memory. The data is stored in the memory, and when there is a data input to the DMA controller, the data in the cache memory is searched. When the same data as the data input exists in the same cache memory, the data is transferred to the DMA controller. A data transfer control method for a data transfer device, characterized by outputting to a controller.