JPH11219294A - Method for controlling program and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize stall control by means of referring to a NOP field in an instruction code by executing an instruction after the insertion of N NOPs which are set in the NOP field at the time of decoding an instruction code. SOLUTION: A stall control part 3 inputs a first instruction code 21 and an NOP code 23. The first instruction code 21 is inputted and it is judged whether the code is the instruction code provided with the NOP field or not. When the first instruction code 21 is the one provided with the NOP field, control for detecting the number of NOPs to be decoded and inserted, outputting pipeline temporary stop signals 24 for temporarily stopping a pipeline processing stage to an address generating part 2 for the portion of a designated number and outputting the NOP code 23 as a second instruction code 22. Thus, when the number of NOPs which are set in the NOP field is N at the time of decoding the instruction code, the instruction pertinent to the instruction code is executed after the insertion of N NOPs and a stall is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stall (gaining time) in an information processing apparatus for processing instructions in a pipeline.
The present invention relates to a program control method and apparatus.

[0002]

2. Description of the Related Art An information processing apparatus for pipeline processing instructions, for example, a digital signal processor (hereinafter referred to as DS).
P) is provided with a dedicated pointer register (hereinafter abbreviated as PR) for addressing a data memory, separately from a general-purpose register (hereinafter abbreviated as GR). In such an information processing apparatus, there is a case where resource conflict such as register interference occurs between instructions.

For example, in the case of a four-stage pipeline, there are four processing stages of instruction fetch (IF), instruction decode 1 (D1), instruction decode 2 (D2), and execution stage (EX). The transfer is performed in the EX stage. The PR addresses the data memory in the D1 stage. Therefore, if a command accompanied by access to the data memory (for example, a transfer command from the data memory to GR: MOV GR, M (PR)) is executed immediately after the transfer command from the GR to the PR (MOV PR, GR), There is a problem that addressing is performed with the PR value before the change and register interference occurs.

In order to avoid resource contention such as register interference, a method is adopted in which a no-process instruction (hereinafter referred to as NOP) is inserted between instructions causing resource contention to stall the instruction. JP-A-1-119829 is known as a technique for solving this resource conflict problem. JP 1
The technique disclosed in 119829 uses N
A field for designating the number of OPs is provided.
The register interference is avoided by detecting the number and inserting a predetermined number of NOPs following the output of the execution internal code of the instruction code to realize stall control.

According to this technique, an NOP field is provided in an instruction code, and the number of NOPs to be inserted after execution of the instruction is set in the NOP field for an instruction causing resource conflict such as register interference. This NOP
According to the setting of the field, a stall is executed between a preceding instruction and a subsequent instruction that cause resource conflict such as register interference, thereby preventing resource conflict. In the case of a four-stage pipeline, the instruction 1 “MOV PR, GR” and the instruction 2 “MOV PR, GR”
By inserting two NOP instructions between "GR, M (PR)" and "GR, M (PR)", addressing can be performed by the instruction 2 using the PR value changed by the execution of the instruction 1.

[0006]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 1-119 has been disclosed.
829 does not disclose a specific hardware configuration for implementing stall control by inserting a predetermined number of NOPs with reference to the NOP field of the instruction code.

According to the technique disclosed in Japanese Patent Laid-Open Publication No. 1-119829, when there is a preceding instruction and a following instruction that cause resource conflict such as register interference, NOP is applied to the preceding instruction.
A field can be provided, and the number of NOPs can be set in the NOP field.
An OP can be inserted. However, if there are many types of preceding instructions that cause resource contention in the processing program, the types of instruction codes provided with the NOP field will increase. Increasing the number of instruction code types having the NOP field undesirably increases the amount of instruction code data. Further, according to the conventional method of providing the NOP field in the code of the preceding instruction, it is impossible to use this method if there is not enough room to provide the NOP field in the instruction code.

Accordingly, a first object of the present invention is to provide a program control device that realizes stall control by inserting a predetermined number of NOPs with reference to a NOP field in an instruction code.

A second object of the present invention is to provide a method and apparatus for controlling a program which suppresses an increase in the amount of instruction code data accompanying insertion of a NOP for stall control at the time of resource contention.

A third object of the present invention is to provide a program control method and apparatus in which, when the field margin for providing the NOP field in the instruction code is small, the field margin is increased as compared with the conventional method.

[0011]

According to a first program control method in an information processing apparatus for performing a pipeline process of an instruction according to the present invention, a NO indicating the number of NOPs which are non-processing instructions
If a P field is provided in the instruction code and the number of NOPs set in the NOP field is N when the instruction code is decoded, the instruction corresponding to the instruction code is executed after inserting N NOPs In this case, the stall is executed.

According to the above configuration, according to the present invention, when a processing program includes a preceding instruction causing a resource conflict and a subsequent instruction, a NOP is inserted after the preceding instruction is executed, and finally the subsequent instruction is executed. become.

It is preferable that the setting of the number of NOPs in the NOP field is automatically set by a assembler, a compiler, or the like to a specific instruction code that may cause a resource conflict. The same applies to the second and third program control methods described later.

Next, in the above program control method,
If the processing program includes a preceding instruction and a succeeding instruction that cause resource conflict, and the type of the following instruction is smaller than the type of the preceding instruction, it is preferable to provide a NOP field in the subsequent instruction code.

According to the above configuration, when the type of the subsequent instruction is smaller than the type of the preceding instruction, the NOP field is provided in the subsequent instruction code. The number of instructions for providing the NOP field can be reduced as compared with the case where the NOP field is provided for the.

According to a second program control method in an information processing apparatus for performing pipeline processing of an instruction according to the present invention, when a processing program includes a preceding instruction and a succeeding instruction which cause resource conflict, the processing instruction includes a preceding instruction code and the succeeding instruction. NOP fields are provided on both sides of the code, and after executing the instruction of the preceding operation code,
The stall is executed by inserting the number of NOPs set in the P field and inserting the number of NOPs set in the NOP field of the subsequent instruction code before executing the instruction of the subsequent instruction code. And

According to the above configuration, since the NOP field is provided in both the preceding instruction code and the subsequent instruction code, when the field margin of either the preceding instruction or the subsequent instruction or both instruction codes is small, The field margin can be increased.

Next, according to the present invention, there is provided a program control apparatus for pipeline-processing an instruction including an instruction code having a NOP field, comprising: an instruction code storage unit for storing a first instruction code; An address generation unit for generating an address for outputting the first instruction code; and
Output control of a stop signal for temporarily stopping a pipeline processing stage to the address generation unit, based on a determination result as to whether the instruction code is an instruction code having a NOP field, and the first instruction code or NOP code And a stall control unit for performing control for outputting the second instruction code as a second instruction code.

According to the above configuration, the pipeline processing stage can be temporarily stopped in accordance with the result of the determination as to whether or not the input instruction code has the NOP field, and stall control can be realized.

Next, the stall control unit includes a first instruction register for latching the first instruction code read from the instruction code storage unit, and a first instruction output from the first instruction register. Code and NOP code, and the first instruction code or NO
A switching unit that selects a P-code and outputs it as a second instruction code, and inputs a second instruction code output from the switching unit, and determines whether the second instruction code is an instruction code having a NOP field Pipeline suspension for performing output control of the stop signal to the address generation unit and the first instruction register and output control of the switch signal to the switching unit based on the determination result. It is preferable to include a part.

According to the above configuration, when the input first instruction code is an instruction code having a NOP field, the first instruction code is output as the second instruction code and the NOP field is temporarily stopped so that the NOP field is stopped. Can be executed. Since the second instruction code is output from the stall control unit, it is executed before NOP.

Next, the stall control unit comprises: a first instruction register for latching the first instruction code read from the instruction code storage unit; and a first instruction register read from the first instruction register. Second to latch code
And a first instruction code and a NOP code output from the second instruction register, and selecting the first instruction code or the NOP code based on a switching signal to generate a second instruction code And a first instruction code output from the first instruction register, and determines whether or not the first instruction code is an instruction code having a NOP field. Based on a result, the address generation unit and the first and second
It is preferable to include a pipeline temporary stop unit that controls the output of the stop signal to the instruction register and the output of the switch signal to the switch unit.

With the above arrangement, the first instruction code is NO
In the case of an instruction code having a P field, the pipeline processing is temporarily stopped, and the NOP code can be output as the second code by the switching signal. Note that N
After the OP is executed, the latched first instruction code is output as the second instruction code. Therefore, the instruction code is output from the stall control unit and executed after the NOP is executed.

Next, the stall control unit inputs a first instruction register for latching the first instruction code read from the instruction code storage unit, an output of the first instruction register, and a NOP code. A first switching unit that selects and outputs an output of the first instruction register or a NOP code based on a first switching signal, and a second instruction register that latches an output of the first switching unit And an output of the second instruction register and a NOP code, and an output or a NOP code of the second instruction register selected based on a second switching signal and output as a second instruction code. 2 and an output from the first switching unit, and determines whether or not the output is an instruction code having a NOP field. Based on the determination result, the address generation unit and the Output control of the stop signal to the first instruction register and a stop signal different from the stop signal to the second instruction register, and output control of the switching signal to the first and second switching units are performed. Preferably, a pipeline pause is included.

With the above configuration, the NOP field is provided in both the first instruction code and the second instruction code, a predetermined number of NOPs are executed after the execution of the first instruction code, and the NOP field is executed before the execution of the second instruction code. By executing a predetermined number of NOPs, the NOP field area provided per instruction can be reduced. In particular, if the instruction code is NO
This is effective when the field margin for providing the P field is small.

It is needless to say that the number of NOPs represented by the bit string in the NOP field is not limited to a binary value, and a combination of bit strings may be determined so as to indicate a specific numerical value.

Next, the pipeline suspending unit is a NOP number counting unit that counts the number of NOPs specified in a NOP field provided in the instruction code, and the instruction code is an instruction code having a NOP field. And a determining unit for determining whether the instruction code has an NOP field. When the determining unit determines that the instruction code has an NOP field, during a pipeline processing stage corresponding to the number of NOPs output from the NOP number counting unit, Preferably, the stop signal is output.

According to the above configuration, it is possible to determine the specific instruction provided with the NOP field and to detect the number of NOPs set in the NOP field.

[0029]

Embodiments of the present invention will be described below. First, the basic concept of the present invention will be described, and then,
A specific embodiment will be described.

First, the basic concept of the program control method of the present invention will be described below. During the program processing, when the same register is referred to in the preceding instruction and the succeeding instruction, resource contention such as register interference may occur.

FIG. 1A shows an example of how register interference occurs. This is a timing chart in the case of a four-stage pipeline, in which the preceding instruction is a data transfer instruction “MOV PR, GR” from GR to PR, and the succeeding instruction is a data transfer instruction from the data memory using the PR value as an address. Transfer instruction “MOV GR, M (PR)”, and both are continuous. In the preceding instruction shown in the upper part, data transfer from GR to PR is performed in the EX stage. on the other hand,
In the subsequent instruction shown in the lower part, the PR addresses the data memory in the D1 stage. In other words, the addressing of the subsequent instruction is performed before the data transfer to the PR by the preceding instruction, and the addressing is performed with the PR value before the data transfer.

In order to avoid the problem of register interference, stall control may be performed by inserting a required number of NOPs between the preceding instruction and the following instruction, and the timing of both may be adjusted. FIG. 1B shows a state in which register interference due to NOP insertion is avoided. Since two NOPs are inserted and the timing of the subsequent instruction is delayed by two pipeline processing stages, the subsequent instruction can be addressed using the PR value after data transfer by the preceding instruction.

As a method of designating NOP insertion, there are a method of detecting resource conflict by hardware and inserting a NOP, and a method of inserting and writing a NOP instruction in a program. Inviting the latter, the number of instructions in the program increases and consumes a lot of memory. Therefore, in the present invention, a method of providing a NOP field in the instruction code and designating NOP insertion is adopted.

There are three methods for providing a NOP field in this instruction code. The first is a method provided in a preceding instruction causing a resource conflict, the second is a method provided in a subsequent instruction, and the third is a method provided separately for both the preceding instruction and the subsequent instruction. Which of the first to third methods should be used depends on the nature of the preceding instruction and the following instruction that cause resource conflict.

FIG. 2 is a chart in which instructions causing resource conflict are classified by paying attention to the number of instruction types and the field margin.
For a combination of a preceding instruction and a succeeding instruction belonging to Type I, a method of providing a NOP field in the instruction code of the first preceding instruction is adopted. The reason is that, as shown in FIG. 3, in this type, the number of NOP fields provided as a whole can be reduced because the number of preceding instructions provided with NOP fields is small and the number of subsequent instructions is large. Conversely, when the NOP field is provided in the subsequent instruction, the number of NOP fields provided as a whole increases.

For the combination of the preceding instruction and the succeeding instruction belonging to Type II, a method of providing a NOP field in the instruction code of the second succeeding instruction is adopted. The reason is that, as shown in FIG. 4, this type has many preceding instructions and few succeeding instructions having a NOP field.
This is because the number of NOP fields provided as a whole can be reduced. Conversely, if the NOP field is provided in the preceding instruction, the number of NOP fields provided as a whole increases.

For the combination of the preceding instruction and the succeeding instruction belonging to Type III, a method is adopted in which the NOP field is divided and provided in the instruction code of both the third preceding instruction and the following instruction. The reason is that in this type, the field margin of the instruction is small, and the NOP field cannot be collectively included in any of the instruction codes before and after. Therefore, the necessary NOP number is designated by dividing the instruction into the preceding and following instructions. This is shown in FIG.

It is needless to say that the instructions such as MOV and ADD shown in FIG. 2 are examples of the preceding instruction and the succeeding instruction. As described above, NO in the instruction code
The stall control method provided with the P field is selected according to the number of instruction types and the field margin, and the following stall control method is realized for the combination of the preceding instruction and the following instruction that causes resource conflict in the processing program. I do.

If the type of the preceding instruction is smaller than the type of the succeeding instruction, the above-mentioned type I is used.
If an OP field is provided and the number of NOPs set in the NOP field is N when the preceding instruction code is decoded, N NOPs are inserted after executing the instruction corresponding to the instruction code. Perform a stall.

If the type of the succeeding instruction is smaller than the type of the preceding instruction, the type II
If an OP field is provided and the number of NOPs set in the NOP field is N when the subsequent instruction code is decoded, the instruction corresponding to the instruction code is executed after inserting N NOPs To execute the stall.

When there is no field margin in the instruction code, NOP fields are provided in both the preceding instruction code and the subsequent instruction code as Type III,
If the number of NOPs set in the NOP field is N when the preceding instruction code is decoded, the number of NOPs set in the NOP field of the preceding instruction code is inserted after executing the instruction of the preceding instruction code. Then, the subsequent instruction code is decoded, and if the number of NOPs set in the NOP field is M, the number set in the NOP field of the subsequent instruction code before the instruction of the subsequent instruction code is executed. Stall is executed by inserting M NOP.

Next, the basic configuration of the program control device of the present invention will be described. FIG. 6 is a block diagram of the basic components of the present invention. 6, 1 is an instruction code storage unit,
2 is an address generation unit, and 3 is a stall control unit. The instruction code storage unit 1 is a memory in which instructions are stored, and the like.
According to the address signal from the address generation unit 2, the corresponding instruction is output to the stall control unit 3 as a first instruction code.

The stall control unit 3 stores the first instruction code 2
1 and NOP code 23 are input. The first instruction code 21 is input, and it is determined whether the first instruction code is an instruction code having a NOP field. As a result of this determination, if the first instruction code 21 is an instruction code having a NOP field, it is decoded and inserted.
The number of OPs is detected, a pipeline pause signal 24 for temporarily suspending the pipeline processing stage to the address generation unit 2 is output by the designated number, and the NOP code 23
Is output as the instruction code 22 of the instruction. next,
If the input first instruction code 21 is an instruction code having no NOP field, the pipeline pause signal 24 to the address generation unit 2 is not output, and the first instruction code 21 is replaced with the second instruction code. Control to output as 22 is performed.

By giving an instruction provided with a necessary NOP field to the program controller having the basic configuration, a required number of NOPs are inserted between instructions causing resource conflict such as register interference to reduce resource conflict. Can be avoided.

The above is the basic concept of the program control method and the program control device according to the present invention. Next, a program control method and a program control device adapted to each of the instruction types I to III classified using FIG. 2 will be described as first to third embodiments.

(Embodiment 1) The embodiment 1 is an application example in the case of Type I in which the type of the preceding instruction is smaller than the type of the following instruction. The NOP field of the input preceding instruction code is detected, and After executing the relevant instruction,
The stall is executed by inserting the NOP of the cycle corresponding to the value of N.

FIG. 7 is a block diagram mainly showing the stall control unit 3 of the program control device according to the first embodiment. For convenience, illustration of the instruction code storage unit 1 and the address generation unit 2 is omitted. In FIG. 7, reference numeral 11 denotes a first instruction register as an instruction holding unit, which receives a first instruction code 21 as an input, receives a pipeline pause signal 24 as a control signal input, and outputs a latch signal 26 as an output. Reference numeral 12 denotes a multiplexer as a switching unit, which receives the NOP code 23 and the output 26 of the first instruction register 11 as input signals,
Is a control signal input, and a second instruction code 22 is output. Reference numeral 13 denotes a pipeline suspending unit which receives the second instruction code 22 and outputs a switching signal 25 and a pipeline suspending signal 24.

FIG. 10 shows an example of a circuit configuration of the pipeline temporary stop unit 13 when the NOP field is composed of 2 bits. In FIG. 10, 101 is NOP
The first instruction code 21 (may be an instruction code other than the NOP field) is input to the designated instruction
Detects whether a field is provided. In addition,
In FIG. 7 of the first embodiment, the second instruction code 22 is input, but the first instruction code 21 is selected and input by the multiplexer 12. It is assumed that the first instruction code 21 is also input in other embodiments described later.

In the NOP-designated instruction determining unit 101, the first
If the instruction code 21 is an instruction having a NOP field, it outputs logic "1", and if it is an instruction having no NOP field, it outputs logic "0". 102 and 103 are flip-flops (hereinafter, FFs)
, 104 and 105 are OR (logical sum) gates, and 106 is an AND (logical product) gate. The flip-flop 102 and the OR gates 104 and 105 form a NOP number counting unit 107. When the instruction code employs LSB, the NOP field is the lower 2 bits here, the signal 111 is the lower bit of the NOP field, and the signal 112 is the upper bit of the NOP field.

The FF 102 receives the signal 112 as an input. F
F103 receives the output of the AND gate 106 as an input, and outputs a switching signal 15 and a pipeline pause signal 24.
The OR gate 104 outputs the signal 112 from the output from the FF 102.
Is input. The OR gate 105 receives the signal 111 and the output from the OR gate 104 as inputs. AND gate 10
Reference numeral 6 designates an input from an output from the OR gate 105 and an output from the instruction determination unit 101 with NOP designation.

With this circuit configuration, when the first instruction code 21 is an instruction having a NOP field, the pipeline temporary stop unit 13 outputs the switching signal 25 for the processing stage corresponding to the designated NOP number and the pipeline temporary stop unit 13. The stop signal 24 is output.

The operation of the program control device configured as described above will be described with reference to FIG. 6, FIG. 7, FIG. 10, FIG.
5 will be described. FIG. 12 shows the bit field of the preceding instruction code provided with the NOP field, and bit 0 and bit 1 are the NOP field. When bit 0 is 1, the number of NOPs N = 1 is indicated, and when bit 1 is 1, the number of NOPs N = 2 is indicated. FIG.
5 is a flowchart showing an outline of a processing flow by the program control device of the present embodiment. FIG. 15 shows a timing chart for a four-stage pipeline,
The transfer instruction (MOVPR, GR) is an example of the instruction.

Hereinafter, the operation will be described for each step. (1) Step 1 The address held by the program counter of the address generation unit 2 is output to the instruction code storage unit 1. The instruction code storage unit 1 reads the first instruction code 21 corresponding to the input address and outputs the first instruction code 21 to the stall control unit 3.

(2) Steps 2 and 3 In the stall control section 3, the first instruction register 11 holds the first instruction code 21, and the multiplexer 12 selects the output 26 of the first instruction register 11. Output as the second instruction code 22. The pipeline temporary stop unit 13 receives the output signal 22 and detects the instruction code provided with the NOP field by the instruction determination unit with NOP designation 101.

(3) Step 4 The pipeline suspending unit 13 determines that the signal 111 as the lower bit of the NOP field is 1 (see FIG. 15).
(A)) outputs the pipeline pause signal 24 and the switching signal 25 for one cycle. When the signal 112, which is the upper bit of the NOP field, is 1 (see FIG. 15).
(B)) outputs the pipeline pause signal 24 and the switching signal 25 for two cycles.

(4) Step 5 In response to the switching signal 25, the multiplexer 12 selects the NOP code 23 and outputs it as the second instruction code 22, and the program counter continuously holds the address, and the first instruction register 11 holds the first instruction code 21.

(5) Step 6 Transit to the next instruction processing stage. As described above, the program control device according to the first embodiment can temporarily stop the pipeline processing stage according to the determination result as to whether or not the input preceding instruction code includes the NOP field, and can realize stall control. That is, according to the input NOP field of the preceding instruction, the pipeline processing of the succeeding instruction is temporarily stopped, and resource conflict such as register interference is avoided. (Second Embodiment) Embodiment 2 is an application example in the case of Type II in which the type of the subsequent instruction is smaller than the type of the preceding instruction, and the NO of the subsequent instruction code input following the preceding instruction.
The P field is detected, and the cycle NO according to the value of N is determined.
A stall is executed by inserting P, and thereafter, a subsequent instruction corresponding to the instruction code is executed.

FIG. 8 is a block diagram mainly showing the stall control unit 3 of the program control device according to the second embodiment. For convenience, illustration of the instruction code storage unit 1 and the address generation unit 2 is omitted. In FIG. 8, reference numeral 11 denotes a first instruction register, which is a first instruction holding means, which receives a first instruction code 21 as an input, a pipeline pause signal 24 as a control signal input, and outputs a latch signal 26. Reference numeral 13 denotes a pipeline suspending unit which receives the output 26 of the first instruction register as an input signal, and outputs a pipeline suspending signal 24 and a switching signal 2
5 is output. Reference numeral 14 denotes a second instruction register which is a second instruction holding unit, which receives a latch output 26 from the first instruction register, receives a pipeline pause signal 24 as a control signal input, and outputs a latch signal 27. . Reference numeral 12 denotes a multiplexer as a switching unit, which receives a NOP code 23 and an output 27 from the second instruction register 14 as input signals, a switching signal 25 as a control signal input, and outputs a second instruction code 22.

In FIG. 8, components having the same functions as those in FIG. 7 are denoted by the same reference numerals. Further, the circuit configuration example of the pipeline temporary stop unit 13 may be the same as that shown in FIG. 10 in the first embodiment. In the second embodiment, when the first instruction register output 26 which is a latch signal of the first instruction code 21 is input and the signal is an instruction having a NOP field, the pipeline suspending unit 13 The switching signal 25 and the pipeline temporary stop signal 24 of the cycle corresponding to the designated NOP number are output.

The operation of the program control device configured as described above will be described with reference to FIGS. 6, 8, 10, 12, and 16 to 1.
7 will be described. Stall control 3 of the second embodiment
Is applied to the bit field of the subsequent instruction code shown in FIG. 12 as in the first embodiment. When bit 0 is 1, the number of NOPs N = 1 is indicated, and bit 1 is 1
At this time, it is assumed that the number of NOPs N = 2. FIG.
9 is a flowchart schematically showing the flow of processing by the program control device according to the second embodiment. FIG. 17 is a timing chart for a four-stage pipeline according to the second embodiment, in which the subsequent instruction is a branch instruction (BRC).
Z, JMP) is an example of an instruction.

The operation will be described below for each step. (1) Step 1 The address held by the program counter of the address generation unit 2 is output to the instruction code storage unit 1. The instruction code storage unit 1 reads and outputs the first instruction code 21 corresponding to the input address.

(2) Step 2 The first instruction register 11 holds the first instruction code 21 and outputs an output signal 26. The latch output signal 26 is input to the pipeline temporary stop unit 13 and the second instruction register 14. The pipeline temporary stop unit 13 receives the latch output signal 26, and the instruction determination unit with NOP designation 101 detects that the instruction code has an NOP field.

(3) Step 3 The pipeline suspending unit 13 determines that the signal 111 which is the lower bit of the NOP field is 1 (see FIG. 17).
(A)) outputs the pipeline pause signal 24 and the switching signal 25 for one cycle. Also, when the signal 112 which is the upper bit of the NOP field is 1 (see FIG. 17).
(B)) outputs the pipeline pause signal 24 and the switching signal 25 for two cycles.

(4) Step 4 In response to the switching signal 25, the multiplexer 12 selects the NOP code 23 and outputs it as the second instruction code 22, and the program counter continuously holds the address, and the first instruction register 11 Holds the first instruction code 21, and the second instruction register 14 outputs the output signal 27 (first
(Same as the instruction code 21).

(5) Step 5 The signal of the switching signal 25 is inverted, and the multiplexer 12 selects the output 27 (the first instruction code is latched) of the second instruction register 14 and the second instruction code Output as 22.

(6) Step 6 A transition is made to the next instruction processing stage. According to the second embodiment, the program control device can suspend the pipeline processing stage according to the result of the determination as to whether or not the input subsequent instruction code includes the NOP field, and stall control can be realized. In other words, the required number of NOPs are inserted according to the input NOP field of the subsequent instruction, and the processing stage of the subsequent instruction is temporarily stopped, thereby avoiding resource conflict such as register interference. (Third Embodiment) The third embodiment is an application example in the case of Type III where the field margin of the instruction code is small, and detects the NOP field of the input preceding instruction code.
After executing the instruction corresponding to the instruction code, the stall is executed by inserting the NOP of the cycle corresponding to the value of N, and the NOP field of the input subsequent instruction code is detected, and the cycle corresponding to the value of N is detected. The stall is executed by inserting the NOP, and the subsequent instruction corresponding to the instruction code is executed.

FIG. 9 is a block diagram mainly showing the stall control unit 3 of the program control device according to the third embodiment. For convenience, illustration of the instruction code storage unit 1 and the address generation unit 2 is omitted. In FIG. 9, reference numeral 11 denotes a first instruction register, which is a first instruction holding means, which receives a first instruction code 21 as an input, a first pipeline temporary stop signal 24a as a control signal input, and a latch signal 26 as a first instruction register. Output. Reference numeral 12 denotes a first multiplexer which is a switching unit, which receives an output 26 from the first instruction register and a NOP code 23 as input signals,
A first selection signal is output using the first switching signal 25a as a control signal. Reference numeral 13 denotes a pipeline suspending unit which receives an output 26 from the first instruction register as an input, and outputs a first pipeline suspending signal 24a, a second pipeline suspending signal 24b, a first switching signal 25a, The second switching signal 25b is output.

Reference numeral 14 denotes a second instruction register which is a second instruction holding unit, and a latch output 26 from the first instruction register.
, The second pipeline pause signal 24b as a control signal input, and the latch output 27 as an output. Fifteen
Is a second multiplexer as a second switching unit, and NO
P code 23 and latch output 2 of second instruction register 14
7 as an input signal, a second switching signal 25b as a control signal input, and a second instruction code 22 output.

In FIG. 9, components having the same functions as those in FIGS. 7 and 8 are denoted by the same reference numerals. An example of a circuit configuration of the pipeline temporary stop unit 13 is as shown in FIG. In the third embodiment, it is necessary to discriminate between a preceding instruction (with NOP field) and a subsequent instruction (with NOP field), and it is necessary to separately output a “pipeline pause signal” and a “switching signal”. is there. In FIG. 11, reference numeral 201 denotes a first instruction corresponding to the preceding instruction.
Is a second NOP-designated instruction determining unit corresponding to a subsequent instruction, and receives a first instruction code 21 (which may be an instruction code other than the NOP field) as an input, It is detected whether a NOP field is provided. 203 to 205 are FF, 2
07 and 208 are AND (logical product) gates, 206 is O
R (logical sum) gate. If the instruction code employs LSB, the NOP field is the least significant bit and the signal 111 is the least significant bit of the instruction code. F
F203 outputs a first switching signal 25a, and FF204
Outputs a second switching signal 25b and a second pipeline halt signal 24b, and the FF 205 outputs a first pipeline halt signal 24a. In the third embodiment, when the preceding instruction is input as the first instruction code 21, if the signal is an instruction having a NOP field,
A first pipeline temporary stop signal 24a and a first switching signal 25a for a cycle corresponding to the designated NOP number are output. Next, when the subsequent instruction is input as the first instruction code 21, if the signal is an instruction having a NOP field, the pipeline temporary stop unit 13
The first pipeline pause signal 24a and the second pipeline pause signal 24b for the number of cycles corresponding to the number of OPs
And the second switching signal 25b.

The operation of the program control device configured as described above will be described with reference to FIG. 6, FIG. 9, FIG. 11, FIG.
9 will be described. The bit fields of the preceding instruction and the subsequent instruction code to which the stall control of the third embodiment is applied are as shown in FIG. The NOP field is provided with only the lower one bit, and when bit 0 is 1,
The NOP number N = 1 is indicated. FIG. 18 is a flowchart schematically illustrating the flow of processing by the program control device according to the third embodiment. FIG. 19 shows the fourth embodiment according to the third embodiment.
5 shows a timing chart in the case of a stage pipeline, in which an immediate transfer instruction (MOV PR, immediate) to PR and an add instruction (ADD) accompanied by access to a data memory are shown.
GR, M (PR)) as an example of the instruction.

Hereinafter, the operation will be described for each step. (1) Step 1 The address held by the program counter of the address generation unit 2 is output to the instruction code storage unit 1. The instruction code storage unit 1 reads and outputs the first instruction code 21 that is the preceding instruction in accordance with the input address.

(2) Steps 2 and 3 The first instruction register 11 holds the first instruction code 21 and the first multiplexer 12 stores the first instruction register 1
1 is selected and an output signal 28 is output. The pipeline suspending unit 13 receives the output signal 28,
The P-designated instruction determining unit 101 detects that the instruction code has a NOP field.

(3) Step 4 The first instruction code 21 becomes the output 28 of the first multiplexer 12 and is input to the pipeline temporary stop unit 13 and the second instruction register 14. The first instruction code 2
1 is output as a second instruction code 22 via the second instruction register 14 and the second multiplexer 15.

On the other hand, the pipeline suspending unit 13
When the signal 111, which is the lower bit of the OP field, is 1 (FIG. 19), the first pipeline stop signal 24a and the first switching signal 25a are output for one cycle.

(4) Step 5 The first multiplexer 12 is activated by the first switching signal 25a.
Selects the NOP code 23 and outputs the output signal 28. In addition, the program counter holds the address and the first instruction register 12 holds the first instruction code 21 due to the first pipeline suspension 24a.

(5) Step 6 The program counter of the address generation unit 2 is incremented, and the updated address is output to the instruction code storage unit 1. In response to the address, the instruction code storage unit 1 stores the subsequent instruction in the This is output as the instruction code 21 of 1.

(6) Step 7 The first instruction register 11 holds the first instruction code 21, and the first multiplexer 12 stores the first instruction register 1
The latch output 26 from 1 is selected and an output signal 28 is output. The pipeline pause unit 13 outputs the output signal 28
Is input, and the NOP designation command determination unit 101
It detects that the instruction code has a field.

(7) Step 8 The pipeline suspending unit 13 determines that the signal 111 which is the lower bit of the NOP field is 1 (FIG. 19).
Outputs a second switching signal 25b and a second pipeline pause signal 24b for one cycle.

(8) Step 9 The output signal 28 of the first multiplexer 12 is input to the second instruction register 14, but the second instruction register 14 is transmitted to the second instruction register 14 by the second pipeline pause signal 24b. A certain first instruction code 21 is held. Also, the second
, The second multiplexer 15 selects the NOP code 23 and outputs it as the second instruction code 22.

(9) Step 10 The second multiplexer 15 selects the output of the second instruction register 14 and outputs it as the second instruction code 22.

(10) Step 11 A transition is made to the next instruction processing stage. According to the third embodiment, the program control device can suspend the pipeline processing stage according to the determination result of whether or not each of the input preceding instruction code and the subsequent instruction has the NOP field. Can be realized. That is, the processing stage of the subsequent instruction is temporarily stopped for a predetermined number of NOP cycles in accordance with the input NOP field of the preceding instruction, and a predetermined number of NOPs are inserted according to the input NOP field of the subsequent instruction to process the subsequent instruction. The stage will be paused further, avoiding resource conflicts such as register interference.

According to the present embodiment, a stall (delay time) equivalent to the first and second embodiments can be obtained while reducing the size of the NOP field from 2 bits to 1 bit.

In the above embodiment, the NOP number represented by the bit string in the NOP field has been described as a binary value. However, the combination of bit strings is determined so as to indicate a specific numerical value, and the NOP number is determined. May be. For example, a combination of “0” and “1” represented by 2 bits is
“00” → 0, “01” → 2, “10” → 4, “11”
→ You can make an agreement of 6. Also, "0
0 → 0, “01” → 3, “10” → 6, “11” → 9
You can make an agreement. According to such an agreement, a numerical value of 4 or more can be specified by using 2 bits, so that it is particularly effective when the field margin is small.

[0084]

According to the program control method and apparatus of the present invention, stall control can be realized by inserting a predetermined number of NOPs with reference to the NOP field in the instruction code. If a processing program includes a preceding instruction and a succeeding instruction that cause resource conflict, a NOP is inserted after the preceding instruction is executed, and a stall that temporarily stops the processing stage of the succeeding instruction can be realized by executing the succeeding instruction at the end. .

Further, according to the program control method and apparatus of the present invention, the NOP for stall control at the time of resource contention is controlled.
By providing the NOP field in the instruction code with a small number of instructions, the increase in the amount of instruction code data can be suppressed.

Further, according to the program control method and apparatus of the present invention, when the field margin for providing the NOP field in the instruction code is small, the stall control is performed using the NOP field of the preceding instruction and the NOP field of the subsequent instruction. Thus, it is possible to provide a program control method and apparatus in which the field margin is increased as compared with the conventional method.

[Brief description of the drawings]

FIG. 1 is a diagram showing how register interference occurs and how register interference due to NOP insertion is avoided.

FIG. 2 is a diagram in which instructions causing resource conflict are classified by paying attention to the number of instruction types and a field margin;

FIG. 3 is an instruction field of a preceding instruction and a following instruction belonging to type I in the classification of FIG. 2;

FIG. 4 is an instruction field of a preceding instruction and a following instruction belonging to type II in the classification of FIG. 2;

5 is an instruction field of a preceding instruction and a following instruction belonging to type III in the classification of FIG. 2;

FIG. 6 is a basic configuration diagram of a program control device of the present invention.

FIG. 7 is a configuration diagram of a program control device according to the first embodiment of the present invention.

FIG. 8 is a configuration diagram of a program control device according to a second embodiment of the present invention.

FIG. 9 is a configuration diagram of a program control device according to a third embodiment of the present invention.

FIG. 10 is a detailed circuit configuration diagram of a pipeline temporary stop unit 13 in the program control device of FIGS. 7 and 8;

11 is a detailed circuit configuration diagram of a pipeline temporary stop unit 13 in the program control device of FIG. 9;

FIG. 12 is an instruction field diagram of an instruction code according to the first and second embodiments of the present invention.

FIG. 13 is an instruction field diagram of an instruction code according to the third embodiment of the present invention.

FIG. 14 is a flowchart showing an outline of a processing flow by the program control device according to the first embodiment of the present invention;

FIG. 15 is a timing chart for a four-stage pipeline in the program control device according to the first embodiment of the present invention;

FIG. 16 is a flowchart showing an outline of a processing flow by a program control device according to the second embodiment of the present invention;

FIG. 17 is a timing chart for a four-stage pipeline in the program control device according to the second embodiment of the present invention;

FIG. 18 is a flowchart showing an outline of a processing flow by a program control device according to a third embodiment of the present invention;

FIG. 19 is a timing chart for a four-stage pipeline in the program control device according to the third embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 instruction code storage unit 2 address generation unit 3 stall control unit 11 first instruction register 12 first multiplexer 13 pipeline temporary stop unit 14 second instruction register 15 second multiplexer 21 first instruction code 22 second 23 NOP code 24 Pipeline pause signal 24a First pipeline pause signal 24b Second pipeline pause signal 25 Switching signal 25a First switching signal 25b Second switching signal 26 First instruction Output signal of register 11 27 Output signal of second instruction register 14 28 Output signal of second multiplexer 15 101 Instruction determination unit with NOP designation 201 First instruction determination unit with NOP designation 202 Second instruction determination with NOP designation Units 102 to 103, 203 to 204 flip-flops 104 105 and 206 OR gate 106,207～208 upper bits of the lower bit 112 NOP field of the AND gate 111 NOP field

Claims (8)

[Claims] 1. A program control method in an information processing apparatus for processing an instruction in a pipeline, wherein a NOP field indicating the number of NOPs which are non-processing instructions is provided in the instruction code, and when the instruction code is decoded, If the number of NOPs set in the NOP field is N, N N
A program control method for executing a stall by executing an instruction corresponding to the instruction code after inserting an OP. 2. A processing program comprising a preceding instruction and a succeeding instruction which cause resource conflict, and wherein the type of the following instruction is smaller than the type of the preceding instruction, a NOP field is provided in the subsequent instruction code. 2. The program control method according to 1. 3. A program control method in an information processing apparatus for performing pipeline processing of an instruction, wherein when a processing program includes a preceding instruction and a subsequent instruction that cause resource conflict, the processing instruction program includes a preceding instruction code and a following instruction code. Are provided with NOP fields, and after executing the instruction of the preceding instruction code, insert the set number of NOPs into the NOP field of the preceding instruction code, and execute the subsequent instruction before executing the instruction of the subsequent instruction code. A program control method for executing a stall by inserting a set number of NOPs into a NOP field of a code. 4. A program control device for pipeline-processing an instruction including an instruction code having a NOP field designating a NOP, wherein the instruction code storage unit stores a first instruction code, and the instruction code storage unit stores the first instruction code. An address generation unit for generating an address for outputting the first instruction code from the unit; and inputting the first instruction code, and determining whether the first instruction code is an instruction code having a NOP field A stall control unit that controls output of a stop signal for temporarily stopping a pipeline processing stage to the address generation unit based on a result, and control of outputting the first instruction code or NOP code as a second instruction code. A program control device comprising: 5. A stall control unit comprising: a first instruction register for latching the first instruction code read from the instruction code storage unit; and a first instruction code output from the first instruction register And a NOP code, and selects a first instruction code or NOP code based on a switching signal and outputs the selected instruction code or NOP code as a second instruction code; and a second instruction code output from the switching unit. Input,
Determining whether the second instruction code is an instruction code having a NOP field, based on the determination result, controlling output of the stop signal to the address generator and the first instruction register; 5. The program control device according to claim 4, further comprising a pipeline temporary stop unit that controls output of the switching signal to a switching unit. 6. The stall control unit, comprising: a first instruction register for latching the first instruction code read from the instruction code storage unit; and a first instruction code read from the first instruction register. A second instruction register that latches a first instruction code and a NOP code output from the second instruction register, and selects the first instruction code or the NOP code based on a switching signal. A switching unit that outputs as a second instruction code, and a first instruction code that is output from the first instruction register, and determines whether the first instruction code is an instruction code having a NOP field. Determining, based on the determination result, controlling output of the stop signal to the address generation unit and the first and second instruction registers, and controlling the switching signal to the switching unit. 5. The program control device according to claim 4, further comprising a pipeline suspension unit for performing output control. 7. The stall control unit, comprising: a first instruction register for latching the first instruction code read from the instruction code storage unit; an output of the first instruction register and a NOP code; A first switching unit for selecting and outputting an output of the first instruction register or a NOP code based on a first switching signal; a second instruction register for latching an output of the first switching unit; A second instruction register which receives an output of the second instruction register and a NOP code, selects an output of the second instruction register or a NOP code based on a second switching signal, and outputs the selected output as a second instruction code. And an output from the first switching unit, and the output is NO
It is determined whether or not the instruction code has a P field. Based on the determination result, the stop signal to the address generation unit and the first instruction register and the stop signal to the second instruction register are different. 5. A pipeline pause unit for controlling output of a stop signal and controlling output of the switching signal to the first and second switching units.
The program control device according to the above. 8. The NOP number counting section for counting the number of NOPs specified in a NOP field provided in an instruction code, the pipeline temporary stopping section, and whether the instruction code is an instruction code having a NOP field. When the determination unit determines that the instruction code has an NOP field, during the pipeline processing stage corresponding to the number of NOPs output from the NOP number counting unit, 5. The program control device according to claim 4, which outputs a stop signal.