JP2015210628A - Programmable controller in which no external memory access for calculated data reading occur - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable controller for shortening the execution time of an instruction with a hardware configuration where the reading of calculated data at a low access speed does not occur between different processors.SOLUTION: A programmable controller 100 for executing a sequence program includes: a first processor 10 for executing a predetermined first instruction; a second processor 20 for executing a second instruction which is not executable by the first processor; an instruction decoder 16 incorporated in the first processor 10 for decoding an instruction to be processed by the second processor 20 included in an instruction code configuring a sequence program and a code generator 17 incorporated in the first processor 10, and incorporated with a memory access circuit for performing the reading of a memory for acquiring calculated data necessary for the second processor 20 to execute the instruction from the address information of the calculated data.

Description

  The present invention relates to a programmable controller, and more particularly to a programmable controller that does not generate an external memory access for reading operation data by a processor.

  In the programmable controller, the sequence program processing is composed of a dedicated processor (ASIC) specialized for arithmetic processing on 1-bit data and a general-purpose processor (CPU) for executing complex instructions that handle data of 1 byte or more. It is often executed by hardware (see, for example, Patent Document 1).

JP 2009-116445 A

  In the hardware composed of two processors as in the prior art, there is only one memory for storing operation data, and this memory can be accessed at high speed from one processor, but it depends on the other processor. The access speed is slow, which causes the instruction execution speed to slow down.

  For example, in the case of a programmable controller configured as shown in FIG. 3, the arithmetic data storage memory is built in the dedicated processor, so that it can be accessed at high speed from the arithmetic processing circuit of the dedicated processor. Since the data storage memory is connected by an external bus, access to the operation storage memory by the general-purpose processor is slower than access to the operation data storage memory of the dedicated processor.

As a technique for solving the problems found in the prior art, a configuration in which a sequence program is executed only by a general-purpose processor (using a general-purpose processor built-in data cache) can be considered. In the case of using this configuration, in the sequence program processing, word / longword access is performed across the alignment boundary of the memory for 1-bit data operation processing, operation data read / operation result data write. For this reason, it is necessary to select a general-purpose processor for sequence program processing that satisfies the following conditions.
Condition 1: A means for executing read-modify-write atomically in order to execute arithmetic processing of 1-bit data by a general-purpose processor.
Condition 2: In order to maintain the coherency (consistency) of data at the time of word / longword access across the memory alignment boundary, it has means for executing two memory accesses atomically.

  Further, as another technique for solving the problem, it may be configured to execute processing of a part of frequently used function instructions by an exclusive processor (ASIC). However, in order to provide such a configuration, it is necessary to incorporate a processing circuit for complex functional instructions into an exclusive processor (ASIC), so that much time and cost are required for development and evaluation of the ASIC.

  Accordingly, an object of the present invention is to provide a programmable controller that shortens the execution time of an instruction by adopting a hardware configuration that does not cause reading of operation data having a low access speed between different processors.

  According to the first aspect of the present invention, in a programmable controller that executes a sequence program, a first processor that executes a predetermined first instruction, and a second instruction that executes a second instruction that cannot be executed by the first processor The first processor is included in a memory for storing operation data used when executing the first instruction and the second instruction, and an instruction code constituting the sequence program. A decoding circuit that decodes information related to an instruction processed by the second processor and a memory access circuit that reads out the operation data from the memory based on address information of the operation data decoded by the decoding circuit are incorporated. A programmable controller having a code generator It is over La.

  The invention according to claim 2 of the present application is characterized in that the code generator includes an address conversion circuit that calculates an address on a memory in which a function for executing an instruction processed by the second processor is stored. The programmable controller according to claim 1.

  According to a third aspect of the present invention, the code generator combines the operation data and the load instruction code of the second processor, and the second processor uses the operation data as the general-purpose of the second processor. The programmable controller according to claim 1, wherein a load instruction to be loaded into a register is generated.

In the invention according to claim 4 of the present application, the code generator combines an address data on a memory storing a function and a branch instruction code of the second processor, and generates an instruction to be executed by the second processor. Generate a branch instruction to branch to the corresponding function,
The programmable controller according to claim 1.

  In the invention according to claim 5 of the present application, the code generator generates an instruction code of the second instruction that can be executed by the second processor, which is necessary for the second processor to execute a sequence program. 2. The programmable controller according to claim 1, wherein the instruction code is transferred to a buffer memory that can be read by the second processor.

  The invention according to claim 6 of the present application is such that the code generator fetches the second instruction to be executed by the second processor from a sequence program, except for the NOP (No Operation) code of the second processor. The programmable controller according to claim 1, wherein the instruction code is transferred to a buffer memory that can be read by the second processor.

  The invention according to claim 7 of the present application is characterized in that the buffer memory seems to be arranged in a memory space when the code generated by the code generator is viewed from a second processor. 6. The programmable controller according to 6.

  According to the present invention, it is possible to reliably reduce the processing time of instructions to be executed by a general-purpose processor used in a sequence program, while taking advantage of the advantages of a dedicated processor (ASIC) and a general-purpose processor (CPU). A controller can be provided.

It is a block diagram of the programmable controller based on this invention. 5 is a diagram illustrating an example of contents of a buffer 15. FIG. It is a block diagram of the programmable controller based on a prior art.

  Hereinafter, an embodiment of a programmable controller of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram of a programmable controller of the present invention.
The programmable controller 100 includes a dedicated processor 10, a general-purpose processor 20, a main memory 30, a bus 40, and a bus 50.

  The dedicated processor 10 includes an arithmetic processing circuit 11, an arithmetic data storage memory 12, an arbitration circuit 13, an I / F 14, a buffer 15, an instruction decoder 16, a code generator 17, and a buffer 18. The arithmetic processing circuit 11 is a circuit that performs arithmetic processing on an instruction to be executed by a dedicated processor, for example, 1-bit data. The calculation data storage memory 12 stores calculation target data to be subjected to calculation processing. The arbitration circuit 13 controls writing / reading to / from the arithmetic data storage memory 12. The I / F 14 is an interface circuit that is used when the dedicated processor 10 takes out the sequence program code from the main memory 30 and receives an operation result from the general-purpose processor 20. The buffer 15 is a buffer memory used when the load / branch instruction generated by the code generator 17 is transferred to the general-purpose processor 20, and the main body of the buffer 15 is composed of, for example, several stages of FIFOs. The instruction decoder 16 has a function of decoding an instruction fetched from the main memory 30. The code generator 17 has a function of generating a load / branch instruction to be executed by the general-purpose processor 20 and transferring the code to the general-purpose processor 20 when a code to be executed by the general-purpose processor 20 is fetched. The buffer 18 is used as a write buffer when the result of the instruction executed by the general-purpose processor 20 is written in the arithmetic data storage memory 12.

  The general-purpose processor 20 executes an instruction that cannot be executed by the dedicated processor and that should be executed by the general-purpose processor (hereinafter referred to as a function instruction). In this embodiment, the general-purpose processor 20 is connected to a dedicated processor via two buses. One is a bus 40 realized by PCI-Express or the like. The bus 40 is connected to the buffer 15, and is used by the general-purpose processor 20 to read a function instruction from the buffer 15. The other is a bus 50, which is used when the general-purpose processor 20 reads a function instruction function code from the main memory and writes a result of executing the function instruction into the buffer 18 of the dedicated processor 10.

  The main memory 30 stores a sequence program code executed by the dedicated processor 10 and a function instruction function code executed by the general-purpose processor 20. In the present embodiment, the main memory 30 is connected to the dedicated processor 10 and the general-purpose processor 20 via the bus 50.

  Further, in order to make each code generated by the code generator and transferred to the buffer 15 appear to be arranged in the code area on the memory when viewed from the general-purpose processor, for example, the address space of the buffer 15 is stored on the memory. Is mapped to a part of the address space. With this configuration, the code generated by the code generator and transferred to the buffer 15 seems to be arranged in the code area on the memory space as seen from the general-purpose processor. The code can be executed directly.

  Next, a sequence program execution process in the programmable controller 100 having the above hardware configuration will be described.

  The programmable controller in the present embodiment handles two types of program codes: “sequence program code” and “code configured by the instruction set of the general-purpose processor 20”. The sequence program code is a code that can be directly executed by the dedicated processor 10 and cannot be executed by the general-purpose processor 20. The sequence program code includes an intermediate code indicating the type of instruction executed by the general-purpose processor 20 and the address information / size / format (binary format, BCD format, etc.) of the operation data. On the other hand, the code configured by the instruction set of the general-purpose processor 20 is a code that can be directly executed by the general-purpose processor 20 and cannot be executed by the dedicated processor 10.

  The dedicated processor 10 writes a “NOP (No-Operation)” instruction code in the buffer 15 when a functional instruction to be executed by the general-purpose processor 20 is not generated. A branch instruction for returning to the start address of the buffer memory is recorded every n bytes according to the apparent memory size of the buffer memory (memory size as viewed from the general-purpose processor 20). For example, when the instruction length of the instruction set of the general-purpose processor 20 is 4 bytes and the apparent size of the buffer memory is 64 bytes, the branch instruction code “BL StartAddress” to the buffer head address every 64 bytes (16 instructions) Insert. In this case, the buffer 15 as a code area viewed from the general-purpose processor 20 is in a state as shown in FIG.

The dedicated processor 10 fetches the program code from the main memory 30 via the external bus 50. When the fetched program code is a sequence program code, execution processing is performed by a dedicated processor. On the other hand, when the fetched program code is an instruction to be executed by the general-purpose processor 20, information such as the instruction type and the address information, size, and format of the operation data is decoded from the instruction code. The code generator 17 performs the following processing using each piece of information.
Step 1: Necessary operation data is read from the operation data storage memory 12 based on the address information, size, and format of the decoded operation data.
Step 2: Calculate the address of the memory storing the processing function of the corresponding instruction based on the decoded instruction type.
Step 3: The instruction set of the general-purpose processor 20 (“instruction code for loading the operand data into the general-purpose register of the general-purpose processor 20” and “processing function of the corresponding instruction) using the arithmetic-operation data and the address obtained in steps 1 and 2 The instruction code that branches to the address where "is stored") is generated.
Step 4: The instruction code generated in Step 3 is transferred to the general-purpose processor 20 via the buffer 15.
Here, the buffer 15 is composed of, for example, two banks, and the instruction code generated in step 3 is written to the buffer 15 by a method such as transferring the instruction code to the general-purpose processor 20 when writing of the instruction code to one buffer is completed. The timing is not overlapped with the timing at which the data in the buffer 15 is transferred to the general-purpose processor 20.

  When the instruction code generated by the code generator 17 is transferred, the buffer 15 as a code area viewed from the general-purpose processor 20 is in a state as shown in FIG. Here, "LD Data_A, GPR_1", "LD Data_B, GPR_2", and "LD Data_C, GPR_3" are instructions for loading the operation data Data_A, Data_B, Data_C into the general registers GPR_1, GPR_2, GPR_3 provided in the general processor 20, respectively. is there. “BL InstAddress” is a branch instruction code that branches to an address of the main memory 30 in which the corresponding instruction processing function is stored.

  Then, the general-purpose processor 20 reads out the program code generated by the dedicated processor 10 from the buffer 15 and sequentially executes it. When the function instruction processing is performed, a load instruction and a branch instruction are written in the buffer 15 as shown in FIG. 2B. Therefore, the general-purpose processor 20 executes this to branch to the corresponding function instruction function code, and the general-purpose processor 20 The operation data is extracted from the general-purpose register provided and the operation process is executed.

  After the arithmetic processing is completed, the general-purpose processor 20 writes the operation result to the buffer 18 built in the dedicated processor 10 via the bus 50, and then the operation result is stored from the buffer 18 into the operation data storage memory 12.

  As described above, when the general-purpose processor 20 executes the function instruction, the low-speed memory access process that has been a large proportion of the processing time does not occur so that the function instruction can be processed at a higher speed than in the past.

10 Dedicated Processor 11 Arithmetic Processing Circuit 12 Arithmetic Data Storage Memory 13 Arbitration Circuit 14 I / F
15 Buffer 16 Instruction decoder 17 Code generator 18 Buffer 20 General-purpose processor 30 Main memory 40 Bus 50 Bus 100 Programmable controller

Claims (7)

In a programmable controller that executes a sequence program,
A first processor for executing a predetermined first instruction;
A second processor that executes a second instruction that cannot be executed by the first processor;
The first processor is
A memory for storing operation data to be used when executing the first instruction and the second instruction;
A decoding circuit for decoding information related to an instruction to be processed by the second processor included in an instruction code constituting the sequence program;
A code generator including a memory access circuit that reads out the operation data from the memory based on address information of the operation data decoded by the decoding circuit;
A programmable controller characterized by that. The code generator includes an address conversion circuit that calculates an address on a memory in which a function for executing an instruction processed by the second processor is stored.
The programmable controller according to claim 1. The code generator combines the operand data and the load instruction code of the second processor, and generates a load instruction for the second processor to load the operand data into a general-purpose register of the second processor. ,
The programmable controller according to claim 1. The code generator is a branch for branching to a function corresponding to an instruction to be executed by the second processor by combining address data on a memory storing a function and a branch instruction code of the second processor Generate instructions,
The programmable controller according to claim 1. The code generator generates an instruction code of the second instruction that can be executed by the second processor, which is necessary for the second processor to execute a sequence program, and the instruction code is generated by the second processor. Transfer to a buffer memory that can be read,
The programmable controller according to claim 1. The code generator generates a NOP (No Operation) code of the second processor, except when the second instruction to be executed by the second processor is fetched from a sequence program. Transfer to a buffer memory that the second processor can read;
The programmable controller according to claim 1. The buffer memory seems to be arranged in a memory space when the code generated by the code generator is viewed from a second processor.
The programmable controller according to claim 5 or 6, wherein the programmable controller.

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