JPH036705A - Sequence controller - Google Patents

Abstract

PURPOSE:To shorten the program processing time and to improve the memory efficiency by using a NOP code production circuit which produces forcibly an instruction code and gives it to an MPU to minimize the executing time. CONSTITUTION:A NOP code generating circuit 3 produces a NOP instruction and sends it to a data bus 16 to minimize the executing time when a microprocessor MPU 1 fetches an operation code for an area where a sequence program 4 decided previously to a main program 2 of the MPU 1 is carried out. As a result, a one-step sequence instruction can be carried out within a time when the NOP instruction requiring the minimum executing time is carried out. Thus the high speed performance is secured. Furthermore the memory capacity can be saved because it is not required to store the NOP instruction into the program 2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a sequence controller, and particularly to a sequence controller that uses a general-purpose microprocessor (hereinafter referred to as MPU) to shorten the processing time of a sequence program and improve memory efficiency. The present invention relates to a sequence controller that can increase flexibility in program specifications.

[Conventional technology]

A sequence controller is a control device that sequentially advances operations according to predetermined conditions and sequences, and in particular, a controller that fully exhibits control functions according to the control purpose of numerically controlled machine tools, etc. is required.

By the way, the sequence controller performs operations in bytes or words in the MPU, and
The sequence logic operation circuit is configured to perform bit-by-bit logic operations in response to instructions from the sequence logic operation circuit. For this reason, the sequence controller requires a capacity of multiple bytes or multiple words in the sequence program to perform logical operations on a focus-by-focus basis, resulting in a problem that memory efficiency deteriorates and the processing time of the sequence program increases. Ta.

Therefore, the applicant of the present application has proposed a sequence controller in Japanese Patent Laid-Open No. 59-218510 in order to solve the above problem.

This sequence controller has specific commands, e.g.
An instruction to output the contents of the register of the PU to the sequence program area and an instruction to increment the contents of the register of the MPU after outputting that instruction are provided.
By using the register of the PU as a program counter for sequence processing, the purpose is to shorten the processing time of the sequence program by eliminating the need for means for adding up the program counter of the sequence program.

By the way, the sequence controller disclosed in Japanese Patent Application Laid-Open No. 59-218510 has a specific command in the program area of the MPU, for example, LDA (HL) ... (1) INCHL
...(2) LD A (HL) TNCHL JUMP XXXX...(3) is provided. Note that (1) means a read command to output the contents rA(HL)J of the address register of the MPU to the sequence program area, and (2) means an increment command to increment the address register HL by +1. However, (3) is a jump instruction provided in order to save memory capacity in the MPU program by alternately providing a large number of read instructions in (1) and increment instructions in (2). This means returning to the read command in (1).

[Problem that the invention is trying to solve]

By the way, in a conventional sequence controller, when the MPU processes a sequence program, (1) the MPU fetches the rLD A (HL) J instruction, (II) the MPU outputs the contents of the address register HL to the sequence program area. (III) MPU fetches the rlNcHL instruction, (rV) MPU outputs the contents of rINCHLJ to the sequence program area, and so on to execute a one-step sequence instruction in the sequence program area. (1) to (IV)
The above four processes had to be performed, and there was a problem with the high speed of the process.

Further, the conventional sequence controller must store a large number of read instructions and increment instructions alternately arranged in the main program area of the MPU, at least enough to process all sequence instructions. Also, when using jump instructions to save memory capacity, it is necessary to line up many read and increment instructions in order to make the execution time of the jump instruction sufficiently smaller than the execution time of read and increment instructions. There was a problem in that it needed to be arranged in program memory, requiring a large memory capacity.

From the above, it is an object of the present invention to use a general-purpose microprocessor to perform operations in byte or word units, to perform bit operations, which are the main task of a sequence controller, at high speed, and to improve memory efficiency. The purpose is to propose a sequence controller.

[Means to solve the problem]

In order to solve the above problems, the sequence controller of the present invention allocates a predetermined area of the main program 2 of the MPUI (see FIG. 1) as an area for executing the sequence program 4, and uses the program counter of the MPU 1 (hereinafter referred to as PC). ) on the PC of sequence program 4
When a predetermined area of the main program 2 is instructed by the PC of the MPU 1, a NOP code that forcibly generates and gives an instruction code (for example, a NOP instruction) that minimizes the execution time to the MPUI. It is composed of a generation circuit 3, and an interrupt means that performs sequence processing in combination with a PC and a sequence logic operation circuit 7, and connects an interrupt controller 10 to the MPU 1 to execute a functional instruction by interrupt processing. .

[Effect]

Since the PC of MPUI and the PC for executing sequence program 4 were shared, after MUPI sets the initial value (for example, rmmmm") to the PC, MPUI reads the NOP instruction in the opcode fetch cycle, and at the same time A sequence instruction of addresses is read and a logical operation is performed. After executing the sequence command, MPUI increments the PC by +1 and
Execute the instruction at the address indicated by .

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a Bronk diagram showing the main parts of the sequence controller of the present invention, FIGS. 2 and 3 are flowcharts explaining the contents of processing contact commands and function commands by sequence program counter processing according to the present invention, FIG. 4 is an explanatory diagram of sequence commands, FIG. 4(a) is an explanatory diagram of basic commands, FIG. 4(b) is an explanatory diagram of functional commands, and FIG. 5 is a ladder diagram of an embodiment of the present invention. Sequence diagram, Figure 6 is the 5th
FIG. 7 is an explanatory diagram of the machine code, and FIG. 8 is a timing chart of various signals issued by MPU commands.

In Figure 1, 1 is a general-purpose microprocessor (hereinafter referred to as M
(referred to as PtJ), 2 is the main program, 3 is a NOP code generation circuit that generates an instruction code (for example, a NOP instruction) with the minimum execution time, 4 is a sequence program as a data area, 5 is an address output by MPIJI An address decoder 6 distributes the sequence command to the main program 2 or the sequence program 4, and 6 determines whether the sequence command output from the sequence program 4 is a basic command (Fig. 4 (a)) or a functional command (Fig. 4 (b)). 7 is a sequence logic operation circuit that performs a 1-bit logic operation, 8 is an input section, 9 is an output section,
10 is an interrupt controller for calculations, etc., 11 is Hanwha, 12 is a data transmitter, 13 is a 16-bit address bus, 14 is a read signal output by MP (Jl), 15 is an AND gate, and 16 is an 8-bit data bus. ,
17 is a 16-bit data line for the sequence program, C30 is a select signal for selecting (lengthing) main program 2, C8I is a select signal for selecting sequence program 4, 18 is a 4-bit sequence instruction code line, 19 is an input/output address line which also includes a bit data line.

5CLK is a sequence clock line, 20 is an interrupt signal line for arithmetic processing, etc., and 21 is an interrupt signal for the MPU.

The MPU 1 is provided with means for allocating a predetermined area of the main program 2 of the MPtJ 1 as an area for executing the sequence program 4 and sharing the PC of the MPUI as the PC of the sequence program 4.

The main program 2 includes programs for processing contact commands and function commands shown in the flowcharts of FIGS. 2 and 3. Furthermore, the main program 2 also includes a program for processing instructions as shown in FIG.

The NOP code generation circuit 3 is a circuit that generates a NOP instruction and sends it to the data bus 16 when the MPUI fetches an operation code for an area for executing a sequence program 4 predetermined in the main program 2 of the MPUI. .

Next, the processing of contact commands by the sequence controller of the present invention will be explained according to the flowchart shown in FIG.

When the operation starts, the MPUI program counter PC
Initial value of PC of sequence program 4, for example, r
mmmmJ is set (step 101).

When r m m m m m J is set in the MPUI PC, MPtJl executes the instruction indicated by the address "rmmmm", but in the instruction part, for example, mmm
Since the NOP instruction like m NOP is sent from the NOP code generation circuit 3 via the data bus 16, the MPU 1 reads the NOP instruction in the operation code fetch cycle. Note that executing a NOP instruction means not performing any processing, so
At the same time as executing the NOP instruction, the MPUI reads the sequence instruction at address rmmmmJ of the sequence program 4, and performs logical operation processing based on the sequence instruction (step 102).

If the instruction indicated by address rmmmmJ is executed, MP
The UI automatically increments (+1) the PC. For example, suppose the PC is rmmm(m+1) (step 1
03). After incrementing PC, the MPUI repeats the process from step 102 onwards.

When the MPU fetches the opcode as described above,
The time to execute the instruction NOP that can be executed in the minimum time is 1
It is possible to demonstrate high-speed execution of step sequence commands.

Further, by providing the circuit 3 that generates a NOP instruction and sends it to the data bus 16 when the MPU fetches an operation code, it is not necessary to store the NOP instruction in the main program 2, so that memory can be saved.

Next, the operation when processing the ladder sequence program shown in the ladder sequence diagram of FIG. 5 will be explained in detail.

Note that the sequence program 4 (see Figure 1) includes the fifth
It is assumed that a ladder sequence program (ladder language) having the content shown in the ladder sequence diagram in the figure is stored in the memory in the form shown in FIG. Furthermore, this ladder language is actually stored in the form of executable contents as machine language (machine code) shown in FIG. That is, the upper 4 bits are a sequence instruction code, the next 3 bits are bit designation data, and the remaining 9 bits are input/output address data. Note that the bit designation data is -1'
This data is used to convert input/output data into 1-bit data for sequence processing when the IQ MPUI treats input/output data as parallel data.

By starting the sequence, the initial value rmmmmJ of the PC of the sequence program 4 is set in the PC of the MPUI.

When rmmmmJ is set in the MPUI PC, address rmmmmJ is output to the main program 2 via the address bus 13. Then, the MPUI causes the NOP code generation circuit 3 to generate a NOP command via the read signal 14, and the NOP command is generated.

Execute P command. On the other hand, address rmmmmJ is distributed by address decoder 5 and output to sequence program 4 via select signal C5l. That is, according to the timing chart of FIG. 8, the select signal CS for selecting the sequence program 4, ,
The read signal 14, sequence clock 5CLK, and sequence data line 17 generate a sequence command, that is, rRDo at memory address rmmmmJ in FIG.
A sequence command with the content "ol" will be output.

This sequence instruction is the mnemonic rRDj (see FIG. 6) which is the content of address 001. This sequence instruction is decoded through the instruction decoder 6, and if it indicates a basic instruction, the sequence instruction rRD, Output.

Then, the processing results of the sequence logic operation circuit 7 are outputted to the outside through the output section 9. This operation is performed between the falling edge and rising edge of the sequence clock 5CLK in FIG.

When the sequence instruction with the contents at memory address rmmmmJ is executed, the MPUI increments the PC by +1, making it PC4-PC+1. Then, PC becomes rmmm(m+1)J.

Once again, the MPUI executes the NOP command pointed to by the PC and sends the address rmmm to the sequence program 4.
Output (m+1)J. Then, sequence instruction rOROO4J is output. This sequence instruction rO
ROO4'' also indicates the basic command, so Figure 4(a)
Based on the function of , the previous result and address 004 are logically ORed. Is this behavior +? Sequence clock 5C as in 1.
This is performed between the falling edge and rising edge of LK.

Next, MPUI gives +1 to PC, and PC rmmm
(m+2)".

The sequence processing is executed by repeatedly performing the processing operations of the PC as described above.

By the way, if the above-mentioned instruction decoder 6 indicates a functional instruction (FIG. 4(b)) as a result of decoding, it is output to the interrupt controller 10 via the interrupt signal line 20. Then, the interrupt controller 10
An interrupt signal 21 is issued to the MPUI, and the MPUI enters interrupt processing.

That is, the MPUI reads from the sequence program 4 what kind of instruction the interrupt instruction (functional instruction) is, and starts its processing.

For example, suppose that it is sequence program 4 shown by (II) in the ladder sequence diagram of FIG. It is assumed that this sequence program 4 is included in the sequence program 4 as a ladder language in the form shown in (II) in FIG. The PC processing program shown in Figure 2 continuously counts up the contents of the PC and r
mmm(m+5)", the contents of this PC are transferred to the MPU
I is output to sequence program 4 and rmmm(m+
5) Read the contents of address j into the sequence logic operation circuit 7.

If MPUI increases PC by +1, rmmm(m+
6)", and when the MPUI outputs the contents of the PC to the sequence program 4, the contents of address rmmm(m+6)j indicate a function command, so interrupt signal 2 is output.
I is output and interrupt processing begins. That is, M.P.
The UI displays the contents of (A) at address rmmm(m+7)J when the content of address rmmmc m+6) is 005.
mmm(m-)-8) CB at address J].

Next, the processing of functional commands according to the present invention will be explained according to the flowchart of FIG.

As described above, the MPUI performs interrupt processing such as saving depending on the contents of the PC and registers (step 201).

It is determined whether the interrupt instruction from the sequence program 4 is an END instruction indicating the end of the sequence program 4 (step 202), and if it is an END instruction, the PC 4-m
mmm, step 203), and the process ends. On the other hand, if it is not an END command, the functional command is processed (step 204), the interrupt processing returns to normal sequence processing (step 205), and the interrupt processing ends.

In this way, the interrupt function of M PtJ 1 can be used to process sequence operations and tasks by software having the functions shown in Figure 4, and the flexibility of program functions can be demonstrated. can.

〔Effect of the invention〕

As explained above, according to the present invention, there is provided a means for allocating a predetermined area of a program of an MPU as an area for executing a sequence program, and a means for sharing a PC of the MPU as a PC of the sequence program; When instructed by the MPU
Sequence processing is performed by combining a NOP code generation circuit that forcibly generates and gives an instruction code that minimizes the execution time, a PC and a sequence logic operation circuit,
In addition, since it is configured with an interrupt controller connected to the MPU and an interrupt means that executes function instructions by interrupt processing, program processing time can be shortened, memory efficiency is improved, and interrupt processing is possible. By providing a program processing function, it is possible to provide a sequence controller with a high degree of flexibility in program specifications. As a result, it is possible to improve processing efficiency, processing capacity, etc. as a sequence controller for machine tools, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of the sequence controller of the present invention, FIGS. 2 and 3 are flow charts explaining the contents of sequence program counter processing according to the present invention, and FIG. 4 is an explanation of sequence instructions. Figure 4.
Figure (a) is an explanatory diagram of basic commands, Figure 4 (b) is an explanatory diagram of functional commands, Figure 5 is a ladder sequence diagram of an embodiment of the present invention, and Figure 6 is a coating of the state of Figure 5. Figure 7
The figure is an explanatory diagram of the machine code, and FIG. 8 is a timing chart of various signals issued by MPU commands. DESCRIPTION OF SYMBOLS 1...Microprocessor (MPU), 2...Main program, 3...NOP code generation circuit, 4...Sequence program, 5...Address decoder, 6...Instruction decoder, 7... - Sequence logic operation circuit, 8... Input section, 9... Output section, 10... Interrupt controller, 11... Buffer, 12... Data transmitter. Engraving of drawings Figure 1 Figure 6 Figure 5 Figure 9 Poor code bit data Human output address data Figure 8 Procedure amendment (method) Indication of incident Patent application No. 142647 λ Title of invention Sequence controller 3° correction Relationship with the patent case Patent applicant address: 1 Abiko, Abiko City, Chiba Name: Hitachi Seiki Co., Ltd. Representative: Teshima Gobe 4゜

Claims (1)

[Claims] In a sequence controller using a general-purpose microprocessor, a predetermined area within a program of the general-purpose microprocessor is allocated as an area for executing the sequence program, and a program counter of the general-purpose microprocessor is used for executing the sequence program. means for common use as a program counter of the general-purpose microprocessor; and when a predetermined area in the program is specified by the program counter of the general-purpose microprocessor, generating and providing an instruction code that forcibly minimizes the execution time to the general-purpose microprocessor. comprising an instruction code generation circuit, and an interrupt means that performs sequence processing in combination with the program counter and the sequence logic operation section, and connects an interrupt controller to the general-purpose microprocessor to execute a functional instruction through interrupt processing. A sequence controller featuring: