JPH02234227A - Misalignment processing system - Google Patents

Abstract

PURPOSE:To process the misalignment at a high speed by using an operand address generated by an adder and an action control signal of a processor undergone the extension of time due to the interruption caused by an instruction update control circuit to give an access to the next boundary of an external element. CONSTITUTION:If the misalignment is generated in the executing stage of an instruction which gives an access to an external element, an instruction update control circuit 6 interrupts the update of the instruction. At the same time, an adder 4 adds the fixed value to an operand address caused by the misalignment and produces an operand address of the next boundary. The next boundary of the external element receives an access by the generated operand address and the action control signal of a processor which undergone the extension of time due to the interruption caused by the circuit 6. Then the update of the instruction is restarted and the prefetched subsequent instructions are processed. Thus the processing time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a misalignment processing method in a computer.

[Prior Art] When an instruction to access an external element such as a main memory is for an area that straddles the boundary of the external element,
A misalignment has occurred. That is, assuming a 32-pinto processor and an external device in which the unit that can be written and read by one bus access starts from a 4-byte boundary, the lower two bits of the operand address of the external device access instruction are "1,""2J" or " 3” is 4
Byte access 3-byte access where the 2 bits are "2" or "3". 2 where the 2 bints are “3”
For byte accesses, misalignment occurs and two bus accesses are required to process the external element access command. In computers where such misalignment can occur,
It has a detection circuit that detects the occurrence of misalignment in hardware, and when the detection circuit detects the occurrence of misalignment, it performs two bus accesses and then executes the next instruction after the instruction that caused the misalignment. It has a built-in mechanism to handle misalignment so that the instructions that should originally be executed are executed. Conventionally, this type of misalignment processing has been realized by software control as shown in FIG.

FIG. 3 is a time chart of a processor that fetches, decodes, and executes instructions using pipeline methods; f. is an external element access instruction, rat is an instruction that branches depending on whether or not misalignment occurs, f8 is an instruction that should be executed next to instruction ``1,'' if misalignment does not occur, f is an instruction “Instruction to be executed next after 2, instruction f1.゜, f+z'. f+' is instruction I
ll is an instruction that is fetched due to misalignment. Furthermore, d and e are the decoding stages of the instruction r with the same subscript as that subscript.
Indicates an execution stage, and NOP is a no-operation.

Now, as shown in FIG. 3, the command r. ．． (If misalignment occurs in cycle TI3 where lt.ft is processed in that order and instruction fil is at the start of execution stage e, then the detection signal causes the instruction address of the misalignment processing routine to be set at decode stage adz of instruction fl2. is generated, and NOP is applied to the instruction r2 fetched at this time.Then, in the next cycle T., the misalignment processing instruction rat゜ is fetched according to the instruction address generated in the decode stage aCt. , In the following cycle 'I'Is, the return instruction fI!' to the main routine is fetched and the instruction f is decoded, and in the next cycle T14, the misalignment processing instruction fil゜ is executed and the second bus access is performed. That is, the next boundary of the external element accessed by instruction f. is accessed.

In addition, an instruction address for returning to the main routine is generated at the decode stage dCt' corresponding to the instruction r+z' in the same cycle Tl&, and in accordance with this, the main routine instruction r! Is it Fueso again? and execution returns to the main routine. Note that since there is a one-cycle gap between the fetch of the instruction ",2" and the re-fetch of the instruction f2, an operation is performed to fetch the instruction f1, ", which is a NOP instruction, by a dummy.

(Problems to be Solved by the Invention) Conventionally, the occurrence of misalignment has been dealt with by the above-mentioned processing, but: ■ branching to the misalignment processing routine and returning to the main routine using software-based IH; Therefore, it takes a long time to process.

■ The instruction (r
t) must be converted to NOP and re-fetched, which further increases the processing time. (2) It is necessary to create software in consideration of the occurrence of misalignment, such as by inserting the instruction r1 (2) into the main routine or preparing a misalignment processing routine.

There were problems such as.

The present invention solves these conventional problems, and its purpose is to speed up processing without having to consider the occurrence of misalignment in software, and without converting prefetched instructions to NOPs. The object of the present invention is to provide a misalignment processing method that can eliminate the problem.

[Means to solve the problem]

In order to achieve the above object, the misalignment processing method of the present invention provides an instruction update system that interrupts instruction update when a misalignment occurs in a processor that processes instruction decoding and execution in a pipeline method. 1
1 means, and an adder for generating an operand address by adding a fixed value to the operand address where the misalignment has occurred, and the time is extended by the operand address generated by the adder and the interruption by the instruction update control means. The next boundary of the external element is accessed using the processor's operation control signal, and the update of the instruction is then restarted. [Operation] When a misalignment occurs in the execution stage of an instruction that accesses an external element, the instruction update control means interrupts the update of the instruction, and the adder adds a certain value to the operand address where the misalignment occurred and performs the next operation. generates an operand address of the boundary of (becomes the same as the signal), the next houndry of the external element is accessed, after which instruction updating is resumed and the prefetched subsequent instruction is processed.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, in which hardware related to the misalignment processing method of the present invention is installed in a processor that processes fetching, decoding, and execution of instructions in a pipeline manner. Only the parts that do are shown. Each element included in the figure has the following configuration or function.

・2-1 selector 1 Inputs the address added from the signal line 100 and the address added from the adder 4 via the signal line 1o1, and selects the signal line 1
The held value of flag 3 added through 03 is the logical value “0゛”
It is a two-man power, one-output selector that outputs the address of the signal line 100 to the signal line 102 when the logical value is ``゛]'', and outputs the address of the signal line 101 to the signal line 102.

Misalignment detection circuit 2 Detects whether misalignment has occurred based on the address applied from the signal line 102, and when the occurrence of misalignment is detected, sets the level of the signal line 1o4 to a logical value of "1", for example.

・Flag 3 At the falling edge of the clock, the logic value on the signal line 105 connected to the output of the gate 10 is held, and the held logic value is sent to the 2-1 selector 1 and the gate 1 via the signal line 103.
Enter 0.

Gate 10 This is a gate for masking the output of the misalignment detection circuit 2. It is of course possible to incorporate this gate IO function into the misalignment detection circuit 2.・Address storage register 5 When an address is output from the 2-1 selector l to the bus 11 via the signal line 102, the address is sent to the signal line 106.
This is a register that is input through and held. - Bus 1l This is a bus that connects to external elements such as main memory (not shown) and transmits addresses for access. Adder 4 Adds the address supplied from address storage register 5 via signal line 107 and a constant value input via signal line 108, and adds the added value to 2 via signal line 101.
This is an adder that inputs to the -1 selector 1. Here, the constant value is a value commensurate with the difference between the operand address where the misalignment occurred and the operand address of the next boundary, and in the case of a 32-binotov processor, +4,1
When using a 6-bin fluoro sensor, it is +2.

- Instruction register 9 This is a register into which instructions received from an external element are input through the signal line 1o9.

-Decoder 8 This is a decoder that inputs and decodes the command from the command register 9 via the signal line 110.

- Control register 7 This is a register into which the output of the decoder 8 is input through the signal line 112, and the contents held therein are supplied to each section through the signal line 113 as an operation control signal for the processor.

・Instruction update control circuit 6 This is a circuit that manually inputs the output of the gate IO via the signal line 105, and outputs a signal to the signal 1i1114 to interrupt the update of the instruction when the level is the logical value "B".Signal line 114 When such a signal is output to the instruction register 9,
No new instructions are stored in the decoder 8, the decoder 8 holds the current output, and the control register 7 continues to output the processor operation control signal currently being output.

FIG. 2 is a time chart of FIG. 1, and the operation of the embodiment of FIG. 1 will be explained below according to this time chart. Note that in the second time, f1 is an external element access command, f. ．． f, is an instruction that is followed by instruction ``1'', d and e indicate the decode stage execution stage of instruction f with the same subscript as that subscript, and e1゜ is the instruction generated when misalignment occurs. This is the execution stage.

Now, as shown in FIG. 2, the instruction r+. rz. rs is quenched in that order and reaches cycle T, where the execution stage e1 of instruction f1 begins, the instruction f is sent from the control register 7.
An operation control signal according to the decoding result of instruction f1 is supplied to each part, and the operand address determined by the address information of the instruction f1 is output to the bus 1l via the signal line 100.1-1 selector l and the signal line 102. The area specified by the operand address of the external element is accessed. At this point, if the instruction f1 does not cause misalignment, that is, if the misalignment detection circuit 2 does not detect the occurrence of misalignment, the output of the gate 105 is the logical value "0", and the flag 3 is The logical value ``0'' remains. Furthermore, the instruction update control circuit 6 does not interrupt the update of instructions. Therefore, in the next cycle, the execution stage of the instruction f2 will start.

However, when a misalignment occurs at the execution stage e1 of the instruction r1, the output of the misalignment detection circuit Is2 that detects it becomes a logical value "1", and the value held in the flag 3 becomes a logical value "o゜" at that point. Therefore, as shown in FIG. 2, the output of the gate 10 becomes the logical value "P".As a result, the instruction update control circuit 6 interrupts the instruction update.Furthermore, the flag 3 is set at the next clock fall. The logical value "BI゜" is set. In the next cycle T4, the 2-1 select 1 selects the adder 4 side, so a certain value is added to the operand address of the instruction r and Nigagar held in the address storage register 5. Operand address is 2-1 selector l. It is output to bus 1l via signal 1102.

On the other hand, since the update of the instruction has been interrupted, the control register 7 continues to output the operation control signal related to the instruction f1. Therefore, in execution stage e,'' in cycle T4, an access to an external element is executed in the same way as instruction r1, and the access target becomes the boundary next to the boundary accessed by instruction rl. Misalignment is detected by the misalignment detection circuit 2, but since the output of the flag 3 is a logical value ``bi'', the output of the misalignment detection circuit 2 is masked by the gate IO, and the flag 3 is set again. In addition, the instruction update control circuit 6 does not interrupt the update of the instruction.As a result, in the next cycle T, the execution stage e2 of the instruction [2 is started.

As described above, in this embodiment, processing related to misalignment is executed by hardware. As can be seen by comparing FIG. 2 and FIG. 3, this embodiment has 4
Processing speed can be improved to the extent of Chronoku. (Effects of the Invention) As explained above, in the misalignment processing method of the present invention, when a misalignment occurs, a certain value is added to the operand address where the misalignment occurred, so that the second lot access is performed. In addition to generating such an operand address, the operation control signal of the brothenosa associated therewith is generated by extending the operation control signal that was generated based on the instruction that caused the misalignment every time, and accesses the next houndry of the external element,
Thereafter, the instruction update is restarted, and (1) Branching to the misalignment processing routine and returning to the main routine under software control are not necessary, so the processing time is shortened accordingly.

■ The instructions that were preempted by pipeline control are
Since there is no need to convert it into an OP, processing time is further shortened. ■ There is no need to create software that takes the occurrence of misalignment into account. You can obtain the following effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
The time chart shown in the figure and FIG. 3 are time charts of a conventional misalignment processing method. In the figure, ■...2-1 Selector 2... Misalignment detection circuit 3... Flag 4... Adder 5... Address storage register 6... Instruction update control circuit 7... Control IB register 8...Decoder 9...Instruction register 10...Gate 11...Bus patent applicant: 1 person other than NEC Corporation

Claims (1)

[Scope of Claims] In a processor that processes fetching, decoding, and executing instructions in a pipeline manner, an instruction update control means for interrupting instruction update when misalignment occurs; an adder that generates an operand address by adding values, and uses the operand address generated by the adder and the processor operation control signal whose time has been extended due to the interruption by the instruction update control means to perform the next operation of the external element. A misalignment processing method characterized in that a boundary is accessed and then updating of the instruction is restarted.