GB2080989A

GB2080989A - Improvements in or Relating to Data Processing Systems Including Cache Stores

Info

Publication number: GB2080989A
Application number: GB8101981A
Authority: GB
Original assignee: Honeywell Information Systems Italia SpA; Honeywell Information Systems Inc
Current assignee: Bull HN Information Systems Italia SpA; Bull HN Information Systems Inc
Priority date: 1977-11-22
Filing date: 1978-10-12
Publication date: 1982-02-10
Also published as: FR2425110A1; GB2080989B; FR2425110B1; GB2008817B; GB2008817A; DE2849448A1

Abstract

A data processing system includes a cache store to provide an interface with a main storage unit for a central processing unit. The central processing unit includes a microprogram control unit in addition to control circuits for establishing the sequencing of the processing unit during the execution of program instructions. Both the microprogram control unit and control circuits include means for generating pre-read commands to the cache store in conjunction with normal processing operations during the processing of certain types of instructions. In response to pre-read commands, the cache store, during predetermined points of the processing of each such instruction, fetches information which is required by such instruction at a later point in the processing thereof.

Description

1 GB 2 080 989 A 1

SPECIFICATION

Improvements in or relating to data processing systems including cache stores The present invention relates to data processing systems and more particularly to systems which include a type of prefetch capability.

In large scale and multiprocessor systems, processor performance has been improved by providing a cache store or high-speed buffer storage unit between the system's large main storage unit or backing store and the central processing unit. To further increase the system performance, prior art data processing systems have also included a prefetched capability in which a next sequential line of data is fetched by the cache store automatically after supplying the line of data requested by the central processing unit.

A disadvantage of the above systems was that such systems did not take into account conditions which alter the basic philosophy that the next sequential line should be prefetched immediately from main store. To overcome the disadvangate mentioned, one system has included algorithms for prefetching a next sequential line from main storage to the highspeed buffer and algorithms for replacement of existing lines in the high-speed buffer which maybe dynamically modified relative to the 15 type of program being executed by the use of a system console unit. More particularly, the system includes an operating state register which corresponds to the variables of the prefetch control algorithm. Such variables are based upon references to preceding lines being requested.

While the above arrangement provides for variation as to accessing a next sequential line of data before a request is made, it has the disadvantages of basing the prefetch request upon an arbitrary 20 circumstance relating to the particular byte or portion of a line being referenced by a previous request.

While this is advantageous in certain types of operations, it could result in decreased performance in other cases. More specifically, automatic accesses can increase memory congestion.

Accordingly, it is a primary object of the present invention to provide a data processing system with an improved type of prefetch capability. Such a system comprises:

an addressable main store having a plurality of word locations for storing information including data and instructions; high speed buffer storage means coupled to said main store for providing immediate access and to data and instructions fetched from said main store, said buffer storage means having a plurality of addressable locations, and said buffer storage means including control means for fetching information 30 from said main store; and processing means coupled to said high speed buffer storage means, said processing means for processing instructions, each instruction including an operation code portion, said processing means including control means for generating signals including memory commands required for the execution of said instructions, said control means including decoder circuit means responsive to signals indicative 35 of an operation code portion coded to specify a predetermined class of instruction to generate memory command signals accompanied by coded command signals specifying a predetermined type of buffer storage read operation and said buffer storage control means being operative in response to said coded command signals to generate signals for forwarding said memory command signals to said main store to fetch the data 40 specified by said command signals when said data is not stored in said buffer storage means, such data being fetched for storage in advance of its required use in said buffer storage means without interrupting the operation of said processing means facilitating the execution of each predetermined class of instruction.

In a preferred embodiment of the present invention a data processing system includes a high- 45 speed buffer or cache unit which couples to at least one central processing unit and to a main store. The processing unit operates under microprogram control and includes control logic circuits for establishing the different cycles of operation for the processing unit. Additionally, certain microinstruction words accessed during the execution of certain types of instructions are coded to specify a pre-read operation.

Similarly, the control logic circuits also include means for generating a pre-read command to the cache 50 unit for such instruction types. ' The cache unit in response to each pre-read command is operative to fetch from main store a block of data specified by the instruction being executed when the data being requested has not been previously stored in the cache unit. In operation, during the execution of the certain types of program instructions, either the microprogram control or the control logic circuits, generates pre-read commands to the cache unit at predetermined points during the execution of such instructions. In this manner, the data normally required at a later point in the execution of an instruction can be fetched in advance from main store and stored in cache while other operations pertaining to that instruction are being carried out.

The cache unit has a plurality of word locations arranged into a number of groups of blocks of word locations, a data directory including a plurality of locations corresponding in number to the number of groups and a control directory including a plurality of multibit locations corresponding in number to the number of blocks. The system further includes an input buffer for storing a plurality of 2 GB 2 080 989 A 2 memory commands, generated by the data processing unit and control logic circuits. The control logic circuits include decoder circuit means coupled to the buffer and to said control directory.

The decoder circuit means is operative to selectively set one of bit locations identified by the memory command to a predetermined state. This occurs when the command calls for an operation which cannot be completed immediately but which must remain outstanding for a certain minimum length of time. During the processing of subsequently received commands, the contents of the control directory are accessed. When a next memory command is received which specifies information requested by previous commands the contents of control directory bit location indicate whether the operation which has been initiated is still pending or outstanding. When the contents indicate that the operation is outstanding, the control circuits signal the processor to stop its operation in the cases where the information requested is needed immediately. The control circuits further include control sequencing circuits. When all of the information required to complete the pending operation has been stored in the cache unit, the control sequencing circuits automatically re-execute such next command and enable the processor to continue operation.

By referencing the contents of the control directory during the normal command processing in. 15.

parallel with the data directory, the system is able to detect the presence of conflicting commands and prevent the issuance of duplicate commands. Additionally, the arrangement permits the processing of certain commands generated by the processor which do not necessitate stopping processor operation.

Further, the arrangement of the present invention provides states as to the completion of those operations being processed.

Arrangements according to the invention will now be described by way of example and with reference to the accompanying drawings, in which:- Figure 1 illustrates in block form a system employing the principles of the present invention.

Figure 2 shows in block diagram form the host processor 700 and the cache memory 750 of Figure 1.

Figure 3a to 3i show in greater detail the different blocks of Figure 2.

Figure 4 shows in greater detail the cache unit 750 of Figure 2i.

Figures 5a to 5e show the lines which comprise different ones of the interfaces of Figure 1.

Figure 6b illustrates the format of the microinstruction words of the execution control store of Figures 2 and 3.

Figure 7 illustrates the format and coding of an edit instruction used in explaining the operation of the present invention.

Figure 8 is a diagram used to illustrate the operation of the system of Figures 3a through 3j and 4 constructed in accordance with the principles of the present invention.

Figure 9 is a diagram which sets forth the various cycles required for processing the instruction of 35 Figure 8 in accordance with the present invention.

Figure 10 is a flow chart illustrating the sequencing of processor 700 required for processing the instruction of Figure 8 in accordance with the present invention.

Figure 11 is a state diagram used in describing the hardware sequencing of the apparatus of the present invention.

Figure 12 is a flow diagram used in explaining the operation of the preferred embodiment.' Figure 13a to 13d illustrate the formats of certain types of instructions used in describing the operation of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT 45 General Description

As seen from Figure 1, the system which incorporates the principles of the present invention 45 includes at least 1 input/output processor (IOPP) 200, a system interface unit (SIU) 100, a high-speed multiplexer (HSMX) 300, a low-speed multiplexer (LSMX) 400, a host processor 700, a cache memory 750, at least one memory module corresponding to a local memory module 500, and at least one memory module corresponding to a remote memory module 800. Different ones of these modules 50 connect to one of a number of ports of the system interface unit 100 through a plurality of lines of different types of interfaces 600 through 603. More specifically, the input/output processor 200, the cache memory 750, and the high-speed multiplexer 300 connect to ports G, E and A, respectively, while the low-speed multiplexer 400, local memory module 500, and main memory module 800 connect to ports J, LMO and RMO, respectively. The host processor 700 connects to the cache memory 750. 55 The input/output system of Figure 1 can be viewed as including a number of -active modules-, passive modulesand -Memory modules---. The IOP processor 200, host processor 700 and high speed multiplexer 300 serve as active modules in that each has the ability to issue commands. The active modules normally connect to ports A through H while the host processor 700 connects to port E through the cache unit 750 via interfaces 604 and 600. A plurality of passive modules are connected to 60 three ports J, K and L. These modules correspond to the low-speed multiplexer 400 and the system interface unit 100 and are units capable of intercepting and executing commands applied to the lines of interface 601 as described herein. The last group of modules constitutes local memory modules, and 3 GB 2 080 989 A -3 main memory modules capable of executing two different types of commands applied to the lines of interface 603.

The input/output system of Figure 1 normally functions as an input/output subsystem responsive to inputloutput instructions issued by the host processor 700. Ports E and F include interfaces for enabling connection of either multiplexer or procesor modules of Figure 1. These interfaces are described in greater detail herein.

For the purpose of the present invention, host processor 700 is conventional in design and may take the form of these units described in U.S. Patent No. 3,413,613. In the preferred embodiment, the input/output processor 200 initiates and terminates channel programs required for the execution of input/output instructions, processes interrupt requests received from the system interface unit 100, and 10 directly controls unit record peripheral devices coupled to low-speed multiplexer 400. The processor 200 connects to port G via the data interface 600 and interrupt interface 602.

The lowspeed multiplexer 400, for the purposes of the present invention can be considered conventional in design, provides for attachment of lowspeed peripheral devices via peripheral adapters, each of which couples to the lines of a device adapter interface (DAI). The interface and adapter may 15 take the form of those units described in U.S. Patent No. 3,742,457, which is assigned to the assignee of the present invention. The low-speed devices include card readers, card punches and printers. As seen from Figure 1, the multiplexer 400 connects to port J via the programmable interface 601.

The high-speed multiplexer 300 directly controls transfers between the groups of disk devices and tape devices 309 through 312, which connect to different ones of the channel adapters 303 to 306. 20 Each of the channel controller adapters 303 through 306 which can connect up to a maximum of 16 devices to a different one of the channel ports 0 through 3 via the interface lines of a channel adapter interface (CAI) 300-1. The high-speed multiplexer 300 connects to port A corresponding to a data interface 600, a programmable interface 601 and an interrupt interface 602.

For the purposes of the present invention, each of the channel controller adapters 302 through 25 305 may be considered in design and take the form of controller adapters described in the aforementioned U.S. Patent No. 3,742,457.

System Interfaces Before describing in detail the processor 700 and cache unit 750, constructed in accordance with princ 1 iples of the present invention, each of the interfaces 600 through 604 discussed previously will 30 now be described with reference to Figures Sa through 5e.

Referring first to Figure 5a, it is seen that this figure discloses the lines which constitute the data interface 600 which is one of the interfaces which provides for exchange of information between an active module and the system interface unit 100. Exchange is accomplished by controlling the logical states of various signal lines in accordance with pre-established rules implemented through a sequence 35 of signals termed a "dialog".

As seen from Figure 5a, the interface includes an active output port request line (AOPR), a plurality of data to SIU lines WS 00-DTS 35, PO-P3), a plurality of steering data to SIU lines (SIDTS 0-6, P), an active request accepted line (ARA), an accept read data line (ARDA), a plurality of data from SM bus lines (DFS 00-35, PO-P3), a plurality of multiport identifier from SIU lines (MIFS 0-3, P), a double 40 precision from SM line (DPFS), and an accept status line (AST). The description of the interface lines are given in greater detail in the section to follow.

4 GB 2 080 989 A 4 Designation DATA INTERFACE LINES Description

AOPR DTS 00-35, PO-P3 S DTS 0-6, P MITS 0-3, P ARA ARDA DFS 00-35, PO-P3 MIFS 0-3, P DPFS AST The active output port request line is a unidirectional line which extends from each of the active modules to the SIU 100. When set, this line signals the SIU that the module requests a transfer path over which commands or data are to be transmitted. The data path lines are a four byte wide unidirectional path (four to 10 bit bytes) that.extends between each of the active modules and the SIU and are used for transferring commands or data from each active module to the SIU 100 The steering data to SIU lines extend from each active module to the 10 SIU 100. These lines are used to apply steering control information to the SIU 100 when the line AOPR is set. Steering control information consists of seven bits and a parity bit which are coded as follows: (a) The state of bit 0 indicates the type of command applied to the DTS lines (whether the command is a programmable interface or a memory 15 command).

(b) Bits 1-4 are coded to indicate which one of the modules is to receive and interpret the memory command (commands are interpreted only by memory modules and programmable interface commands shall be interpreted by ail modules except input/output 20 processor 200).

(c) The state of bit 5 indicates whether one or two words of the command information is to be transferred between the requesting active module and the designated receiving module (one word specifies a single precision transfer and two words specifies a double 25 precision transfer).

(d) The state of bit 6 indicates the direction of transfer between the requesting module and the designated receiver module.

(e) Bit P is a parity bit generated by the requesting active module which is checked by apparatus included within the SM 100.

The four multiport identifier to SIU lines extend from active module to the SIU 100. These lines are coded to indicate which subchannel or port within an active module caused the setting of line AOPR.

The active request accepted line extends from the SIU 100 to each of the active modules. This line is set to indicate that the designated receiving module has accepted the active module's request which allows the active module to remove the requested information from the data interface lines.

The accept read data line extends from the SIU to each of the active modules. This line is set by the SIU 100 to indicate to the active module that it is.to accept the previously requested data from a designated module.

The data from SIU lines are another set of data path lines which are a four byte wide unidirectional path (four 10 bit bytes) which extends from the SM to each active module. These sets of lines are used by the 45 SIU 100 to convey read type data to a designated one of the active modules.

The four multiport identifier lines plus odd parity line extend from the SIU 100 to each of the active,modules. These lines are coded to indicate which port or subchannel on the active module is to accept 50 the data of a previous read operation from the SM 100.

The double precision from SIU line extends from the SIU to each of the active modules. The state of this line indicates whether one or two words of read data are to be accepted by the active module to complete a transfer (read command).

The accept status line extends from the SIU 100 to each active module. The state of this line which is mutually exclusive of line ARDA, signals the active module that it should accept status information applied to the DFS lines.

GB 2 080 989 A 5 Tile lines of tile programmable interface 601 shown in Figure 5b provide for transfer of command information from an active module and a designated module. The transfer is accomplished by controlling the logic of states of the various signal lines in accordance with pre-established rules implemented through a sequence of signals termed dialog. The programmable interface includes an accept programmable interface command line (APC), a plurality of programmable interface data from SIU lines (PDFS 00-35, PO-P3), a programmable interface ready line (PIR), a read data transfer request line (RDTR), a plurality of programmable interface data to SILI lines (PDTS 00-35, PO-P3) and a read data accepted line (RDAA). The description of the interface lines are given in greater detail herein.

PROGRAMMABLE INTERFACE LINES 10 Designation Description

APC The accept programmable interface command line extends from the SIU 100 to each receiving module. When set, this line signals the module that command information has been applied to the PUS lines of the interface by the SIL) and is to be accepted by the module.

PDFS 00-35, PO-P3 The programmable interface data from SIU lines are a four byte wide 15 unidirectional path (four 10 bit bytes) that extend from the SIU 100 to each module. These lines apply programmable interface information from the system interface unit to a designated receiving module.

PIR The programmable interface ready line extends from each module to the SIU. When set, this line indicates that the module is ready to 20 accept a command to be applied to line PIDFS.

PDTS 00-35, PO-P3 The programmable interface data to the SIU lines are a four byte wide unidirectional path (four 10 bit bytes) that extends from each module to the SIU 100. These lines are used to transfer programmable interface information to the SIU. 25 RDTR The read data transfer request line extends from each module connected to the programmable interface to the SIU 100. When set, this line indicates that the previously requested read data is available for transfer to a module and has been applied to the lines PDTS by the module. 30 RDAA The read data accepted line extends from the SIU 100 to each module.

When set, the line indicates to the module that the data applied to the lines PDTS has been accepted and that the module may remove the information from these lines.

A further interface is the interrupt interface 602 of Figure 5c which provides for interrupt 35 processing by the input/output processor 200. That is, the interface enables the transfer of interrupt information by an active module to the SIU 100 as well as the transfer of interrupt information by the SIU 100 to the input/output processor 200 for processing. Similar to the other inter-faces, the transfer of interrupt requests is accomplished by controlling the logical states of the various signal lines in accordance with pre-established rules implemented through a sequence of signals termed---dialog---. 40 The interface includes an interrupt request line (M), a plurality of interrupt data lines (IDA 00-11, PO-P1) and a plurality of interrupt multiport identifier lines (IMID 00- 03) for modules connected to ports A through L. For modules connected to ports G and H, the interrupt interface further includes a level zero present line (LZP), a higher level interrupt present line (HUP), an interrupt data request line 0DR), a release line (RLS) and a plurality of active interrupt level fines (AIL 0-2). As seen from Figure 45 5c, the interrupt interface ports G and H do not include an interrupt multiport identifier line. The description of the interrupt interface lines are given in greater detail herein.

6 GB 2 080 989 A 6 Designation INTERRUPT INTERFACE LINES Description

IR IDA 0-3, PO 5IDA4-11,P1 IMID 00-03 LZP HLiP IDR AIL 0-2 The interrupt request line extends from each module to the SIU 100. When set, this line indicates to the SIU that it requires service. The interrupt data lines extend from an active module to the SIU 100. These lines are coded to contain control information required to be transferred to the input/output processor when an interrup request has been accepted by the processor. These bits are coded as follows: (a) The state of bit 0 specifies to the SIU 100 which of the two processors (i.e., processor number) is to process the interrupt request.

(b) Bits 1-3 are coded to indicate the priority or level number of the 10 interrupt request to the SIU 100.

(c) Bit PO is a parity bit for bits 0-3.

(d) Bits 4-8 are coded to provide a portion of an address required to be generated by the inputloutput processor 200 for referencing the correct procedure for processing the interrupt (i.e., an interrupt control 15 block number ICBN).

(e) Bit P 1 is a parity bit for bits 4-11.

The interrupt multiport identifier lines extend from each active module to the SIU 100. These lines are coded to identify which specific subchannei of the active module has requested interrupt service. 20 The level zero present line extends from the SIU 100 to the input/output processor 200. When set, this line indicates that there is a highest priority (level 0 interrupt) request being directed to the processor 200 by the SIU 100.

The higher level interrupt present line extends from the SIU to the inputloutput processor. When set, this line indicates that there is an interrupt request having a higher level or priority than the procedure or process being executed by the processor 200.

The interrupt data request line extends from the input/output processor 200 to the SIU 100. When set, this line indicates that interrupt data is to be sent to the processor on lines DFS by the SIU 100.

The release line extends from the input/output processor 200 to the SIU 100. This line when set indicates that the processor 200 has completed execution of the current procedure.

The active interrupt level lines extend from the SIU to the input/output processor 200. These lines are coded to designate the interrupt level n umber of the procedure being executed by the processor 200.

A next set of interface lines utilized by certain ones of the modules of Figure 1 corresponds to the local memory interface lines of Figure 5d. The local memory interface 603 provides for exchanging information between local memory 500 and the modules of the system. The exchange is accomplished by controlling logical states of the various signal interface lines in accordance with pre-established rules implemented through a sequence of signals termed a---dialog---. The local memory inter-face includes a plurality of data to memory lines (DTM 00-35, PO-P3), a plurality of request identifier to memory lines (RITM 0-7, PO-P 1), a plurality of specification lines to memory lines (SLTM 0-3, P), 45 an accept P 1 command line (APC), an accept ZAC command line (AZC), a P 1 interface ready fine (PIR), a ZAC interface ready line (ZIR), a read data transfer request line (RDTR), a plurality of data from memory lines (DFM 00-35, PO-P3), a plurality of request identifier from memory lines (RIFM 0-7, PO-P 1), a double precision from memory lines (DPFM), a QUAD line, a read data accepted line (RDAA) and a system clock line (SYS-CLK).

Memory and programmable interface commands are transferred out of the same physical data lines of the interface. The interface does not include a set of lines for processing interrupt requests and therefore the modules connected to the local memory by the SIU 100 cannot directly cause a memory interrupt. The description of the local memory interface lines are given in greater detail herein.

7 GB 2 080 989 A 7 Designation LOCAL MEMORY INTERFACE LINES Description

DTM 00-35, PO-P3 The data path lines constitute a four byte wide unidirectional path (36 information lines and four odd parity lines) that extends from the SIU to the local memory 500. These lines are used to transfer memory or programmable interface commands to the local memory 500. 5 RITM 0-3, PO The requestor identifier to memory lines constitute two groups of four RITM 4-7, P 1 lines which extend from the SIU 100 to the local memory 500. These lines are coded to convey information to the local memory identifying the module which initiated the command and are used to return the data requested to the proper module. 10 SLTM 0-3, P The specification lines to memory extend from the SIU 100 to the local memory 500 and include two port number selection lines, a read/write to memory line, a double precision to memory line and a parity line.

The information signals applied to these lines are coded as follows.

(a) Bits 0-1 are port number selection bits coded to specify which 15 port or subchannel within the attached module is to receive or interpret the memory command sent to the module.

(b) Bit 2 is a read/write to memory bit which is included in the steering control information received from the active module which is forwarded by the SIU to the local memory 500 when a new command 20 is sent to the memory by the SIU 100. The state of this bit indicates the direction of data transfer.

(c) Bit 3 is a double precision to memory bit coded to specify the amount of data to be transferred. It is also included in the steering control information provided by the active module which is forwarded 25 to the local memory module 500 by the SIU 100 when a new command is sent to the memory module.

AZC APC PIR/ZIR RDTR DFM 00-35, PO-P3 RIFM 0-3, PO RIFM 4-7, P 1 DPFM and QUAD The accept ZAC command line extends from the SIU 100 to the local memory module 500, When set, this line signals the local memory module 500 to accept the ZAC command and control information 30 applied to the other lines by the SIU 100. The setting of this interface line is mutually exclusive with the accept P 'I command interface line. The accept programmable interface command line, as described in connection

with the programmable interface, extends from the SIU to the local memory module 500. When set, this line indicates that the command information applied to the lines DTIV1 is to be accepted by the local memory module 500.

The programmable interface ready line/ZAC interface ready line extends from the local memory module 500 to the SIU 100. When set, each line signals the SIU 100 that the local memory module 500 is 40 capable of accepting a programmable interface (P0/memory (ZAC) command.

The read data transfer request line extends from the local memory module 500 to the SIU 100. This line when set indicates that the read type data previously requested by a ZAC or PI command is available 45 along the necessary control information to be sent to the module requesting the data.

The data from memory)ines are a four byte wide unidirectional bus which extends from the local memory module 500 to the SIU 100.

These lines are used to return read requested type data to an active 50 module via the SIU 100.

The two groups of requestor identifier from memory lines extend from the local memory module 500 to the SIU 100. These lines are coded for directing the read data back from module 500 to the requesting module.

The double precision from memory line and QUAD line extend from the local memory module 500 to the SIU 100. These lines are coded to indicate the number of words to be transferred via the SIU 100 to the requesting module during read data transfer request time interval.

8 GB 2 080 989 A 8 Designation INTERRUPT INTERFACE LINES (cont'd) Description

These lines are coded as follows:

QUAD DPFM 0 0 one word, single precision 0 1 two words, double precision 1 X (don't care) four words DSD RDAA SYS-CLK The read data/status identifier line extends from the local memory module 500 to the SIU. The state of this line signals the SIU 100 whether the information applied to the lines DFM is read data or status 10 information when line RDTR is set. When set, the line indicates status information of one or two words (QUAD = 0) is being transferred.

When reset to a binary ZERO, the line signals that up to four words of data are being transferred, the number being specified by the coding of lines QUAD and DP17M.

The read data accepted line as mentioned in connection with the programmable terminal extends from the SIU 100 to the local memory module. When set, this line signals the memory module that the data applied on the interface lines by the local memory module has been accepted and that the local memory module may remove data from 20 these lines.

The system clock line is a line which extends from the SIU 100 to each m odule of the system. This line is connected to a clock source included within the input/output processor 200 to synchronize the operations of each memory module from a common system clock source.

A last set of interface lines utilized as an internal interface between the cache unit 750 and central processor 700 corresponds to the cache/CPU interface lines of Figure 5e. The interface 604 provides for exchanging information apd control signals between the processor 700 and the cache unit 750. The exchange is accomplished by controlling the logical states of the various signal interface lines. The cache/CPU interface includes a plurality of data to processor lines (M1 0- 35, PO-P3), a plurality ZAC 30 and write data lines (ZADO 0-23, RADO 24-35, PO-P3), a processor request signal line PREQ-CAC), a plurality of cache command lines (DMEM 0-3), a hold cache line (HOLD-C-CU), a cancel line (CANCEL-C), a flush line (CAC-FLUSH), a read request line (RD- EVEN), a read instruction buffer line (RD-IBUR a read data buffer line (DRDS), an initialization pointer line (INIT-IBUF), a plurality of instruction lines (ZIBO-35), a plurality of address pointer lines (ASFA-M32-33), a 35 control line (DSZ), a read 1-buffer data line (RD-IBUF/ZDI), a plurality of zone bit lines (DZD 00-3), a bypass cache line (BYP-CAC), a write signal line (WRT-SGN), an instruction buffer empty line (IBUF-EMPTY), an instruction buffer ready line (iBUF-RDY), an instruction buffer full line (IBUF-FULL), a CP stop line (CP-STOP), and a CP control line (DATA-RECOV).

Instructions, cache commands and data are forwarded to the cache unit 750 via different ones of 40 these lines. Additionally, the operation of the processor 700 is enabled or disabled by certain ones of these lines as explained herein. The description of the CP/cache interface lines are given in greater detail herein.

---1 -:

1, - 1 - 9 GB 2 080 989 A 9 Designation CP/CACHE INTERFACE LINES Description

DREQ-CAC DMEM 0, 1, 2, 3 This line extends from the processor 700 to cache unit 750. When the DREQ- CAC is set to a binary ONE, a ZAC command is transferred to the cache 750. In the case of a write ZAC command, write data words are transferred in the one or two cycles following the ZAC command and data words are sent from the processor 700 through the cache 750 without modification, to the SIU 100. These lines extend from the processor 700 to cache 750. These lines are coded to designate the command that the cache 750 is to execute. 10 The coding is as follows: DMEM = 0000 no op No action is taken and no cache request is generated. DMEM = 000 1 Direct The direct command enables the processor 700 to perform a direct transfer of an operand value without action on the 15 part of the cache 750. Hence, no cache request is generated by this type of command. DMEM = 00 10 0-3 -Address Wraparound Command (ADD-WRAP) The address wraparound command is executed in 2 cycles. At the start of the first cycle, data and command information is 20 transferred to the cache 750. The processor 700 is then turned off before the next clock interval. During the second cycle, the processor is turned on and at the end of the cycle the data given to it is made available to the processor 700.

DMEM = 0 100 0-3 - Load Instruction Buffer Instruction Fetch 1 25 (LD-IBUF-IF1) The load instruction buffer command is executed in one cycle. At the start of the cycle, address and command information is transferred to the cache 750. At the end of the cycle, the block specified by the address is written into the instruction buffer at a previously designated instruction buffer address, and the addressed 30 word is transferred to the processor 700 via the M1 lines 0-35.

DMEM = 0 10 10-3 - L oad Instruction Buffer Instruction Fetch 2 (LD-IBUF-IF2) The load instruction buffer command is executed in one cycle. At the start of the cycle, address and command information is transferred to the cache 750. At the end of the cycle, the block specified by the address is written into the instruction buffer at the previously designated instruction buffer address.

DMEM = 0110 -Load Quad The load quad is executed in one cycle. Same as IF2 but data goes to another portion of the 1 Buffer.

DMEM = 0 1110-3 -Preread (PR-RD) The preread command is executed in a variable number of cycles with a minimum of one.

At the start of the first cycle, address and command information are transferred to cache 750. During the first cycle, when the address specified is that of a block which is in the cache 750, the preread 45 operation terminates and no other action is taken. If the addressed block is not in the cache 750, then at the end of the first cycle, the request is transferred to the main memory. When the requested block has been read from main memory, the data is stored in the cache 750.

DMEM = 1000 0-3 -Read Single (RD-SNG) The read single 50 command is executed in one cycle. At the start of the cycle, address and command information are given to the cache 750 and at the end of the cycle the data made available to processor 700.

DMEM = 100 10-3 - Read Clear (RD-CLR) The read clear command is executed in a variable number of cycles with a minimum of 9. At the start of the first cycle, address and command information are transferred to the main memory, and the processor is turned off.

During the second cycle, when the addressed word is contained in a cache the block containing the word is fetched from the cache 750.

When the requested word has been read from main memory and transferred to the cache 750, then the processor is turned on.

DMEM = 1010 0-3 -ReadDouble Odd(RD-DBL-0) (line DSZ is GB 2 080 989 A 10 Designation CP/CACHE INTERFACE LINES (cont'd) Description

HOLD-C-CU CANCEL-C CAC-FLUSH RD-EVEN ZADO 0-23 ' RADO 24-35 60 PO-P3 a binary ZERO). The read double odd command is executed in two cycles. At the start of the first cycle, address and command information are transferred to the cache 750. At the end of the first 5 cycle, the word at the odd address is made available to the processor 700. At the end of the second cycle, the word at the even address is made available to the processor.

DMEM = 10 10 0-3 - Read Double Even (RD-DBL-E) (line DSZ is a binary ONE) The read double even command is executed in two 10 cycles. At the start of the first cycle, address and command information are transferred to cache 750. At the end of the first cycle the word at the even address is made available to the processor 700.

At the end of the second cycle, the word at the odd address is made available to the processor 700.

DMEM = 1011 0-3 - ReadRemote (RD-RMT) The read remote command is executed in a variable number of cycles, with a minimum of 10. At the start of the first cycle, address and command information are transferred to cache 750. At the end of the first cycle, the request is transferred to the main memory and the processor 700 is turned off. When the requested word pair has been fetched from memory, processor 700 is turned on and the data is made available to it.

DMEM = 1100 0-3 - Write Single MR T-SNO The write single command is executed in two cycles. At the start of the 25 first cycle, address and command information is transferred to the cache 750. At the start of the second cycle, the data is transferred to the cache 750. During the second cycle, the data is written into the cache 750, if the block which contains the addressed word is stored in the cache 750. During the end of the second cycle, the write request 30 and the data is transferred to the main memory.

DMEM = 1110 0-3 - Write Double (WR T-DBL) The write double command is executed in three cycles. At the start of the first cycle, address and command information are transferred to the cache 750. At the start of the second (third) cycle the even (odd) 35 data word is transferred to the cache 750. During the third cycle, the data is written into the cache, if the block which contains the addressed word pair is stored in the cache 750. At the end of the third cycle, the write request and both data words will have been passed on to the main memory.

DMEM = 11110-3 - Write Remote (WRT-RMT) The write remote command is executed in three cycles. At the start of the first cycle, address and command information are transferred to the cache 750. At the end of the first cycle, the request is transferred to the main memory. During the next two cycles, the 2 data words are 45 transferred to the cache 750 which transfers same to main memory.

This line extends from processor 700 to cache 750. When set to a binary ONE, this control signal specifies that the cache 750 is to assume a HOLD state for requests or data transfers.

This line extends from procesbor 700 to cache 750. When set to a 50 binary ONE, this control signal aborts any request made to cache 750.

This line extends from processor 700 to cache 750. When set to a binary ONE, it starts a flush of the cache 750.

This line extends from processor 700 to cache 750. When the cache makes a double word request to the SIU, the even word is saved in a special register. When RD-EVEN line is set to a binary ONE, the contents of this register is gated onto the M1 lines.

These 40 unidirectional lines extend from processor 700 to cache 750.

The lines are used to transfer ZAC command and write data words to the cache 750.

i 1 11 GB 2 080 989 A.1-1 Designation RD-IBUF DZD 0-3 BYP-CAC WRT-SGN ASFA 32-33 CP/CACHE INTERFACE LINES (cont'd.) Description

This line extends from the processor 700 to cache 750. When set to a binary ONE, the line causes an instruction buffer out pointer to increment for processing a next instruction in accordance with the state of a line DRDB as follows. These four lines extend from processor 700 to cache 750. These lines transfer odd word zone bit signals for write double commands. This line extends from processor 700 to cache 750. When set to a binary ONE, this line causes the cache 750 to request data words from 10 main memory for read type instructions. This line extends from the cache 750 to processor 700. It is used to signal the processor 700 during write commands that the cache 750 has completed the transfer of ZAC commands and data words of the SIL1 100. These two lines extend from processor 700 to cache 750. These lines are coded to specify the next word of a block stored in the 1 buffer to be read out to the processor 700 when the 1 buffer is initialized under hardware control via the INIT IBUF line.

MT-IBUF The initialize instruction buffer command is executed in one cycle. At 20 the end of the cycle, a buffer in pointer is reset to ZEROS and the buffer out pointer is loaded - with an initial value.

MZ1 This line extends from the processor 750 to cache 750. The state of this line specifies to cache 750 the order in which words are to be sent to the processor 700 when a read double command is performed. 25 DRD13100 This line extends from the processor 700 to cache 750. It is used as the most significant bit of the 1 Buffer read address.

RD-IBUIF/M1 This line extends from processor 700 to cache 750. It causes the cache 750 to apply the data on the ZI B lines to the M1 lines.

M1 0-05 These 40 unidirectional Hnes extend from cache 750 to processor 700. 30 PO' P1, P21 P3 They apply data from the cache 750 to the processor 700.

ZIB 0-35 These 40 unidirectional lines extend from cache 750 to processor 700.

PO' P1, P21 P3 They apply instructions from the cache Instruction Buffer to the processor 700.

1 BUF-EMPTY This line extends from cache 750 to processor 700. When set to a 35 binary ONE, this line indicates that the Instruction Buffer contains no instructions at this time.

i BUF-RDY This line extends from cache 750 to processor 700. When set to a binary ONE, the line indicates that the Instruction Buffer contains at least one instruction. 40 1 BUF-FULL This line extends from cache 750 to processor 700. This line indicates that the Instruction Buffer contains more than four instructions or it has at least one instruction and an outstanding instruction fetch request line.

CP STOP This line extends from cache 750 to processor 700. When forced to a 45 binary ONE state, the line signals that as a result of special conditions detec - ted within the cache unit 750, the processor 700 is required to wait or halt its operation while the cache unit 750 resolves the special conditions.

DATA-RECOV This lines extends-from the cache 750 to processor 750. It is used to 50 re-strobe processor registers following the stopping of the processor 700 in response to the detection of a cache miss condition.

While Figures 5a through 5e show lines which connect the different modules of the system of Figure 1 to SM 100 in addition to the connection to processor 700 and cache unit 750, it will be appreciated that other lines are also included for signalling other conditions, as for example, certain 55 error conditions and operational conditions. For further descriptions of the various modules of Figure 1, reference may be made to U.S. Pat. No. 4,000,487. Now, the processor module 700 and cache unit 750 will be described in greater detail.

12 GB 2 080 989 A 12 General Description of Processor 700 - Fig. 2

Referring to Figure 2, it is seen that the host processor 700 includes an execution control unit 701, a control unit 704, an execution unit 714, a character unit 720, an auxiliary arithmetic and control unit (AACU) 722, a multiply-divide unit 728, which are interconnected as shown. Additionally, the control unit 704 has a number of interconnections to the cache unit 750 as shown.

The execution control unit 701 includes an execution control store address preparation and branch unit 701 -1, and an execution control store 701-2. The store 701-2 and unit 701 -1 are interconnected via buses 701-3 and 701-6 as shown.

The control unit 704 includes a control logic unit 704-1, a control store 704-2, an address preparation unit 704-3, data and address output circuits 704--4, an XAQ register section 704-5 10 which interconnect as shown.

As seen from Figure 2, the SIU interface 600 provides a number of input fines to the cache unit 750. The lines of this interface have been described in detail previously. However, in connection with the operation of cache unit 750, certain ones of these lines are specially coded as follows.

1. MITS 0-3 for Reads are coded as follows:

bits 0-1 = 00; bits 2-3 = Read ZAC buffer address; For Write Operation bit O3 = Odd word zone 2. MIFS lines are coded as follows:

bit 0 = 0; 20 bit 1 = 0 even word pairs (words 0, 1); bit 1 = 1 odd word pairs (words 2, 3); bits 2-3 = ZAC buffer address to memory.

As concerns the interface lines DFS 00-35, PO-P3, these lines convey read data to cache unit 25 750. The lines DTS 00-35, PO-P3, are used to transfer data from cache 750 to the SIU 100.

Additionally, the SlU interface 602 provides a number of input lines to the cache unit 750 which convey information in the form of PI commands. These commands are forwarded through the cache unit 750 to a group of control logic circuits via a set of internal interface lines some of which are shown in Figure 4.

These circuits can be considered comparable to the circuits disclosed in U.S. Patent Nos. 4,006,466 30 and 4,017,836. The control logic circuits in turn forward command control signals via the lines ZPIB 9-16 for decoding by the cache section 750-100 for reading and writing cache registers and memory as explained herein. Also, the circuits forward address signals to section 750-100 via the lines ZPIDT29-35. The utilization of the above lines will be explained in greater detail with respect to Figure 4.

The control unit 704 provides the necessary control for per-forming address preparation operations instruction fetching/execution operations and the sequential control for various cycles of operation and/or machine states. The control generated by logic circuits and by the execution control unit 701 for the various portions of the control unit 704.

The register section 704-5 includes a number of program visible registers such as index 40 registers, an accumulator register, and quotient register. This section will be discussed in greater detail with reference to Figure 3. Other program visible registers such as the instruction counter and address registers are included within the address preparation unit 704-3.

As seen from Figure 2, the section 704-5 receives signals from unit 704-3 representative of the contents of the instruction counter via lines RIC 00-17. Also, lines ZRESA 00-35 apply output signals from the execution unit 714 corresponding to the results of operations performed upon various operands. The section 704-5 also receives an output signal from the auxiliary arithmetic and control unit via lines MAU0-8.

The section 104-5 provides signals representative of the contents of one of the registers included within the section as an input to the address preparation unit 704-3. The address preparation 50 unit 704-3 forwards the information through a switch to the execution unit 714 via the lines ZDO 0-35. Similarly, the contents of certain ones of the registers contained within section 704-5 can be transferred to the execution unit 714 via the lines ZEB 00-35. Lastly, the contents of selected ones of these registers can be transferred from section 704 to the multiply/divide unit 728 via the lines ZAQ 00-35.

The address preparation unit 704-3 generates addresses from the contents of various registers contained therein and applies the resultant logical, effective and/or absolute addresses for distribution to other units along the lines ASFA 00-35. The address preparation unit 704-3 receives the results of operations performed on a pair of operands by the execution unit 714 via the lines MESB 00-35.

The unit 704-3 receives signals representative of the contents of a pair of base pointer registers from 60 the control logic unit 701 via the lines RBASA and RBASBO-1. Outputs from the muitiply/divide unit 728 are applied to the address preparation unit 704-3. Lastly, the contents of a secondary instruction register (RSIR) are applied as input to the unit 704-13 via the lines RSIR 00-35.

The data and address output circuits 704-4 generate the cache memory address signals which it 13 GB 2 080 989 A 13 applies to the cache unit 750 via the lines RADO/ZADO 00-35. These address signals correspond to the signals applied to one of the sets of input lines M 00-35, ASFA 00-35 and ZRESB 00-35 selected by switches included within the circuits of block 704-4. Also, word address signals are applied via the lines ASFA 32-33. These circuits will be further discussed herein in greater detail.

The control logic unit 704-1 provides data paths which have an interface with various units included within the cache unit 750. As described in greater detail herein, the lines ZIB 00-35 provide an interface with an instruction buffer included within the cache 750. The lines W1 00-35 are used to transfer data signals from the cache 750 to the control logic unit 704-1. Other signals are applied via the other data and control lines of the cache-CP interface 604. These lines include the CP stop line shown separately in Figure 2.

As seen from Figure 2, the control logic unit 704-1 provides a number of groups of output signals. These output signals include the contents of certain registers, as for example, a basic instruction register (RBIR) whose contents are applied as an input to control store 704-2 via the lines RBIR 18-27. The control store 704-2 receives certain control signals read out from control store 704-2 via the lines CCWO 13-3 1.

The control logic unit 704-1 also includes a secondary instruction register (RSIR) which is loaded in parallel with the basic instruction register at the start of processing an instruction. The contents of the secondary instruction register RSIR 00-35, as previously mentioned, are applied as inputs to the address preparation unit 704-3. Additionally, a portion of the contents of the secondary instruction register are applied as inputs to the auxiliary arithmetic control unit 722 via the lines RSIR 1-9 and 20 24-35.

The control store 704-2 as explained herein provides for an initial decoding of program instruction op-codes and therefore is arranged to include a number of storage locations (1024), one for each possible instruction op-code.

As mentioned, signals applied to lines RBIR 18-27 are applied as inputs to control store 704-2. 25 These signals select one of the possible 1024 storage locations. The contents of the selected storage location are applied to the lines CCSID0 13-31 and to CCWO 00-12 as shown in Figure 2. The signals supplied to lines CCSID0 00-12 correspond to address signals which are used to address the execution control unit 701 as explained herein.

' The remaining sections of processor 700 will now be briefly described. The execution unit 714 30 provides for instruction execution wherein unit 714 performs arithmetic and/or shift operations upon operands selected from the various inputs. The results of such operations are applied to selected outputs. The execution unit 714 receives data from a data input bus which corresponds to lines RDI 00-35 which have as their source the control logic unit 704-1. The contents of the accumulator and quotient registers included within section 704-5 are applied to the execution unit 714 via the lines 35 ZEB 00-35 as mentioned previously. The signals applied to the input bus lines WO 00-35 from the address preparation unit 704-3 are applied via switches included within the execution unit 714 as output signals to the lines ZRESA 00-35 and ZRES13 00-35, as shown in Figure 2. Additionally, execution unit 714 receives a set of scratch pad address signals from the auxiliary arithmetic and control unit 722 applied via the lines ZRSPA 00-06. Additionally, the unit 722 also provides shift ffiformation to the unit 714 via the lines ZRSC 00-05.

The character unit.720 is used to execute character type instructions which require such operations as translation and editing of data fields. As explained herein, these types of instructions are referred to as extended instruction set (EIS) instructions. Such instructions which the character unit 720 executes include the move, scan, compare type instructions. Signals representative of operands are applied via lines ZREA 00-35. Information as to the type of character position within a word and the number of bits is applied to the character unit 720 via the input lines ZPB 00-07.

Information representative of the results of certain data operations is applied to the unit 722 via the lines ZOC 00-08. Such information includes exponent data and data in hexadecimal form. The character unit 720 applies output operand data and control information to the unit 722 and the unit 50 728 via the lines RCHU 00-35.

The auxiliary arithmetic and control unit 722 performs arithmetic operations upon control information such as exponents used in floating point operations, calculates operand lengths and pointers and generates count information. The results of these operations are applied to execution unit 714 via the lines ZRSPA 00-06 and lines ZRSC 00-06 as mentioned previously. Information signals 55 corresponding to characters such as 9-bit characters, 6-bit characters, decimal data converted from input hexadecimal data, quotient information and sign information are applied to section 704-5 via the lines RAAU 00-08.

As seen from Figure 2, the unit 722 receives a number of inputs. Character pointer information is applied via the lines ASFA 33-36. EIS numeric scale factor information and alphanumeric field length 60 information are applied to the unit 722 via the lines RSIR 24-35. Other signals relating to fetching of specific instructions are applied via the lines RSIR 01 -09. Exponent signals for floating point data are applied to the unit 722 via the lines ZOC 00-08 while floating point exponent data signals from unit 704-1 are applied via the lines RDI 00-08. Shift count information signals for certain instructions (e.g. binary shift instructions) are applied to the unit via 1he lines RDI 11-17. As concerns the input 14 GB 2 080 989 A 14 signals applied to the lines RCHU 00-35, lines 24-35 apply signals corresponding to the length of EIS instruction fields while 18-23 apply address modification signals to the unit 722.

The last unit is the multiply/divide unit 728 which provides for highspeed execution of multiply and divide instructions. This unit may be considered conventional in design and may take the form of the multiply unit described in U.S. Patent No. 4,041,292 which is assigned to the same assignee as named herein. The unit 728 as seen from Figure 2 receives multiplier dividend and divisor input signals via the lines RCHU 00-35. The multiplicand input signals from register section 704-5 are applied via the lines ZAQ 00-35. The results of the calculations performed by the unit 728 are applied as output signals to the lines ZMD 00-35.

As mentioned previously, the cache unit 750 transfers and receives data and control signals to 10 and from the SM 100 via the data interface line 600. The cache unit 750 transfers and receives data and control signals to and from the processor 700 via the lines of interface 604. Lastly, thecache unit 750 receives address and data signals from the circuits 704-4 via the lines RADO/ZADO 00-35 and the lines ASFA 32-33.

Detailed description of the processor 700

The various sections which comprise the processor 700 illustrated in Figure 2 will now be discussed in greater detail with respect to Figures 3a through 3j. Referring to Figures 3a and 3b, it is seen that the processor includes two control stores: (1) the control unit control store (CCS) 704-200 which forms part of the control unit 704: and (2) the 20 execution control store (ECS) 701-3 which is included within the execution control unit 701. To understand the operation of the control store arrangement, it is hiel p-fu-i to briefly discuss the three-stage pipeline arrangement of processor 700. This means that the processor requires at least three processor cycles to complete the processing of a given program instruction and can issue a new instruction at the beginning of each cycle. 25 Thus, a number of instructions may be in some stage of processing at any given point in time. The 25 three pipeline stages include an instruction cycle (1) wherein instruction interpretation, opcode decoding and address preparation take place; a cache cycle (C) wherein access to the cache unit 750 is made; and an execution cycle (E) wherein instruction execution takes place. As concerns control, during the 1 cycle, the op-code of the instruction applied via lines RBIR 18-27 is used to access a location 30 within control store 704-2. During a C cycle, the accessed contents from control store 704-2 are applied to lines CCS DO 00-12 and in turn used to access one of the storage locations of the execution control store 701-2. During the C cycle, the microinstructions of the microprogram used to execute the instruction are read out from the execution control store 701-2 into a 1 44-bit output register 701-4. The signals designated MEIVIDO 00-143 are distributed to the various functional units of processor 700. During an E cycle, the processor executes the operation specified by the microinstructions.

Referring specifically to Figure 2, it is seen that the control store 7042 includes a control unit control store (CCS) 704-200 which is addressed by the op-code signals applied to the lines RBIR 18-27. The CICS 704-200, as mentioned previously, includes 1024 storage locations, the contents of which are read out into an output register 704-202 during an 1 cycle of operation. Figure 6a shows 40 schematically the format of the words stored within the control store 701- 200.

Referring to Figure 6a, it is seen that each control unit control store word includes five fields. The first field is a 13-bit field which contains an ECS starting address location for the instruction having an op-code applied to lines RBIR 18-27. The next field is a three bit field (CCSO) which provides for the control of certain operations. The bit interpretations of this field depend upon its destination and 45 whether it is decoded by specific logic circuits or decoded under microprogram control. The next field is a 4-bit field which provides for certain register control operations.

The next field is a 6-bit sequence control field which is coded to specify a sequence of operations to be performed under hardwired logic circuit control as well as the type of cache operation. In the present example, this field is coded as 75 81 The last field is a 6-bit indicator field which is not pertinent 50 to an understanding of the present invention.

As seen from Figure 3a, signals corresponding to the WSA field of a control unit control store word are applied via a path 704-204 as an input to the execution generation circuits 701-7. Signals corresponding to the WSR field are applied as an input to the execution unit 714 via path 704-206.

Additionally, the same signals are applied as an input to the address preparation unit 704-3 via 55 another path 704-203.

Signals representative of the sequence control field apply as an input to the sequence control logic circuits 704-100 via path 704-210. As explained herein, these circuits decode the sequence control field and generate signals for conditioning the cache unit 750 to perform the operation designated.

As mentioned previously, the execution address generation circuit 701-1 receives an input address which corresponds to field WSA from the control store 704-2. As seen from Figure 3b, these circuits include an input address register 701 -10 whose output is connected to one position of a four position switch 701-12 designated ZECSA. The output of the switch serves as an address source for -11 GB 2 080 989 A 15 the control store 701-2. The fifst position of the switch 701-12 is connected to receive an address from the MICA register 701-14. The contents of register 701-14 are updated at the end of each cycle to point to the location within the EC8 controfstore foil'owi"ng the location whose contents were read out during that cycle.

The second position selects the address produced from the ZCSBRA branch address selector 5 switch 701-18. The third position selects the address of the first microinstruction in each microprogram provided by the CCS control store which is loaded into the REXA register 701 -10.

When the CCS output is not available at the termination of a microprogram, a predetermined address (octal address 14) is automatically selected.

The first position of branch switch 701-18 receives signals corresponding to a branch address 10 read out from store 701-2 into register 701-4 which is in turn forwarded to a return control register 701-20. The second, third and fourth positions of switch 701-18 receives signals from RSCR register 701-20, an MIC register 701-15 and the contents of a number of vector branch registers 701-36. The MIC register 701-15 stores an address which points to the microinstruction word following the microinstruction word being executed. This address corresponds to address from switch 15.

701-12 incremented by one by an increment circuit 701-12.

The vector branch registers include a 4-bit vector branch register 0 (RVBO), a 2-bit vector branch register 1 (RVB 1) and a 2-bit vector branch register 2 (RV132). These registers are loaded during a cycle of operation with address values derived from signals stored in a number of different indicator flip-flops and registers applied as inputs to the number of groups of input multiplexer selector circuits 701-32 20 and 701-34. The outputs of the circuits 701-32 and 701-34 are applied as inputs to two position selector circuits 701-30. These circuits in turn generate the output signals ZV13RO, ZVBR 'I and ZV13R2 which are stored in the registers 701-26.

The switch 701-36 provides an address based upon the testing of various hardware indicator signals, state flip-flop signals selected via an INIDGRIP field. The branch decision is determined by masking (ANDING) the selected indicator set with the INDIVISKU and INDIVISKI- fields of a micro instruction word. If a vector branch is selected, INDIVISKU is treated as 4 ZERO bits. The "OR" of the 8 bits is compared to the state defined by the TYPG and GO microinstruction fields. The hardware signals are applied via a number of data selector circuits 701-28 only one of which is shown whose outputs are in turn applied as inputs to a further five position multiplexer selector circuit 701-26. The output of 30 the multiplexer circuit 701-26 feeds a comparison circuit which "ands" the indicator signals with the mask signals to produce the resulting signals MSKCBRO-7.

The signals MSKCBRO-7 are applied to another comparison circuit whi ch--ands- the signals with the condition branch test signals TYPGGO to set or reset a branch - decision flip-flop 701-22 which produces a signal RBIDG0 whose state indicates whether branching is to take place. The output 35 signal RBIDG0 is applied as a control input to the first two positions of switch 701-12. When the branch test condition is not met (i.e., signal RRIDG0 = 0), then the incremented address from the MICA register 701-14 is selected.

In some instances, as seen herein, it is not possible to test the state of an indicator on the cycle following its formation. For this reason, history registers HRO-HR7, not shown, are provided for rbgister storage of the Group 2 indicators. The states of such stored indicators are selected and tested in a manner similar to that of the other indicators (i.e., mask fields).

Additionally, the unit 701 -1 includes a number of indicator circuits, certain ones of these are used to control the operation of certain portions of the processor 700 when the strings being processed by certain types of instructions have been exhausted. These indicator circuits are included in block 701-42 and are set and reset under the control of a field within the microinstruction word of Figure 6a (i.e., iND6 field). The bits of this field read out from the ECS output register 701-4 are applied to an RMI register 701-38 for decoding by a decoder 701-40. Based upon the state of status indicator signals received from the various processor units (e.g. 714, 720, 722, etc.), the appropriate ones of the auxiliary flip-flops are switched to binary ONE states. The outputs of these flip-flops are applied via the 50 different positions of a 4 position switch 701-44 to the GP3 position of switch 701-26 for testing. The same outputs are applied to a second position of a ZIR switch 701-43 for storage via the ZDO switch 704-340.

The indicator status signals for example include the outputs of fhedifferent adder circuits (AL, AXP) of the unit 720. These signals will act different ones of a number of exhaust flag flip-flops designated FE1 1, FE1 2, FE1 3, FE1 E, FE2E, FE2 and FE3. The FE1 E and FE2E flip-flops are set during any FPOA cycle of any instruction. These flip-flops in turn cause the FE1 1, FE1 2 and FE1 3 flip-flops to be set when the outputs from the AL or AXP adder circuits of unit 720. The setting and resetting of these indicators will be described herein in further detail in connection with the description of operation.

However, the exhaust flag flip-flops pertinent to the example given herein are set and reset in accordance with the following Boolean expressions.

SET FE111= FPOA + IND6FLID field. RESET FE1E = FPOA + IND6FLID field.

SET FE2E = FPOA + IND6FLID field.

16 GB 2 080 989 A 16 FE2E = IND6FLD field. FE1 1 = IND6FLD field. FE1 E (ALES + AXPES + DESC1 - APO-4 = 0) +

IND6FLD field. FE1 E. DESC1. (APO - 5 = 0 + APM + ALM) + IND6FLD field. FE1 1 = FPOA + IND6FLD field. FE1 2 = IND6FLD field.FE1 E. (ALES + AXPES + FE1 3). FE1 2 = FPOA + IND6FLD field. FE1 3 = IND6FLD field. FE1 E.ALES = IND6FLD field. FE1 3 = FPOA + IND6FLD field. FE2 = IND6FLD field. FE2E. ALES + IND6FLD field. FE2E.

RESET: SET RESET SET RESET SET RESET SET RESET: SET RESET DESC2. (APO-4 = 0 + APO-5 = 0 + APM + ALM + (IND6FLD field) FE2E. DESC2 + IND6FLD. FE2 = FPOA + IND6FLD field. FE3 = IND6FLD field. DESC3. (APO-4 = 0 + APO-5 = 0 + APM + ALM + IND6FLD field. DESC3 + IND6FLD. FE3 = FPOA + I ND6FLI) field.

Wherein IND6FLD indicates a particular code; ALES = AL = 0 or AL-C; AXPES = AXP = 0 or AXP-C; APM = APO-7: 0; and, ALM = ALO-1 1:! 0. 20 The ZCSBRA switch 701-18 is normally enabled when the branch decision flip-flop RBD was set to a binary ONE in the previous cycle. The first position selects a 1 3-bit branch address from the current microinstruction applied via the RSCR register-701-20. The branch address enables any one of the locations of the ECS control store to be addressed directly. The second position selects the concatenation of the 6 low order address bits from the current microinstruction applied via MiC register 25 701-15 and the 7 upper bits of the branch address from the current microinstruction applied via the RSCR register 701-20. This permits branches within a 64-word page defined by the contents of the MIC register 701-15 (current location + 1).

The third position selects the concatenation of 4 low order bits from the RVBO vector branch register, 6 bits from the branch field of the current microinstruction stored in RCSR register and the 3 30 upper bits of the address stored in the MIC register. This permits 1 6- way branches. The fourth position selects the coneatenation of the 2 low order ZEROS with 4 bits from the vector branch register RVBO with the 4 most significant bits of the branch address field of the current microinstruction and the 3 upper bits of the current address stored in the MIC register. This permits 1 6-way branches with 3 control store locations between each adjacent pair of destination addresses.

The fifth position selects the concatenation of 2 low order ZEROS with 2 bits from vector branch register RVB 1, with the 6 bits of the branch address of the current microinstruction and the upper 3 bits from the MIC register. t6is perm-its branches wit. h 4 poss. i 1 ble destinations with 3 control store locations between each adjacent palir of destination addresses.

The sixth position selects the concatenation of 2 low order ZEROS with 2 bits from vector branch 40 register RVB2 with the 6 bits of the branch address of the current microinstruction and the upper 3 bits from the MIC register. This permits 4-way branches with 3 control store locations between each adjacent pair of destination addresses.

The output of switch 701-12 addresses a specific location within control store 701-2 which causes the read out of a microinstruction word having a format illustrated in Figure 6b. Referring to that 45 Figure, it is seen that this microinstruction word is coded to include a number of different fields which are used to control the various functional units within processor 700. Only those fields which are related to the present example will be described herein.

Bits 0-1 Bit 2 Bits 3-5 TRL ELIFIVIT Reserved for Future Use.

Defines which format the EU is to operate with. EUFIVIT-0 specifies a first microinstruction format while EUFIVIT=1 50 specifies an alternate micro-instruction format.

TR Low Write Control.

Write control of EU temporary registers TRO-TR3.

0XX No change Write TRO 101 Write TR 1 Write TR2 ill Write TR3 17 GB 2 080 989 A 17 Bits 6-8 TRH TR High Write Control.

Write control of EU temporary registers TR4-TR7.

0XX No change Write TR4 101 Write TR5 5 Write TR6 ill Write TR7 Bits 9-12 ZOPA ZOPA Switch Control.

Selects the output of ZOPA switch.

0) 0000 TRO 10 1) 0001 TR1 2) 0010 TR2 3) 0011 TR3 4) 0100 TR4 5) 0101 TR5 15 6) 0110 TR6 7) 0111 TR7 8-11) 10xx RDI 12) 1100 ZEB 13) 1101 ZEB 20 14) 1110 ZEB 15) 1111 0 (disable) Bits 13-16 ZOPB Selects the output of ZOPB switch.

ZOPB Switch Control.

Bits 17-18 ZRESA ZRESA Switch Control. 25 Selects the output of ZRESA switch.

00 ALU 01 Shifter 01 Scratchpad/RDI switch 11 M0 30 Bits 19-20 ZRESB ZRES13 Switch Control.

Selects the output of ZFIES13 switch.

00 ALU 01 Shifter 10 Scratchpad/RDI switch 35 11 ZDO Bit 21 RSPB Scratchpad Buffer Strobe Control.

Strobes RSPB with ZRESB data.

0 No strobe 40 1 Strobe RSPB Bit 22 RSP Scratchpad Write Control.

0 Read scratchpad 1 - Write scratchpad Bit 23 ZSM Scratchpad/RDI Switch Control. 45 Selects the output of the Scratchpad/RDI switch.

0 Scratchpad output 1 RDI Bits 24-25 ZSHFOP Shifter Operand Switch Control.

Selects the left operand to the Shifter. '50 00 01 ZOPA output EIS output 0 11 Select 0 or -1 depending on bit 0 ofright operand to Shifter.

Bits 24-27 ALU ALU Function Control. 55 Selects the operation applied to the two inputs (A and B) to the ALU.

Bits 24-29 N/A Bits 26-31 RFU Reserved for Future Use.

Bits 30-31 ZALU ALU Switch Control.

Selects the output of ZALU switch. 60 18 GB 2 080 989 A 18 Bits 32-33 NXTD Next Descriptor Control.

Strobes RBASB and RDESC registers.

00 RBASB(-00 RIDESCx-00 01 RBAS134-01 5 RIDESKx-01 RBASS(-Alt RIDESC,-1 0 11 - No strobes (default) Bits32-35 CCM Control constant field referenced 10 by the CONTF field.

Bits 34-35 IBPIPE IBUF/Pipeline Control.

Selects the reading of IBUF or the pipeline operation.

00 No operation 01 Read IBUF/7-DI (Alt) 15 Type 1 Restart Release or 11 Type 4 Restart Wait Bits 36-37 FIVIT1) Selects the loading of various CLI registers and indicates the interpretation to be given to the MEMADR field for small CU control. 00 01 10 11

No operation RAD04-ASFA RADO--ZRESB RAM-ASFA 'Bits 38-40 MEMADR Cache Control. 25 Selects cache operations. The complete interpretation for this control is a function of the FIVITID control.

000 No operation 001 Read SgI 010 Load Quad 30 011 Preread Write Sgi 101 Write Dbl Read Sgi Trans (for FIVITID 11 only) ill Write SgI Word (for FIVITID 11 only) 35 Bit 41 ZONE Zone Control.

0 1 Indicates zone or no zone for small CU control. No zone Zone Bits 42-44 TYPA Type A Flag. 40 Indicates the types A overiayed fields being used.

000 Bits 44-46 PIPE Pipeline Control Selects the type of restart to be initiated.

Type A = 0 fields

Type A = 4 fields

000 No operation 50 001 Type 1 Restart and Release Type 2 Restart 011 Type 3 Restart Type 4 Restart 101 Type 5 Release 55 Type 6 Restart 1 19 7) 8) 9) 10) Bits 45-46 TYP B GB 2 080 989 A 19 Bits 44-47 AUXREG Auxiliary Register Write Control Selects an auxiliary register or combinations to be strobed with data selected by the AUXIN control field.

0) 1) 2) 3) 4) 5) 0000 0001 0010 0011 0100 0101 6) 0110 0111 1000 1001 No strobe RRI)XA R29 R29, RRDXA, FRL, RID RRDX13 RTYP RBASA RBAS&RTYP RBASB RDESC RBASA, R29, RR13XA Type B Flag. Indicates the Type B overlayed fields being used: 00

*Type B = 0 fields

20 11 Type B = 3 fields

Bit 47 RSC RSC Strobe Control.

Strobes the RSC register. (Shift Count) Bit 47 RSPA RSPA Strobe Control. 25 Bits 47-48 Bit 47 Bits 48-49 Bit 49 Bits 50-52 Strobes the RSPA register.

N/A RAAU Strobes RAAU register.

ZLX Selects Bits 48-49 ZSPA Selects Bits 48-50 AUXIN Selects ZADSP Selects Bits 50-52 zSC Selects ZRSPA Selects ZAAU RSIR Bits 50-52 Bit 51 RAAU Strobe Control.

ZLX Switch Control. the output of the ZLX switch.

ZSPA Switch Control. the output of the ZSPA switch.

Auxiliary Register Input Control. data to be strobed into auxiliary register(s).

ZADSP Switch Control. the output of ZADSP switch.

ZSC Switch Control. the output of ZSC switch.

ZRSPA Switch Control. the output of ZRSPA switch.

ZAAU Switch Control.

RSIR Register Strobe.

Strobes the RSIR register as a function of the AUXIN field.

Bit 53 RDW R 1 DW, R2DW Register Strobe. 45 Strobes the R 'I DW or R2DW register as a function of the RDESC register.

Bits 53-54 ZI-NA ZI-NA Switch Control.

Selects output of ZI-NA switch.

Bits 54-57 CONTF Miscellaneous Flip-Flop Control.

Selects one of four groups of control flip-flops to be set or reset by the control 50 constant field (CCM). The flip-flops include those of blocks 704-104 and

704-110.

Bits 55-56 ZLNB ZI-NI3 Switch Control.

Selects the output of ZI-NB switch.

Bits 55-56 ZSPAW Type A = 2) ZSPA Switch, RSPA Register Control, 55 Selects ZSPA switch output and strobes RSPA register.

Bits 57-58 ZPC ZPC Switch Control.

Selects the output of ZPC swiich.

Bits 59-62 ZXP ZXP Switch, RXI Register Bank Control.

Selects ZXP switch output and the RXI register into which it will be 60 written.

Bits 59-63 ZM1) ZLN Switch, RI-N Register Bank (Type A = 1) Control.

Selects ZLN switch output and the RLN register into which it will be written.

GB 2 080 989 A 20 Bits 59-60 ZPA Selects the output of ZPA switch. 00 = RPO Bit 63 11 = RP3 Bits 61-62 ZPB Selects the output of ZPB switch.

00 = RPO ZPA Switch Control.

ZPB Switch Control.

11 = RP3 Bits 63-64 ZXP L ZXPI- Switch Control. 15 (Type A = 0) Selects the output of ZXP L switch. 00 = RXPA 11 = RXPID Zi-N(2) ZI-N Switch, RLN Register Bank (Type A = 2) Control.

Selects ZI-N switch output and the RLN register into which it will be written. 25 RDI In Control.

Selects the data to be strobed into the RDI register and selects one of the modification control fields (MFl-MF3, TAG) of an instruction word. RDI strobe may also be controlled by the MISCREG field.

Bit 64 ZXPLO) ZXP L Switch Control. 30 (Type A= 1) Selects the output of ZXPI- switch.

Bits 64-68 ZRPAC ZRPA Switch, ZRPC Switch, RPO-3 (Type A = 2) Register Bank Control.

Selects ZRPC and ZRPA switch outputs and the RPO3 register into which the 35 ZRPA output will be written.

Bits 65-66 ZXPR ZXPR Switch Control.

(Type A = 0) Selects the output of ZXP R switch.

Bits 65-66 ZXPO) ZXP Switch, RXI Register Bank (Type A= 1) Control.

Selects ZXP switch output and the RXP register into which it will be written.

Bits 67-68 ZPID ZPD Switch Control. 45 (Type A = 0) Bit 67 Selects the output of ZP D switch.

ZRPAC(4) ZRPA Switch, ZRPC Switch, RPO-3 (Type A = 4) Register Bank Control.

Selects CP4 from ZRPA switch and strobes the RP 1 register.

Bit 67 TYPID Type D Flag.

Bit 68 Bits 68-71 MEM Type D Flag which indicates type D overlayed fields.

ZRPE(4) ZRPB Switch, RP4-7 Register (Type A = 4) Bank Control.

Selects 0 from ZRPB switch and strobes the RP4 register.

Cache Memory Control.

Selects the cache operation in conjunction with the SZ control.

0) 0000 No operation 15) 1111 Write Remote 21 Bits 68-70 IBUF IBUF Read Control.

Selects the destination of IBUF data when reading IBUF.

ZXPA Switch, ZXP B Switch, AXP Adder, ZAXP Switch, RE Register Control.

Selects ZXPA and ZXPB switch outputs, the AXP adder function applied to them, and the ZAXP 5 switch output. Also strobes the RE register.

Bits 69-73 ZRPB MPB Switch, RP4-7 Register (Type A = 1) Bank Control.

Selects ZRPB switch output and the 9P4-7 register into wlhich it will be written.

ZRPAC-3 ZRPA Switch, ZRPC Switch, RPO-3 (Type A = 3) Register Bank Control. Selects MPC and ZRPA switch outputs and the RPO-3 register into which the ZRPA output will be written.

Bits 72-74 ZRP13(3) MPB Switch, RP4-7 Register (Type A = 3) Bank Control.

Selects ZRPB switch output and the RP4-7 register into which it will be written. 15 Bits 72-73 SZ Size/Zone Cache Control.

Controls cache operations in conjunction with the MEM control field.

Bits 74-78 ZRP13(0) MPB Switch, RP4-7 Register (Type A = 0) Bank Control.

Bits 69-73 AXP (Type A = 0) GB 2 080 989 A 21 Bits 69-71 Selects ZRP switch output and the RP4-7 register 20 into Which it will be written.

Bit 74 Bits 74-78 AL ZALA Switch, ZALB Switch, AL (Type A = 1) Adder Control.

Selects ZALA and ZALB switch outputs and the AL adder function applied to them.

TYPE Type E Flag.

Type E flag which indicates the type E ovedayed fields.

Bits 75-77 ZVO ZXP Switch, MP Register Bank (Type A = 3) Control.

Selects ZXP switch output and the RXP register into which it will be written. 30 Bits 75-78 MISCREG Miscellaneous Register Control.

Selects various operations on miscellaneous registers (e.g. RBIR, RDI, RLEN, RSPP).

Bits 75-78 ZDO M0 Switch Control.

Bit 78 ZIM Selects the output of the M0 switch. 35 ZWN Switch Control.

Selects the output of ZIM switch.

Bits 79-83 AP ZAPA Switch, ZAPB Switch, AP Adder Control.

Selects ZAPA and ZAP B switch output and the AP adder function applied to them.

Bits 79-81 Zi-NO ZI-N Switch, RLN Register Bank (Type A = 3) Control. 40 Selects ZI-N switch output and the RI-N register into which it will be written.

Bits 79-83 ZM4) ZI-N Switch, RLN register Bank (Type A = 4) Control.

Selects ZLN output and the RI-N register into which it will be written.

Bits 80-81 RAAU RAALI/RE Register Strobe. 45 Bits 82-83 Selects the data to be strobed into the RAAU and RE registers by controlling several switches and adders in the unit 722.

APQ) ZAPA Switch, ZAPB Switch, (TypeA = 3) AP Adder Control.

Selects ZAPA and ZAPB switch outputs and the AP adder function applied to them.

Bit 84 ZRSC ZRSC Switch Control.

(Type A = 0) Selects the output of ZRSC Switch.

Bits 85-86 N/A 55 Bit 86 RLEN RLEN Strobe Control.

(Type A = 3) RLEN strobes are also controlled by hardware or by the MISCREG field.

Bit 87 FMT Format Flag. 60 Indicates the type of format.

Bits 88-89 TYPF Indicates the type of overlayed fields.

00 Scratchpad Address 01 Character Unit Control 65 22 11 Bit 90 RFU Bits 90-93 CHROP Multiply/Divide Control N/A Reserved for Future Use. Character Unit Op Code.

GB 2 080 989 A 22 Selects main operation to be performed by Character Unit and the 5 interpretation to be given to the CHSUBOP field.

0) 0000 No operation 1) 0001 Load Data 2) 0010 MOP Execute 3) 0011 Compare Single 10 4) 0100 Compare Double 5) 0101 Load Register 6) 0110 Update CN 7) 0111 Undefined 8) 1000 Set RCH Operation A 15 9) 1001 Set RTF 'I 10) 1010 Set RTF2 11) 1011 Set RTF3 12) 1100 Set WN 'I 13) 1101 Set RCN2 20 14) 1110 Set Edit Flags 15) 1111 CH Unit Clear Bit 90 RCH RCH Register Strobe.

Bit 90 Strobes the OP 1 RCH register.

RFU Bits 9 1-9 7 SPA Reserved for Future Use.

Scratchpad Address.

Contains the address that may be used to address the EU scratchpad.

Bits 91-93 N/A Bits 94-97 CHSUBOP Character n t u - p o e. 30 Selects the detailed function of the Character Unit or it may contain a constant.

The interpretation of this field is a function of the CHROP control as shown below.

U i S bO C d CHROP = 0000 No Operation CI-ISUBOP,-, 35 XXXX No interpretation CHROP = 0001 Load Data Operation CHSUBOP,-, (Suboperation) 00 OP 1 Load by CN 1 and TF1 01 OP 1 Load in Reverse by CN 1 and TF 1 40 OP2 Load by CN2 and TF2 and Test Character 11 Load Sign CHSUBOP2-3 (Fill Control) 1X Fill character loaded to WU xl Fill character loaded to ZCV CHROP = 0010 MOP Execute Operation 45 CHSUBOP,-, (Suboperation) 00 MOP set by CN2 01 MOP Execute Undefined 11 Undefined 50 CHSUBOP2-3 XX No interpretation CHROP = 0101 Load Register Operation CI-ISUBOP,-, (Selects output of RCH) CHSUBOP,-, (Selects output of ZOC switch) CHROP = 10 11 Set RTF3 Operation CHSUBOP,-, (Selects data to be inspected tor 00, indicating a 9-bit character. CHSUBOP,-, (Constant Field)

23 GB 2 080 989 A 23 Bits 94-97 Bits 97-97 Bit 98 Bit 99 Bits 99-106 15Bits 99-106 CHROP = 1110 Set Edit Flags Operation CI-ISUBOP,-, (Constant selecting flags to be set) 1 XXX Set ES (End suppression) xixx Set SN (sign) xxi X Set Z (zero) XXX1 Set BZ (Blank When Zero).

RFU Reserved for Future Use.

N/A TYPG TYPE G FLAG.

Indicates the type of overlayed fields.

0 = BRADRU field

1 = IND6 field

GO State of Conditional Branch Test.

BRADRU Branch Address Upper.

IND6FLD Indicator Control.

Selects an indicator.

Bits 39-106 Bit 99 = 0 specifies a change indicators instruction.

Bit 99 = 1 specifies a set/reset indicators instruction (set or reset indicated by X bit 0 or 1 respectively.

Bits 100-104 105 = 1 106 = 1 20 0000 25 1 100x Exhaust 1 Exhaust 2 1101x Exhaust 3 N/A 111 ox Exhaustl Exhaust 2 Eff. Eff.

Bits 107-112 BRADRL BRANCH ADDRESS LOWER. 30 Contains lower portion of an ECS address used for branching.

Bit 113 EXIT Selection of Exit Switch Control.

Bits 114-116 Bit 124 Selection of Exit indicates end of microprogram.

ZCS13RA ZCS13RA Switch Control.

Defines the position to be selected in a Control Store Branch Address Switch. 35 Bits 117-118 N/A Bits 119-123 INDGIRP Conditional Branch Indicator Group Control.

Bits 125-128 - The first two bits (119-120 select the---group-of microprograrn indicators.

The last three bits (121-123 select the---set-of indicators within each "group".

TYPH Type H field.

Indicates the type H overlayed fields.

0 = INDMSKLI 1 = VCTR field

INDMSKLI Conditional Branch Indicator Mask Upper.

Contains the upper 4 bits of the indicator mask in type H = 0 field.

Bits 125-129 VCTR Vector Select. Selects the branching vectors to be strobed into the RV130, RVB 1 and

RV132 registers. The most significant bit (125) determines which of two groups 0 or 1, 2 or 3 and 4 or 5 will be strobed into the RV130, RVI3 l and RV132 registers respectively. The remaining 3 bits select the vector within each group. 50 Bits 129-132 INDMSKI- Conditional Branch Indicator Mask Lower.

Contains the lower 4 bits of the indicator mask.

Bits 133-135 N/A Bits 136-139 CNSTU Constant Upper.

Contains the upper 4 bits of the constant field. 55

Bits 140-143 CNSTL Constant Lower.

Contains the lower 4 bits of the constant field.

Control Logic Unit 704-1 This unit includes the sequence decode logic circuits 74-100 as mentioned whose outputs feed a plurality of 1 cycle control state flip-flops of block 704-102. These flip-flops in response to signals 60 from the circuits 704-100 as well as microinstruction signals from register 701-4 (DEMR038-40 which correspond to the mem address field MEMADR of Figure 6b) generate the various required l cycle control states required for the execution of program instructions. It is assumed that block 704-102 also includes gate circuits which generate register hold signals [HOLDEOO which are distributed throughout the processor 700.

24 GB 2 080 989 A 24 As seen from Figure 3c, the 1 cycle control state flip-flop receive control input signals via control lines including a line CPSTOPOO from cache unit 750. As explained herein, the state of the CPSTOPOO line determines whether processor operation continues in that when the line is forced to a binary ZERO, the hold or enabling signals for the 1 cycle control state flip-flops and other storage registers are also forced to ZEROS. The hold signals corresponding to signals [HOLD100 and [HOLDEOO operate to hold or freeze the state of the processor 700. Since no incrementing of the control store address can take, the ECS control store reads out the same microinstruction word. The signals [HOLDI and [HOLDE are set in accordance with the following Boolean expressions: [HOLD1 = CACHE HOLD + HOLD REL wherein the state of signal CACHE HOLD corresponds to the state of signal CPSTOP and the signal HOLD REL is a binary ONE until switched to a binary ZERO by the generation of a microprograrn release signal; and 10 [HOLD E = [HOLD 1.

In accordance with the teachings of the present invention, each of the instructions which comprise the repertoire of the preferred embodiment of the present invention are assigned one of a number of control sequence codes (CCSS) as follows which enable efficient instruction cycle processing. These different classes of hardwired sequences are established to permit the kind of performance desired for 15 the execution of the entire repertoire of instructions listed in Appendix A. The hardwired sequence selected for each instruction is chosen to provide the particular type of performance required for efficient pipgline operation.

Thdinstructions are designated by mnemonics which are listed in an instruction index included in an appendix A. A number of the instructions are described in.the publication -Series 60 (Level 66)/6ooo 20 MACRO Assembler Program (GIVIAP)" by Honeywell Information Systems Inc., copyright 1977, order number D130813, Rev. 0.

WS-S SEQUENCE INSTRUCTION TYPES - 000000 I-D-SG1- LDA, LDQ, LCA, LCQ, ADA, ADO, ADLA, ADLQ AWCA, AWCQ, SWCA, SWM CMPA, 25 CMPQ, CANA, CANQ, ANA, ANQ, ORA, ORQ, ERA, ERQ, SBA, Sl3Q, SBLA, S13LQ LDE,WN,FWN,1-XLN,LD1 000001 LD-SGL-DEL FLD, CNAA, CNAQ, ADE 000010 LD-WL-ESC MPY, MPF, DIV. DVF, CWL, CMG, CMK, 30 FAD, UFA, FS13, UFS, FIVIP, UFIVI, FDV, FDI, LDT, FCMP, FCIVIG, CCD, ADL, XEC, CIOC, LPDBR, I-DDSA, LDO, LDPn, LDEAn, PAS, LARn, AARn, NARn, LDWS 000011 LD/STR-SGL-ESC ASA, ASQ, AOS, SSA, SSQ, ANSA, 35 ANSQ, ORSA, ORSQ, ERSA, ERSQ, ARAn, ARNn, SARn.

LD-HWU LDXn, LCXn, ADXn, AD1-Xn, SBXn, S131-Xn, ANXn, ORXn, ERXn, CIVIPKn 000101 I-D-HWU-DEL CNAXn 40 I-D-HWU-ESC LBAR, LBER, LMBA, LMBB 000111 LD/STW-HWLI-ESC ASXn, SSXn, ANSXn, ORSXn, ERSXn 001001 LD-DBL LDAQ, LCAQ, ADAG, ADLAG, SBAQ, SI3LAQ, ANAG, ORAQ, ERAQ, CMPAQ, CANAQ, DFLD 45 001010 I-D-13BL-ESC CNAAQ, XED, LDSS, LDAS, WPS, I-DDS1), DFSB, DUFS, DFIVIP, DUFM, 13FDV, DFD1, DFC[ViP, DFCIVIG, DFAD, DUFA, DFD1, DFCIVIP, DFCIVIG, DFAD, DUFA, QFLD, WAD, WSB, QFMP, QSMP. 50.

010000 STR-SGI- STA,STQ.

010001 STR-HWU STXn 010010 STR-DBL STAQ 010100 RD-CLR 011000 EFF-ADR EA&EAQ,EAXn,NEG 55 011010 EFF-ADR-ESC ARS, QRS, LRS, ALS, QLS, LLS, ARL, QRL, LRL, ALR, LLR, OL13, GTB, NEGL 100000 TRF TRA, TZE, TW, TMI, TPL, TW,TNC, TOV, TEO, TEU, TTF, TRTN, TRTF, TTN, TM OZ, TP NZ 60 1 GB 2 080 989 A 25 CCS-S SEQUENCE INSTRUCTION TYPES 100100 ESC RCCL, LCCL, RPT, RPD, RPL, STCA, STCQ, STBA, ST13Q, MME, DRL, JLLOC, CCA, AWD, SWD, A9BD, A4BD, A6BD, ABD, S9BD, S4BD, S6BD, SBD, CAMP, 5 RPN, RIMR, SFR, LLUF, LiMR, RRES, HALT, SDRn, EPAT.

100101 ESC-LD MILIDA,MLI)QMLIDAQ 100110 ESC-ST MSTA, MSTQ, MSTAQ 101000 NO-OP NOP 10 101001 TSXN TSXN 101010 ESC-EA LREG, SREG, STC1, STC2, FSTR, DFSTR, STE, SBAR, TSS, RET, SPL, LPL, STI, SBER, SMBA, SMBB, SAREG, SXLn, EPAT, EPPRn, CLIMB, STWS, STPn, 15 LAREG, QFSTR, LIDDn, FST, DFST, FRD, DFRD, FNEG, FNO, STDn, LDAC, LDQC, SZNC, DIS 101100 DEL-STR-SGIL STT, STZ, SPDBR, STPDW, STPTW, STDS&STO 20 101101 DEL-STR-D131--- STSS, STDSD, STTA, STTD, STPS, STAS, S=n,QFST 110000 BIT CSL, CSR, SZTL, SZTR, CMPB 110001 MTM-MTR MM MTR 25 110011 MRL MRL 110100 TCT TCT 110101 TUR TUR 110110 SCAN-FWD SMSCD 110111 SCAN-REV SCMR, SCDR 30 111000 NUM2 MVN, MVNX, CMPN, CMPNX, AD2D, AD2DX,.

SB2D, S132DX, DV21D, DV2DX, MP2D, MP2DX 111001 MVT MVT 111010 CONV BTD,13TB 111011 MLR MLR 111100 NUM3 AD3D,AD3DX,SB3D,SB3DX,MP3D,MP3DX, 35 DV313,DV31DX CCS-S SEQUENCE INSTRUCTION TYPES 111101 EDIT MVE, MVNE, MVNEX 111110 CMPC CMPC 111111 CMPCT CMPCT 40 The different assignable hardwired sequences operate in the following manner.

HARDWIRED SEQUENCES LID-SGIL SEQ This hardwired sequence causes the control unit to generate the effective address during a FPOA cycle and to cause the cache unit to execute a read single memory cycle of operation. When indirect 45 addressing is specified, control is transferred to an address preparation microprogram routine. The requested data is loaded into the RDI register at the completion of the cache cycle and is then available for use during the execution cycle.

LD-SGL-DEL SEQ This 2T hardwired sequence is the same as LID-SGI--- except that a 'IT delay state is entered after 50.

the FPOA cycle (FPOA-+FDEL-->FPOA-NEXT).

ILD-SGIL-ESC SEQ Same as LID-SGIL sequence except the pipeline is stopped after the current FPOA cycle is completed (escape state is entered).

LD-HWU SEQ Same as LD-SGI--- sequence except that bits 00-17 of RDI register are loaded from the cache unit. Memory bits 00-17 and zeros are loaded into IRDI,_,, 26 GB 2 080 989 A 26 HARDWIRED SEQUENCES (cont'd) I-D-HM-DEL This 2T hardwired sequence is the same as the LD-HWU sequence except a 1 T delay state is entered after state FPOA. The sequence is FPOA---.>FD EL- +FPOA-N EXT.

I-D-HM-ESC This sequence is the same as the LD-HWU sequence except the pipeline is stopped after the completion of the current FPOA cycle.

LDISTR-SGL-ESC This sequence is the same as the I-D-SGL-ESC sequence except that in addition to normal read checks, a write check is also performed. This sequence is used for "READ- ALTER-REWRITE- types of 10 operation.

LD/STR-I-IM-ESC This seqdence is the same as 1-13/STR-SGL-ESC sequence except that bits 00-17 of the RDI register are ioaded from the cache unit memory bits 00- 17 and zeros are loaded in RDI......

LD-DBL SEG This sequence causes the control unit to generate the effective address during a FPOA cycle and causes the cache unit to execute a read double memory cycle of operation. The requested data is returned to the RDI register on two consecutive cycles.

LD-DBL-ESC SEQ This sequence is the same as the LD-DBL sequence except the escape state is entered after the 20 current FPOA cycle is completed STR-SG1- SEQ This 2T sequence (FPOA--)FSTR) causes the control unit to generate an effective address and causes the cache unit to execute a write single memory cycle WPOA) of operation. During the second cycle WSTR) the register to be stored (as selected by the contents of the RRDX-A register) is 25 transferred to the RADO register as follows ZX-ZDO->ZRESB fflADO.

STR-HWU S EQ This sequence is the same as the STR-SG1- sequence except that the cache unit causes a change only in bits 00-17 of a memory location.

STR-DBL SEQ This 3T sequence (FPOA --. FSTR-DBL ---> FSTR) causes the control unit to generate an effective address and causes the cache unit to execute a write double memory cycle (FPOA control state) of operation. During the second and third cycles the EVEN and ODD data words (as selected by the contents of the RIRDX-A register) are sent to the cache unit.

RD-CLR SEO 35 This sequence is the same as the LD-SGi- sequence except the cache unit causes the memory location to be read and also cleared.

EFF-ADR SE0 This sequence causes the control unit to load bits 00-17 of the RDI register with an effective address that is generated during a FPOA cycle while bits 18-35 of the RDI register are loaded with zeros. 40 EFF-ADR-ESC SEO This sequence is the same as the EFF-ADR sequence except the pipeline is stopped after the FPOA cycle (Escape state is entered).

TRF SEO This sequence causes the control unit to request two four word blocks of instructions (during FPOA and 45 FTRF control states) for the instruction buffer in preparation fora transfer of control or any branch operation.

ESC SEO This sequence causes the pipeline to be stopped after the FPOA cycle. No memory cycles are initiated and there is no address preparation performed.

1 1.

I 27 HARDWIRED SEQUENCES (cont'd) ESC-LD & ESC-STR SEOS These sequences are the same as ESC and are used for executing testing operations.

GB 2 080 989 A 27 ESC-EA SEO This sequence causes the control unit to load a temporary register with an address pointer generated 5 during the FPOA cycle. The pipeline is stopped after FPOA.

DEL-STR-SiSL SEO This 3T sequence (FPOA-FDEL-FESC) causes the control unit to generate an effective address during state FPOA and then switch to a second FDEL state. This allows the cache unit an extra cycle to fetch the data to be stored. At the completion of FDEL, the cache unit is caused to initiate a write single 10 memory cycle of operation and the hardware switches to FESC state. The data to be written is transferred to the RADO register under microprogram.

DEL-STR-DBL SEO This sequence is the same as DEL-STR-SGI- except the sequence is 3T. The sequence is FPOA --.> FDEL--+ FESC. A write double memory cycle is initiated during state FDEL. Data is transferred to 15 the RADO register on the cycles following state FEDL under microprogram control.

1 EDIT SEO (EIS) This sequence is FPOA-FPOP 1 -FPOP2 followed by FPOP3. There is an escape to microprograrn control which following the setting up of registers, tables, etc. req-uired for processinq edit-operands 20 signals the hardware control circuits to enter state FPOP3.

The remaining EIS sequences can be considered as having states similar to that of the EDIT sequence.

TSXn This sequence causes the processor 700 to compute the effective address and update the instruction counter. During a second cycle (FTSM), the updated instruction counter is loaded into the RDI register 25 for subsequent transfer to the specified index register. The computed effective address is loaded into TEAO and the processor 700 transfers control to that location (FPI-INIT).

The handwired control states used during 1 cycle processing in accordance with the present invention and a brief description of the operations performed during such control states or cycles are as follows.

1 CYCLE CONTROL TATE/CYCLE DESCRIPTION

FPOA FESC FPOP FSTR FSTR-D13L FDEL The FPOA Prepare Operand state is the starting control state for all instructions. During FPOA, an address is calculated and the op-code is translated via the CCS control store to control further actions. 35 The FPOP Prepare Operand Pointer state is used to process EIS instruction descriptors.

The FSTR Store state is used to transfer -store- data into the RADO register in the case of instructions requiring sequences, and to transfer the second (odd) word of double precision data to the RADO register in 40 the case of instructions requiring store double sequences.

The FSTR-DI3L Store Double state is used to transfer the first (even) word of double precision data to the RADO register for those instructions requiring store double sequences.

The FESC Escape state is used to provide a variable delay to the 45 1-Process pipeline. During state FESC, the ESC control store has complete control over the processor 700, and determines when to restart the 1-Process pipelifie.

The FDEL Delay state provides a 1T delay to the 1-Process pipeline.

28 1 CYCLE CONTROL STATE/CYCLE GB 2 080 989 A' 28 DESCRIPTION (cont'd)

FWF-IND FTR17 FTRF-NG FPIM-1 FPIM-2 FPI-INIT FWF-IBUF FPIM-EIS FWF-DESC FIDESC FW17-1DESC FIT---] 4,5 The FWF-IND Wait for Indirect Word state provides the control to transfer signals on the Z131 lines into the RSI R register.

The FTRF Transfer state is used to request that the cache unit fetch a second block of instructions for loading into the 1 Buffer and to strobe a first instruction for a new instruction stream into the processor 700 RBIR register.

The 17TRF-NG Transfer No Go state is used to reload the 1 Buffer address registers with the old instruction stream address.

The FPIM-1 Prepare Instruction Address for 1 Buffer Maintenance Type.. 1 state is entere d when the 1 Buffer runs out of instructions. During the FP I M-1 state, a block of instructions is requested for the 1 Buffer. Also, during the FPIM-1 state, a processor-hold condition occurs when the cache unit signals a Cache-Miss condition.

0 The FPIM-2 Prepare Instruction Address for 1 Buffer Maintenance Type 2 state enables a second block of instructions to be requested for the 1 Buffer. During the FPIM-2 state, there is no-processor-hold condition generated when the cache unit signals a Cache-Miss condition. Also, during state FPIM-2, the next instruction is strobed into the 20 processor's RBIR register.

The FPI-INIT Prepare Instruction Address for 1 Buffer Initialize state is used to reload the 1 Buffer after a transfer (store compare) or after a Type 3 restart.

The FWF-IBLIF Wait for 1 Buffer Ready state is entered when an 25 instruction is needed from the 1 Buffer, and the 1 Buffer is in a not ready condition.

The FPIM-111S Prepare Instruction Address for 1 Buffer Maintenance EIS state is entered following the FPOA cycle of an EIS multi-word instruction whenever the 1 Buffer does not contain enough deserliptors 30 to complete the processing of the instruction.

The FWF-DESC Wait for Descriptor state is entered when a descriptor is needed from the 1 Buffer, and the 1 Buffer is in a not ready condition.

The FIDESC Indirect to Descriptor state is the control state used to 35 process EIS indirect descriptors.

The FWF-IDESC Wait for Indirect Descriptor control state provides the control to transfer the cache word applied to the ZDI lines to the RSIR register 704-154.

The FIT-1 indirect and Tally Indirect control state is used to process 40 non-EIS descriptors specifying indirect and tally indirect address modifications.

FTSX1 The FIRT Indirect and Register Test control state is entered during the processing of non-EIS descriptors specifying indirect and register address modifications to determine whether the processing of that type of address modification is completed.

The FT5Xl Transfer and Set Index control state is used to transfer the updated contents of the instruction counter to the RDI register in the case of transfer and set index instructions.

- 29 GB 2 080 989 A 29 As seen from Figure 3c, signals corresponding to the 1 cycle control states are applied as inputs to a plurality of control flip-flops of block 704-104, decoder circuits of block 704-106, a number of control logic circuits of block 704-108 and to a plurality of control flag indicator flip-flops of block 704-110. It is also seen that the various indicator flip-flops of block 704-110 also receive microinstruction input signals via lines MEMD054-57 from execution control unit 701-4.

As seen from Figure 3d, signals generated by the hardware control logic circuits 704-108 fall into one of three groups as a function of the units whose operations are being controlled. That is, the groups are instruction buffer control, hardware control and hardware memory control.

In each case, each group of signals are ored together with equivalent signals generated by other sources and then decoded. The other sources correspond to fields within the two different formats of 10 the microinstruction word of Figure 6a which are loaded into RCSR register 704-112 from the ECS output register 701 4.

One field corresponds to bits 32-83 of one format (large CU) and another field (short CU) corresponds to bits 32-41 of another format. These fields are decoded by a decoder 704-114 into the sets of bits indicated and combined within the decoders 704-116, 704- 124, 704-126 and 15 704-128 as shown-Further decoding is done by the circuits of blocks 704- 118, 704-135 and 704-120. The results of decoding such fields are either distributed throughout processor700 or are stored in an RMEM register 704-130, an RSZ flip-flop 704-132, an FREQDIR flip-flop 704-136 and an FREQiCAC flip-flop 704-134. - Additional decoding of the large and short CU fields and signals from the 1 cycle state circuits of 20 block 704-112 is done via a decoder 704-106 and 704-107. The decoder 704- 106 generates control signals for loading different ones of the registers and for enabling various muitiplexer/selector switches within the processor 700. The decoder 704-107 operates to generate signals for setting and resetting a pair (RBASB). of base pointer B flip-flops 704-144. Other combinations of these signals are used to set and reset the descriptor number flip-flops of blocks 704-140 and 704-142.

As seen from Figure 3c, the decodeer 704-116 receives a control signal [EXHOO generated by the decoder circuits of block 704-117. These circuits receive signals from the RDESC register 704-140 and signals from the exhaust flip-flops of block 701 -1. In accordance with the states of these signals, the circuits force signal [EXI-1000 to a binary ZERO to inhibit the generation of a cache memory command upon the occurrence of an exhaust condition. The signal [EXHOOO is generated in 30 accordance with the following Boolean expression:

[EXI-1000 = DESCO. FE 11 + DESC 1. FE2 + DESC2. FE3.

The flip-flop FNUM is normally set in response to the CCS-OP field of the microinstruction word.

When set to a binary ONE, this indicates that the descriptor being processed is a numeric type. 35 The different flip-flops of block 704-104 will now be discussed in greater detail. In greater detail, - the flip-flop FiCHAR provides certain changes in the control of address generation. When the FICHAR flip flop is set to a binary ONE during the processing of a load type instruction specifying character modification, then the contents of the RDI register is not changed under hardware control. This allows, the RDI register to be loaded with data under microprograrn control prior to starting the pipeline. Also, if 40 the FICHAR flip-flop is set to a binary ONE during a store type instruction specifying character modification, then the execution address for this instruction is modified under hardware control to point to a unique address of the microinstruction sequence in the ECS control store that is to process this type of instruction.

The flip-flop FDT-FOUR provides additional control on the readout of the address register 45 (ZAR,_j of block 704-304. Flip-flop FADR-WID provides additional control for the ZDO switch 704-340. When this flip-flop is set to a binary ONE, then the ZAR position of the ZDO switch is forced to select a word address. The flip-flop FADR-B provides additional control for the ZDO multiplexer switch. When set to a ONE, then the ZAR position of the ZDO switch is forced to select a byte address.

The flip-flop FNUM is normally set in response to the CCS-OP field of the microinstruction word. When 50 set to a binary ONE, this indicates that the descriptor being processed is a numeric type. The flip-flop FIG-LEN provides additional control over the loading of registers within the unit 722 (length registers) and over memory operations. When set to a binary ONE, the RXI? and RI-N registers within unit 722 are not loaded from the RSIR register 704-154 during control states FPOP.

The FINI-I-ADRflip-flop inhibits the operation of the address preparation unit 704-3. When set 55 to a binary ONE, an address cycle (17POA/FPOP) consists of adding the contents of a temporary effective address register REA-T + ZERO. The register REA-T will have been loaded with the address prior to doing a FPOA/FPOP cycle. The FABS flip-flop enables the generation of absolute addresses. When set to a binary ONE, a 24-bit absolute address is used. As concerns the flag or indicator flip-flops of block 704-110, flip-flop FID when set to a binary ONE provides an indication that indirect address modification during an instruction is required on the descriptor loaded into the RSIR register.

The FRL flip-flop when set to a binary ONE indicates that the length is specified in a register associated with the instruction loaded into various instruction registers. The three flip-flops FINDA, GB 2 080 989 A 30 FINDB and FINDC provide indications used in processing memory type instructions. Flip-flop FINDA is set to a binary ONE when length is specified in a register or when flip- flop FAR is set to a ONE. Flip-flop FINDB is set to a binary ONE when the descriptor does not include nine bit characters. The flip-flop F] NDC is set to a binary ONE when the descriptor does include six bit characters.

The FAR flip-flop is set to a binary ONE when the processor circuits detect that indicator bit 30 of 5 IR register 701-41 was set ot a binary ONE during the execution of an EIS instruction indicative of a mid instruction interrupt (required to adjust pointer and length values because of interrupt). The FTRGP, FTNGO and FTRF-TST flip-flops are set to binary ONES in conjunction with transfer type instructions.

More specifically, the FTRGP flip-flop provides a microprogram indication of being set to a binary ONE when the processor circuits detect the read out of a transfer type of instruction during the execution of 10 an execute double (XED) of repeat (RPTS) instruction. The FTNGO flip-flop provides a microprogram indication of being set to a binary ONE when the condition of transfer signalled by the execution control unit 701 was transfer NO GO (i.e., transfer did not take plade). The FTRF- TST flip-flop of this group indicates when set to a binary ONE that the previous instruction executed by processor 700 was a 15. transfer type instruction and that the current 1 cycle is to be executed conditioned upon the presence of a transfer GO (TRGO) signal from control unit 701.

Additionally, the circuits of block 704-110 include a number of flipflops used in performing indirect addressing operations under hardwired control for other than EIS instructions. These include FIR, FIRT, FIRL and FRI flip-flops which are switched to binary ONES as functions of the different types of indirect address modifications required to be performed. For example, the FRI flip-flop signals a register then indirect address modification and is switched to a binary ONE when a register indirect (R0 indicator is a binary ONE. The FIR flip-flop is switched to a binary ONE when an indirect then register (M) indicator is a binary ONE. This flip-flop signals the beginning of an indirect then register address modification. The FiRL flip-flop is switched to a binary ONE when an indirect then tally indirect (IT-1) indicator is a binary ONE. This flip-flop signals a last indirect operation. Another flip-flop TSX2 provides an indication used in processing transfer and set index instructions while a STR-CPR flip-flop is used during the processing of store instructions.

As seen from Figure 3c, the outputs from the control flag flip-flops of block 704-110 are applied as inputs to the branch indicator circuits of block 701-1. Also, output signals from the control flag flip flops are also applied as inputs to the 1 cycle flip-flops of block 704- 102.

Register Section 704-150 - As seen from Figure 3c, the control logic unit 704-1 further includes a register section 704-150. This section contains the basic instruction register (RBI R) 704- 152, the secondary instruction register (RSIR) 704-154, a base pointer A register (RBASA) 704-156 used for selecting one. of the address registers RARO through RAR7 of block 704-304, a read index register A ffiRDXA) 35 704-158 used for selection of index registers included within section 704- 5 (not shown) and for selection of outputs from the ZDO multiplexer switch 704-340, a read index A save (RR13iXAS) register 704-159, and a descriptor type register (RTYP) 704-160 indicating the type of data characters being pointed to by the descriptor value (e.g. 9-bit, 6-bit, 4-bit). The section 704-150 further inclu ' des a 1 -bit instruction/EIS descriptor register designated R29 of block 704- 162. The state of this bit in 40 conjunction with the contents of the RBAS-A register 704-158 are used to select the particular address register used for address preparation. When register R29 of block 704-162 is set to a binary ZERO, this indicates that none of the address registers of block 704-304 are used during address preparation. The last registers of section 704-150 include the data in register (RDI) of block 704-164 and a read index B (RRDXB) pointing to registers used by execution unit 714.

As seen from Figure 3, the RBIR register 704-152 is loaded via a two position switch 740-170 connected to receive signals from the sources indicated (i.e., a switch ZIB-B 704-172 and lines ZD] 0-35). The RSIR register 704-154 similarly receives signals from the ZDI lines and switch 704-172. The RBASA register 704-156 receives signals from the W1 line 0-2 in addition to a further switch ZBASA of block 704-174. The RFIDXA register and RTYP register receive signals from 50 the ZDI lines as well as a switch 704-176 and 704-178 as shown. Also, the RRIDXA register receives signals from the 13RDXAS register 704-159.

The switch 704-172 is a two position switch which receives inputs from the switches ZIB and ZRES13 from the cache unit 750 and execution unit 714 respectively. The switch 704-174 is a three input switch which receives two inputs from the execution units 714 and the output of the ZIB switch of 55 cache unit 750.

Switch 704-176 is a four input switch which receives two of its inputs from the execution unit 714 and a single input from cache unit 750. The first position of the ZR1DXA switch 704-176 selects the output of a ZR1DX1V1 switch 704-185. One position of this switch provides a tag field value from bit positions 5-8, 14-17, and 32-35 of the RBIR register 704-152 and bit positions 32-35 of the 60 RSiR register 704-154 selected from ZIDD switch 704-180 and a two position ZMF switch 740-176.

The second position of switch 704-185 provides a constant value from the output of the ECS output register 704-1 (C1CM field 32-34). The signals from the lines ZIDD 27-35 are applied as

31 GB 2 080 989 A 31 inputs to control flag flip-flops of block 704-110. The switch 704-178 receives an input from the control store 704-2, an input from cache unit 750 and an input from execution unit 714.

The data input register 704-164 receives a series of input signals from a ZIDD switch 704-180 which connects in series to a MIA switch 704-181 whose output provides one input of a further switch 704-182 which directly loadsinto the RID1 register 704-164. The MA switch 704-181 provides a further input to a three input switch 704-183 which receives the other inputs indicated from cache unit 750 and execution unit 714.

The ZIDD switch 704-180 receives an effective address via switch 704-186 from the address preparation 704-3 as well as inputs from the RBIR register 704-152, the RSIR register 704- 154 and a two position ZMF switch 740-187. The positions 18 through 35 of the REA position of switch 10 704-180 are derived from the MIA switch 704-181 as shown. The MIA switch 704-181 receives signals from the M1 lines 0-35, a constant value generated from the inputs to a first switch position in addition to signals from the output of the ZIDD switch 704-80 and the ZRESB switch in execution unit 714. The switch 704-182 receives the output of the MIA switch and signals from the M1 lines 0-35. The RRIDX13 register 704-189 is loaded by a three position switch 704-188. The switch 15 receives via a first position signals from a RREG register included in the execution unit, a constant value from control store 701-2 via a second position and signals from the ZIDD switch via a third position.

The section 704-150 further includes a two position switch 704-185 and a scratchpad pointer register 704-186 whose output is used by the AACU 722 to form addresses for access to the scratchpad memory of the EU 714. The first switch position provides a constant value and is selected 20 under hardware control (FPOA. _REM. The second switch position applies as an output the contents of the RBASA register 704-156. This position is selected under both hardware and microprogram control (i.e., FPOA. R29 or MISCREG field).

It will be appreciated that the required timing signals for operating section 704 as well as other sections of processor 700 and cache unit 750 are provided by centrally located clock circuits. For example, in the preferred embodiment of Figure 1, the clock circuits are located within the input/output processor 200. Such clock circuits can be considered as conventional in design and can comprise a crystal controlled oscillator and counter circuits. The timing or clocking signals from such clock circuits are distributed in a conventional manner to the various portions of the system of Figure 1 for synchronized operation.

Register Section 704-150 As seen from Figure 3c, the control logic unit 704-1 further includes a register section 704-150. This section contains the basic instruction register (RBIR) 704- 152, the secondary instruction register (RSIR) 704-154, a base pointer A register (RBASA) 704-156 used for selecting one of the address registers RARO through RAR7 of block 704-304, a read index register A 704-158 35 used for selection of index registers included within section 704-5 (not shown) and for selection of outputs from the ZDO multiplexer switch 704-340, and a descriptor type register (RTYP) 704-160 indicating the type of data characters being pointed to by the descriptor value (e.g. 9-bit, 6-bit, 4-bit).

The section 704-150 further includes a 1 -bit instruction/EIS descriptor register designated R29 of block 704-162. The state of this bit in conjunction with the contents of the RBAS-A register 40 704-158 are used to select the particular address register used for address preparation. When register R29 of block 704-162 is set to a binary ZERO, this indicates that none of the address registers of block 704-304 are used during address preparation. The last registers of section 704-150 include the data in register (RDI) of block 704-164 and a read index register B pointing to registers used by execution unit 714.

As seen from Figure 3, the RBIR register 704-152 is loaded via a two position switch 704-170 connected to receive signals from the sources indicated (i.e., a switch ZIB-B 704-172 and lines M1 0-35). The RSIR register 704-154 similarly receives signals from the M1 lines and switch 704-172. The RBASA register 704-156 receives signals from the M1 line 0-2 in addition to a further switch ZBASA of block 704-174. The RRIDXA register and RTYP register receive signals from 50 the M lines as well as a switch 704-176 and 704-178 as shown.

The switch 704-172 is a two position switch which receives inputs from the switches ZIB and ZRES13 from the cache unit 750 and execution unit 714 respectively. The switch 704-174 is a three input switch which receives two inputs from the execution units 714 and the output of the ZIB switch of cache unit 750.

Switch 704-176 is a four switch which receives two of its inputs from the execution unit 714 and a single input from cache unit 750. The first position of the W1DXA switch 704-176 selects the output of a MM switch 704-185. One position of this switch provides a tag field value from bit positions 5-8, 14-17, and 32-35 of the RBIR register 704-152 and bit positions 32-35 of the RSIR register 704-154 selected from ZIDD switch 704-180 and a two position ZMF switch 60 740-176.

The second position of switch 704-185 provides a constant value from the output of the ECS output register 704-1 (CCM field 32-34). The signals from the lines ZIDD 27-35 are applied as inputs to control flag flip-flops of block 704-110. The switch 704-178 receives an input from the 32.

GB 2 080 989 A 32 control store 704-2, an input from cache unit 750 and an input from execution unit 714.

The data input register 704-164 receives a series of input siggals from a ZIDD switch 704-180 which connects in series to a MIA switch 704-181 whose output provides one input of a further switch 704-182 which directly loads into the RDI register 704-164. The MIA switch 704-181 provides a further input to a three input switch 704-183 which receives the other inputs 5 indicated from cache unit 750 and execution unit 714.

The ZIDD switch 704-180 receives inputs from the RBIR register 704-152, the RSIR register 704-154 and a two position ZMF switch 740-187. The MIA switch 704-181 receives signals from the W1 lines 0-35, a constant value generated from the inputs to a first switch position in addition to signals from the output of the ZIDD switch 704-80 and the MES13 switch in execution unit 10 714. The switch 704-182 receives the output of the MIA switch and signal. s from the W1 lines 0-35. The RI1DX13 register 704-189 is loaded by a three position switch 704-188. The switch receives via a first position signals from a RREG register included in the execution unit, a constant value from control store 701-2 via a second position and signals from the ZIDD switch via a third position.

The section 704-150 further includes a two position switch 704-185 and a scratchpad pointer register 704-186 whose output is used by the AAW 722 to form addresses for access to the scratchpad memory of the EU 714. The first switch position provides a constant value and is selected under hardware control (FPOA. R29). The second switch position applies as an output the contents of the RBASA register 704-156. This position is selected under both hardware and microprogram control (i.e., FPOA.R29 orMISCREG field).

Address Preparation Unit 704-3 The address preparation unit 704-3 includes a number of registers and adders. The registers include a number of base registers (i.e., TBASEO through TBASEB) of block 704-300 used for storing descriptor values of an instruction, a pair of temporary effective address registers (TEAO, TEA1) and a pair of instruction counters (ICBA, IC1313) included within block 704-302 used for addressing the instruction buffer and eight address registers (RARO through RAR7) of 704- 304 used during address preparation operations. The unit 704-3 also includes an instruction counter 704-310.

The adders include adder 704-312 used to update instruction counter 704310 via switches 704-311 and 704-314 and a pair of adders 704-320 and 704-322. The adder 704-322 is used to generate an effective address value which is stored in a register 704-342 applied as an input 30 of the control unit 704-1. The effective address is generated from a number of sources which include ZY switch 704-326 whose output is applied via a number of AND gates of block 704-327, selected address registers of block 704-304 or selected temporary address registers TEAO and TEA1 of block 704-302 applied via another switch 704-328 or the index address signals ZXO-20 from unit 704-5. Additionally, adder 704-322 is used to update the contents of the instruction counter of the 35 cache instruction buffer.

As seen from Figure 3d, the outputs from adder 704-322 are also applied as an input to the adder 704-320. The adder 704-320 is used to combine base value stored in any one of the temporary base registers TBASE0'through TBASEB with the address signals ACSOSO-1 9 from adder 704-322. The resulting bits are applied as an input to a further adder network 704-320 which generates a logical address which is applied to the lines ASFAO-36 via an adder 704-32 1. This adder sums the operand inputs together with the carry inputs from blocks 704-300 and 704-320.

The effective address is used to obtain an absolute address when the system is operated in a paged mode. Since this operation is not pertinent to the present invention, it will not be discussed further herein. For further information regarding such address development, reference may be made to U.S. Patent No. 3,976,978.

The temporary base registers of block 704-300 are loaded via a switch 704332. The switch receives an input from the execution unit 714 and the output from block 704-300. The execution unit 714 applies further inputs to the registers of block 704-302 via a switch 704-334 as well as to the add ress registers of block 704-304. An output multiplexer (M0) switch 704-340 enables the selection of the various registers within the address preparation unit 704-3 and unit 704-5 for transfer of their contents to the execution unit 714 via lines W0 0-35. Also, the W0 switch 704-340 enables the contents of various ones of the registers and control flip-flops of unit 704-1 to be read out via a fourth position (ZDO-A). The fifth position enables the states of various indicators within the control store circuits of block 701-1 to be selected for examination.

XAQ Register Section 704-5 and Data Address Output Section 704-4 Figures 3e and 3j The section 704-5 includes the accumulator RA register 704-50, the quotient QA register 704-2 and the temporary index (RTX) register 704-54 utilized by the control logic unit 704-1 Additionally, it includes a group of eight index (X0-7) registers included within block 704-51. These 60 registers are loaded via the ZRESA bus in execution unit 714. The selection of the register to be loaded is controlled by the contents of the RR13X13 register 704-189. It will be noted from Figure 3.

that selection of outputs from the registers of block 704-51 is controlled by the contents of botChe 33 GB 2 080 989 A.33_ RWXA and RRUB registers 704-158 and 704-189 respectively. The contents of_pro_gram visible registers RA, RQ, XO-7 and RTX are read out to the unit 704-3 via a ZXA2 switch 704-56, a ZXOB switch 704-57 and a ZX switch 704-58. From there, the register contents can be transferred to execution unit 714 or to cache unit 750 via the WO switch in unit 704-3.

As seen from Figure 3j, the output of ZXA2 switch 704-56 is applied via an AND gate 704-61 and an OR gate 704-62 in accordance with the contents of RRDA register 704-158.

The selection of outputs from the above mentioned switches are controlled by the contents of the RRI)XA register 704-158, the FNUM flip-flop of block 704-104 and the RTYP register 704-160 in addition to bits 55-77 (ZX field). The ZM2 switch 704-56 provides for the read out of the upper or lower 18 bits of RA and RQ registers 704-50 and 704-52 for address modification. The selected 10 output signals from the ZXA2 switch and the ZXOB switch are applied to the ZX switch together with the RAAU, RTX and RIC register signals as shown.

The ZX switch selects as an output, bits of the RA/R0/X registers for a 9bit character string via a first position, X/RA/RQ bits for a 6-bit character string via a second position, RA/R0/X bits for a 4-bit character string via a third position and X/RA/RQ bits for word type modification.

Positions five, six and seven are used for selecting the contents of the RAAU register, RIC rq_gister and RTX register respectively. A further W2 switch 704-59 provides a second path to the unit 714 for read out of the program visible registers via the lines ZEBO-35. A similar path to the unit 728 is provided via the lines ZAQO-35.

The section 704-4 includes the registers and switches used for transferring commands and data 20 to the cache 750. Such transfer operations normally require at least two cycles, one for sending an address and another for sending the data bits 5-8 of a command word are derived from the output of a four position switch 704-40. This switch receives a first constant value via a first position, the contents of a RM register 704-42 via a second position, a second constant value via a third position and a third constant value via a fourth position.

Bits 1-4 of a command are applied by the circuits of block 704-1 to an OR gate circuit 704-44 together with bits 5-8. The OR gate 704-44 also receives via a ZADO switch 704-46 bits 1-8 of an RADO register 704-48. The RADO register 704---m-48 is an address and data out register vMich receives via a first position of a ZADOB switch 704-48 a logical (virtual) address from address preparation unit 704-3 via the lines ASFAO-35 and data output signals from the EU 714 via lines 30 WES130-35. The postions of the ZADOB switch 704-48 is under the control of the FIVITD field for small CU format and the RADO field in the case of large CU format.

As seen from the Figure, either the ZM 1 -8 bits or the ZADO bits 1-8 are applied as outputs to the RADO/ZADO lines as a function of the state of control signaf [RADO- ZADO. Bits 0 and 1 are always binary ONES while bits 10-35 are furnished by the RADO register 704-46.

Additionally, the unit 704-5 of the preferred embodiment includes a four position selector ZREG switch 704-53 which is controlled by the coding of the CCSR field. The output of the ZREG switch is used to load the RREG register 714-42 with constant values or with signals corresponding to bit positions 24-26 of the RBIR register 704-152. On a next cycle, signals corresponding to the contents of RREG register 714-42 are transferred to the RRDX13 register 704-189. In the case of 40 i'nstructions which reference COS codes specifying instructions within the STR-SGI- or STR-DBL classes, the same signals are transferred to the RWXA regsiter 704-158. Further, the contents of RREG register 714-42 may be loaded into RBASA register 704-156 under microprogram control.

Execution Unit 714-Figure 3g The unit 714 incudes as major units, addressable temporary register banks 714-10 and 45 714-12, an arithmetic logic unit (ALU) 714-20, a shifter 714-24 and a scratchpad memory 714-30. Additionally, the unit 714 includes a number of multiposition data selector switches 714-15, 714-17, 714-22, 714-26, 714-28, 714-34, 714-36 and 714-38 to provide flexibility in selecting operands and output results.

In operation, the operands are selected via the ZOPA switch 714-15 and ZOPB switch 714-17 50 from one of the registers of the banks 714-12 and 714-10 or from other input lines such as ZEBO-35 or RDIO-35 as shown. The ALU 714-20 and shifter 714-24 performs operations upon the selected operands and the results are selected via the switches 714- 24, 714-36 and 714-38 to be applied to the output bus lines ZRESA 0-35 and ZRES130-35. Similarly, the contents of a scratchpad location selected via the contents of a scratchpad pad buffer 714-32 can be read out via 55 the switches 714-34, 714-36 and 714-38.

The selected output results or other data are thereafter loaded into other registers within processor 700 including the temporary register banks 714-12 and 714-10 or the scratchpad memory 714-30 of execution unit 714.

* In greater detail, the sources of operands are identical for both the ZOPA and ZOPB switches 714-15 and 714-17. The selection of switch position for the ZOPA switch and ZOPB switch is under the control of bits 9-12 and bits 13-16 of the microinstruction word. The ALU 714-20 performs logical, decimal or binary operations upon the selected operand data under the control of bits 24-28 of the microinstruction word of Figure 6a.

34 GB 2 080 989 A 34 The shifter 714-24 is a combinatorial loqjc network used to aliqp, shift or rotate binary data - under microprogram control. The input data signals from the ZSHFOP and ZEIS switches 7141-28 and 714-22 can be viewed as being concatenated to form a single double word input. The shifter 714-24 provides a 36-bit output shifted in accordance with the shift count. The ZSHFOP switch 714-28 is controlled by bits 24-25 of the microinstruction word while the shift count is established 5 by the sequence control constant fields (bits 138-143 of the microinstruction word of Figure 6a which is appropriately selected via the auxiliary arithmetic control unit 722. For the purposes of the present invention, the ALU 714-20 and 714-24 may be considered conventional in design.

The scratchpad memory 714-30 provides a working space for storing various data required for the execution of certain instructions as well as various constants and descriptor values. For example, 10 octal locations 10-15 are used to store an edit instruction table value required for carrying out edit operations. Writing into the scratchpad memory 714-30 involves first loading the RSPB buffer register 714-32 with input data applied via the ZRESB switch 714-38. During a next cycle, the contents of the register 714-32 are written into the location specified by the signals applied to the ZPSPA 0-6 lines by the AACU unit 722. Writing takes place when bit 22 of the microinstruction word (RSP field) is 15 forced to a binary ONE.

As concerns the other switches, as mentioned, the results produced by the unit 714 are provided via the ZALU switch 714-26, the BSPD1 switch 714-34, the ZRESA switch 714- 36 and the ZRESB switch under microprogram control. The ZALU and ZSM switches provide a first level of selection to the ZRESA and MES13 switches which provide a last level of selection. Since both the ZRESA and 20 ZRESB switches have identical input sources, they can provide the same output data. The selection of ZALU switch data is under control of bits 30-31 (ZALU field) while the selection of ZSM data is under control of bit 23 (ZSM field). The selection of ZRESA and ZRES13 data is under the control of bits

17-18 and bits 19-20 respectively of the microinstruction word of Figure 6a.

The registers of banks 714-12 and 714-10 are addressed independently by bits 3-5 (TRI--- 25 field) and bits 6-8 (TRH field) respectively. The first bit in each field specifies whether one of the four registers is to be addressed while the other 2 bits select the register to be addressed. Lastly, a four position switch 714-40 is used to load a RREG register 714-42, with constant values or with signals corresponding to bit positions 24-26 of the RBIR register 704-152.

Character Unit 720 -Figure 3h It is seen that the unit 720 includes a bank of 4 registers 720-10, a number of registers 720-22, 720-24,720-28, 720-30, 720-42,720-46, 720-54,720-63, 720-64,720-68 and 720-70, conversion logic circuits 720-27, adder networks 720-32 and 720- 34, comparator network 720-72 and a number of decode r/detector networks 720-36,720-38, 720-44, 720-48, 720-50, 720-56, 720-58 and 720-74 interconnected via a number of multiposition 35 selector switches 720-26, 720-40, 720-62, 720-12 through 720-20. The control and selection of such switches and the strobing of the various registers is under the control of a number of flip-flop circuits included in block 720-80 and a pair of zero detector circuits 720-82 and 720-84.

The RCH bank of registers 720-10 are used as operand buffer registers for storing information received from the EU 714 via the MESA lines 0-35. A first register (OP 1) is used to store the operand 40 specified by descriptor 1 or data sent to unit 728 or unit 722. A second register (OP2) is used to store the operand specified by descriptor 2. Third and fourth registers (TABLE ENTRY 1, TABLE ENTRY 2) are used to store edit insertion table entry values obtained from EU 714.

The F1M 1 register 720-28 holds the actual character position data for descriptor 1 which is used to select a character to be selected by MU switch 720-12. The RM2 register 720-30 holds signals designating the character position data of descriptor 2. The contents are used to select a characterfrom switch 720-14.

The ZClU and ZCV switches 720-16 and 720-18 are under the control of the MU and ZCV flip flops of block 720-80. The RCN 1 and RM 2 registers 720-28 are loaded under the control of the M 1 and M2 flip-flops of block 720-80 in response to signals generated by decoder 720-56. This is 50 done as a function of the character type (4, 6 or 9-bit characters) defined by the contents of the RTFl and RTF2 registers 720-42 and 720-46 and the starting character position signals generated by the conversion logic circuits of block 720-27. The circuits of block 720-27 convert signals ZCNO-2 applied via switch 720-26 corresponding to an input character position value into an output character position. For 9-bit characters, there is no conversion necessary (i.e., input character position = output 55 character position).

The two bit RTF1 register 720-42 holds the character type information relative to descriptor 1 while the two bit RTF2 register 720-46 holds the character type information for descriptor 2. The one bit RTF3 register 720-52 holds the character type information for descriptor 3. When descriptor 3 consists of 9-bit characters, the detector 720-50 sets the RTF3 register to a binary ONE. In all other 60 cases, the RTF3 register is set to a binary ZERO. As seen from the Figure, these registers are loaded via switch 720-40.

The five bit RMOP register 720-70 stores the "microope ration- values required for processing an edit instruction while the 4-bit RIF register 720-63 stores the information field (IF) values for such

GB 2 080 989 A 35 instructions. The 9-bit RCD register 720-64 is used during certain compare instruction operations for storing a first operand value. The 5-bit FTE8 register 720-68 stores the 5 most significant bits of the eighth edit insertion table entry value in response to a load signal generated by decoder 720-74 in response to a load command. The REFILL register 720-22 is used to store signals received from the unit 704-150 via the lines ZIDD 0-8. The RAD register 720-24 stores character position bits received from the unit 704-3 via the lines AS17A34-36.

The indicator flip-flops of block 720-80 store the result of an operation specified by the contents of the RMOP register 720-70. The indicators include a 2-bit MOP indicator A (MOP [A), a 3-bit MOP indicator B (M0PiB) and a 1-bit END indicator. The MOPIA indicators are decoded as follows:

00 go to MOP execute operation 10 01 go to LOAD MOP operation Test MOPIB 11 N/A.

The MOPIB indicators provide additional status when the MOPIA indicators have the value "1 W' 15. They are decoded as follows:

000 test the state of a length 1 indicator for underflow (L1 UW set when the output of the AXI? adder equals 0 means L1 exhausted) and the state of the CN 'I overflow indicator (CN 'I OV0.

001 test the state of a length 3 indicator for underflow (L3UDF set when the output of the AL adder equals 0, means L3 exhausted) and the state of a CN3 overflow indicator (CNLOW) 20 which is set when the output of the AP adder equals 0.

test the states of the LlUDF, W 1 OW, L31)DF and CWOW indicators.

011 decrement by 1, the length 2 value and test the states of the L3L1W and CWOW indicators during a first cycle and test the states of a length 2 underflow indicator (L2UDF). and the Cl\120W indicator during a second cycle. 100 test the states of the L3U1)F, CN30V17, L1 UDF and CN 1 OW indicators during a first cycle. Transfer the contents of the RAA11 register to EU 714, decrement the length 3 value by 1 and increment the W3 value by one during a second cycle. During a third cycle, test the states of the L3LID17 and CWOW indicators. 101 load the table entry value. 110 change the table values.

111 N/A.

The END indicator is set to indicate that the operation specified by the MOP value is complete.

The Auxiliary Arithmetic and Control Unit (AA CU) 722 -Figure 3i The AAW 722 includes 3 parallel adder networks 722-2, 722-6 and 722-8 designated 35 6erein as a pointer adder network, an exponent adder network and a length adder network respectively.

The pointer network 722-2 includes two banks of 4 registers (RPO-RP3 and RP4-RP7) 722-20 and 722-22. Each bank has its own multiposition switch (722-23 and 722- 24) for selecting the data to be written therein and a pair of four position output switches for selecting the data to be read therefrom (i.e., switches 722-27, 722-28 and 722-29, 722-30). Additionally, bank 722-20 has 40 a second input switch 722-32 whose output feeds the ZRPA switch 722-23 and provides for the selection of additional input data.

The ZRPC switch 722-32, the ZRPA switch 722-23 and the register bank 72220 are jointly controlled by either bits 64-68 (ZRPAC field), bits 69-71 (ZRPAC-3 field) or bit 67 (ZRPAC-4 field) depending upon the microinstruction format. The ZRPA switch 722-23 can select one of the 45 outputs from the ZRPC switch 722-32 via a first position, a value for loading a character offset for address modification/loading address register instructions for the character unit 720 via a second position and a character pointer value for a 9-bit character via a third position.

The ZPA switch 722-27 and the ZPB switch 722-28 select data from the RPORP3 register bank 722-20 under the control of bits 59-60 RPA) and bits 61-62 (ZPB) respectively. The ZRP13 50 switch 722-24 and register bank 722-22 are jointly controlled by a single control field depending upon the type of microinstruction format bits 74-78 (ZRPB-0), bits 69-73 (ZRPB), bits 72-74 (ZRPB-3) or bit 68 (ZR13P-4). The ZRPB switch 722-4 can select the output of adder output switch 722-36 via a first position, an information field from the character unit 720 via a second position, a word or character pointer value for a 9-bit character via a third position and a character pointer value for a 9-bit character 55 via a fourth and fifth position.

The ZPC switch 722-29 and the ZPD switch 722-30 select data from the RP4RP7 register bank 722-23 under the control of bits 57-58 RPC field) and bits 67-68 (ZPD field) respectively. AS seen from Figure 3, the outputs from the switches 722-27 through 722-30 are applied to the A and B operand switches 722-25 and 722-26. The outputs of these switches are applied to a pointer 60 36 GB 2 080 989 A 36 adder 722-34.

The ZAPA switch 722-25, the ZAP B switch 722-26 and the adder 722-34 are jointly controlled by a single control field bits 79-84 (AP field) or bits 82-83 (AP-3 field) depending upon the microinstruction format. As seen from the Figure, the ZAPA and ZAPB switches 722-25 and 722-26 select the outputs from the ZPA, ZPC, ZPB or ZPD switches or a constant value for application 5 to adder 722-34.

A ZLX switch 722-36, a ZXC switch 722-38, a RSC register 722-40 and a ZRSC switch 722-42 operated under microprogram control are arranged to provide shift counts to the execution unit shifter. The ZSC svitch 722-38 can also be used for loading data into the RPG-RP3 register bank 722-20 via the ZRPC and ZRPA switches 722-32 and 722-23 or into the RP4- RP7 register bank 10 722-23 via the MPB switch 722-24.

The selection of ZLX switch positions is controlled by bits 48-49 (ZLX field). The ZSC switch

722-38 is used to select one of the outputs of the ZLX switch 722-38 under the control of bits 50-52 (ZSC field). The RSC register 722-40 is loaded with the right most 6 bits from the output of the ZLX switch 722-38 under the control of bit 47 (RSC field). The two position ZRSC switch 722-42 selects which of two sources is to supply a shift count to the

execution unit 714. Bit 84 (ZRSC field) selects either bits 138-143 (CNSTU/L field) or the RSC register 722-40 as a shift count source.

The last group of circuits s[I6own in block 722-2 include a ZAAL) switch 722-44 and a RAAU register 722-46 connected to receive the output of switch 722-44. The ZAAL) switch 722-44 is used for transferring data to the register 722-46. From there the data is transferred via the section 20 704-5 to the execution unit 714 on the ZEB lines 0-35.

The inputs of the ZAAU switch 722-44 are selected by bits 50-52 (ZAAU field). The first position applies a 9-bit character output from the character unit 720 via the lines ZOC 0-8. The second and third positions are used for displaying the outputs from the length adder and exponent adders of blocks 722-6 and 722-8. The RAAU register 7-2-46 is loaded from the ZAAL1 switch 25 722-44 in response to bit 47 (RAAU field).

As seen from Figure 3i, the exponent adder network 722-6 includes a single bank of 4 registers (RXPA-RXPD). The bank 722-60 has a multiposition switch 722-62 for selecting the data to be written therein and a pair of four position output switches for selecting data to be read therefrom (i.e., 30, switches 722-64 and 722-66). The ZXP switch 722-62 and the RXPA-WD register bank 30 722-60 are controlled by bits 59-62 (ZXP field), bits 65-66 ZXP-1 field orbits 75-77 (ZXP-3 field).

A first position of the W switch 722-62 is used to load the exponent result into register bank 722-60. The second position is used to store the result from the length adder 722-8. The next or third position is used for storing exponent values received from the character unit 720. Lastly, the fourth 35 position is used for storing numeric scale factor information received from the RSIR lines 24-35.

The ZXPL switch 722-64 and ZXPR switch 722-65 select data from the register bank 722-60 underthe control of bits 63-64 (ZXPL field) or bit 64 (ZXPL-1 field) and bits 65-66 (ZXPR field) respectively. The outputs from the switches 722-64 and 722- 66 are applied as inputs to an A operand switch 722-68 and B operand switch 722-70 respectively. These switches apply 40 selected inputs to a pair of 12-bit adders (AXP and AXIVI) of block 722- 72 which generate an exponent output value applied to an output ZAXP switch 722-74. A single control field AXP (bits

69-73) controls the operation of the ZXPA switch 722-68, ZXPB switch 72270, the adders, the ZAXP switch -22-74 and the loading of a RE register 722-76.

One adder AXIV1 is arranged to receive the contents of the RE register 722-76 for providing 45 absolute value when the sign of value generated by the AXP adder is negative (i.e., the AXP sign indicator not shown has control over the ZAXP switch selection).

The ZXPA switch 722-68 can select via a first position the contents of the RE register 722-76 or the output from the ZXP L switch 722-64 via a second position. The ZXPB switch 722-70 can select via a first position, a constant value, via a second position binary floating point exponent signals 50 applied to the RDI lines 0-7, via a third position a numeric scale factor value applied to the RSIR lines 24-35, a fourth position the output from the ZXPR switch 722-66 and via a fifth position the output from the ZI-NA switch 722-84.

The third adder network 722-8 for managing operand length data, similar to network 722-6, includes a single bank of 4 registers (RLW -FILN4). The bank 722-80 has a multiposition switch 55 722-82 for selecting the data to be written therein and a pair of four position output switches for selecting data to be read therefrom (i.e., swiches 722-84 and 722-86). The ZLN switch 722-82 and the RNU -RLN4 register bank 722-80 are controlled by bits 59-63 (ZI-N- 1 field), bit 63 (ZI-N-2 field) bits 79-81 (ZLN-3 field) or bits 79-83 (ZI-N-4 field) depending upon microinstruction format.

The ZLN switch 722-82 applies the output of the length adder as an output via a first position, the output of the ZAXP switch 722-74 via a second position and a length field value from RSER lines

24-35 via a third position. Additionally, it applies a numeric length field value from RSIR lines 30-35 via a fourth position, a shift count value from FID1 lines 11-17 via a fifth position and a length value from RCH lines 24-35 via a sixth position as inputs to register bank 722- 80.

65, 37 GB 2 080 989 A 37 The ZI-NA and ZI-NB switches 722-84 and 722-86 select data from the register bank 722-80 under the control of bits 53-54 (ZI-NA field) and bits 55-56 (ZLNB field) respectively as inputs to an A operand switch 722-88 and a B operand switch 722-90 respectively.

The outputs of these switches are applied as inputs to a 12-bit length (AL) adder 722-92. The ZALA switch 722-88, the ZALB switch 722-90 and AL adder 722-92 are all controlled by bits 5 74-78 (AL field). The ZALA switch 722-88 selects as an operand the output of the ZLNA switch via a first position, a constanf field via a second position, the output of the ZPC switch via a third position and a numeric length field via afourth position.

The ZALB switch 722-90 can select as an operand, a constant field via a first position, the output of the ZLN13 switch 722-86 via a second position, the output of the ZXPI- switch via a third 10 position, a shift count value from RDI lines 11-17 via a fourth position, the output of the ZPC switch via a fifth position, the output of the ZPA swich. via a sixth position and bit positions 6 and 7 of the ZPC switch 722-29 via a seventh position.

The unit 722 includes another group of circuits for furnishing a scratchpad address to unit 714.

The circuits include a ZSPA switch 722-100, a RSPA register 722-102 and a ZRSPA switch 722-104, each controlled by bits 48-49 (ZSPA field), bit 47 (RSPA field) and bits 50-52 (ZRSPA field) respectively. The ZSPA switch 722-100 can select as an output, bits 91-97 corresponding to a scratchpad address field via a first position and the output of pointer adder 722-34 via a second p'tion.

osi The ZRSPA switch 722-104 can select as an output, the contents of register 722-102 via a 20 first position, a scratchpad address field via a second position and a descriptor value applied from the

RSIR lines 32-35 via a third position and a value from the RSPR register of unit 704-150 via a fourth position. Additionally, the unit 722 includes a pair of registers 722-106 and 722-108 which are loaded with signals corresponding to bit positions 21-23 of RSIR register 704-154. One register is loaded when bit 53 of the microinstruction word of Figure 6b or the FPOP flip-flop is a binary ONE. The 25 registers are selected for loading in accordance with the states of the RDESC register 704-140 (00 or = R1 DW; 011 = R2DW).

The various control field signals used by the AACU 722 are derived from a decoder 722-110 which receives as inputs, the various microinstruction word bits loaded into a register 722-112.

CACHE UNIT 750 -Figure 4 General Description

The cache unit 750 is divided into five primary sections: a command buffer section 750-1, a control section 750-3, a cache directory section 750-5, a cache storage section 750-7 and an instruction buffer section 750-9.

Command Buffer Section 750-1 The command buffer section 750-1 includes a four word write command buffer 750-100 and a four word read command buffer 750-102 which are addressed via the counters 750-104 and 750-106. The write ZAC buffer 750-100 provides storage for a single ZAC write command while the read ZAC buffer 750-102 provides storage for up to four read ZAC commands.

The processor 700 transfers commands via the RADO/ZADO lines of interface 605 through the 40 first position of a selector switch 750-110. The processor 700 transfers cache command information via the DMEM and DSZ lines through the first position of a selector switch 750-112. The states of these lines are held or stored in a register 750-114. As seen from the Figure, this information is also written into the buffers 750-100 and 750-102.

In addition to the cache command signals, the processor 700 sets a DREQCAC line. The processor 45 700 sets other control lines (e.g. HOLD-C-CU, CANCEL-C, CAULLISH, BYPASS- CAC, READ IBUF, READ EVEN) when it wants to have the cache unit 7 50 perform other types of operations.

The states of the other control lines are decoded by a decoder 7 50-116 whose output is used to enable the ZAC buffers 750-100 and 750-102. Additionally, the processor 700 transfers zone bit signals for certain types of write commands via the lines M0-3. These signals are loaded into a 50 R= register 750-132 via a switch 750-134. From there, the contents are applied via a switch 750-136 to a set of byte CBYSEL lines. Additionally, the signals on the DZO lines are applied to the MITS lines via a switch 750-139. Other zone signals (bits 5-8) are loaded into an RC address register 750-140 and thereafter applied to another set of byte CBYSEL select lines via a switch 750-142.

A plurality of busy bit registers 750-120 and 750-122 are used to determine which of the locations in the RZAC buffer 750-102 are available. The states of these registers are decoded via a priority decoder network 750-130 which selects the first available buffer location. The value developed is stored in the register 750-106 and is used as a write address for the read ZAC buffer 750-102. When the cache request involves doing a backing store (MEM memory) fetch (cache miss 60 signaled by the state of signal BSPD), the appropriate busy bit or both busy bits are set in accordance with the number of SIU responses (ARDA signals) which will be generated. The busy bits are set by signals applied to a pair of lines SETBOTI-IBSY and SETONEBSY from a decoder, not shown, which 38 GB 2 080 989 A 38 decodes the particular command resulting in the application of a signal to one of the BSY lines. For example, a read single command (not bypassed) causes two SIU ARDA responses, each response for bringing in a pair of words. Thus, both busy bits are set. In the case of a read single bypass command, there is only one SIU ARDA response. Hence, only one busy bit is set. Resetting of the busy bits takes place in response to the ARDA line via a RSPB register 750-124 which receives signals from the SIU via the RMIFS lines.

In greater detail, the contents of registers 750-120 and 750-122 are set in accordance with the number of ARDA responses as mentioned when a PENBIT signal is a binary ONE (i.e., the pending bit corresponding to the block is not set). The decoder circuit 750-130 decodes the states of the busy bits and sets counter register 750-106 to the appropriate address value specifying the next empty 10 location within read RZAC buffer 750-102.

The same address signals PRACWO-1 are also applied to a second position of the switch 750-139 in the case of read commands. From there, the signals are loaded - into a 4-bit MITS register 750-138 and applied to the MITS lines. The main memory 800 operates to return the coded signals to cache unit 750 via the MIFS lines upon transferring the requested pairs of data words of a block.

Thereafter, the signals are loaded into a 4-bit RMIFS register 750-125 and then into the RSPB register 750-124 when the control state signal THCF13 is a binary ONE. The received value causes the resetting of the appropriate busy bit indications stored in registers 750- 120 and 750-122.

It will be noted that the RMIF bit signals 2 and 3 are used to address read RZAC buffer 750-102 for read out of the appropriate command. Additionally, as explained herein, signals from an out pointer 20 circuit (COUT), not shown, are used to access commands stored in read ZAC buffer 750-102. The busy bit indications stored in registers 750-124 and 750-126 are applied as inputs to the exclusive OR circuits of block 750-132. These circuits are operative to generate output signals indicative of the number of busy bits set. These outputs are in turn applied to different positions of a 4 position selector switch 750-133. By selecting the appropriate position or location, in response to the RMIFS bit signals 25 2 and 3, the switch 750-133 provides output signal SECIRCV whose state determines when the cache unit 750 has received the second pair of words of a block. The SECRCV signal is applied as an input to block 750-3.

The outputs of the write ZAC buffer 750-100 and read ZAC buffer 750-102 are applied to different ones of a group of two position switches 750-150, 750-152, 750- 154, 750-156 and 30 750-158. The output of ZAC switch 750-150 is loaded into a SIU output register 750-174 via the switches 750-170 and 750-172. The output from the ZAC switch 750-152 is loaded into a pair of data'register 750-180 via the switches 750-177 and 750-178.

The outputs of switches 750-154 and 750-158 are applied to a further switch 750-160 and stored in a holding register 750-162. The output of switch 750-156 is applied to a decoder 750-166 togetherwith the DMEM outputs of switch 750-160. The other outputs from this switch are applied to a decoder 750-168. Additionally, the output of the switch 7 50-158 is applied to a decoder 750-164.

The decoder 750-166 decodes the cache commands received from processor 700 via the DMEMO-3 lines and those read out from the buffers 750-100 and 750-102 and generates signals 40 for transferring commands to the cache storage 750-7 and directory 750-5. That is, the cache decoder 750-166 is used to control what information will be written into the cache storage 750-7 from the processor 700. The decoder 750-168 decodes the states of the BYPCAC and DSZ1 signals.

It will be noted that the source of these last mentioned signals corresponds to processor 700 or switch 750-154.

The decoder 750-164 decodes the commands read out from the buffers 750100 and 750-102 and generates signals for transferring commands to MEM memory (backing store) via the SIU 100. That is, the S decoder 750-164 is used to control the sending of information from the command buffers 750-100 and 750-102 to the SIU.

Additionally, the ZPSW switch 750-178 via a first position selects the ZAC command from the 50 processor 700 on the RAD0/ZADO, lines for transfer to the SIU 100 on the DTS lines via the switch 750-172 or writes the main memory data into cache storage 50-7 via the RDO, RID1 data registers 750-180. The second position of the ZPSW switch 750-178 applies the data output of the ZALT switch 7501 77 to the DTS lines (ZAC data) or writes the main memory data from the DFS lines into cache storage 750-7 via the RDO, RID1 registers 750-180 or transfers the ZAC commands to the 55 processor 700 via the W1 lines.

The ZACSW2 switch 750-170 is used to transfer a ZAC command (first position) or data from the ZAC buffer to the SIU 100 via the DTS lines (second position).

Control Section 750-3 This section includes a number of control state flip-flops which generate signals for sequencing 60 the cache unit 750 through the required cycles of operation for processing the various commands.

Additionally, the section includes the necessary logic circuits for generating the required control signals during the required cycles of operation. For the purposes of the present invention, these circuits may be' imnlemented in a conventional manner. Therefore in order to simolifv the descriotion hereifi,.o,n[y a bii6f 39 GB 2 080 989 A 39 description and the Boolean expressions will be given for certain control state flip-flops and control logic circuits as required for an understanding of the operation of the present invention.

The control state flip-flops generate a series of timing sequences which control the following data transfer sequences:

(1) processor to cache, SIU (operation to cache and to SM; 5 (2) processor to SIU (transfer write data to SILl):

(3) ZACBUF to cache (operation to cache); (4) ZACBUF to SIU (operation to SM; (5) processor to ZACBUF (write data saved in buffer); (6) SIU to cache, processor (2 words transferred); 10 (7) SIU to cache, processor (1 word transferred).

The transfers utilize the following flip-flops.

Control State Flip-Flops The OATB flip-flop is the first flip-flop set in a first sequence which enables a transfer information from the SIU 100 to cache 750 and to the processor 750.

The OATB flip-flop is set for one cycle in accordance with the following Boolean expression: ARDA.DPFS.

The THCFD flip-f lop is the next flip-flop set in the first sequence which enables the information received during cycle OATB from the SIU 100 to be transferred to processor 700 via the ZM lines. The THM flip-flop is set for one cycle in accordance with the following Boolean expression:

SET: OETF = ARDA. DPFS. 20 The UG COGTH flip-flop when set permits the setting/resetting of a F/F bit, the setting of a pending bit, the setting of RR bits, writing MSA into the address of the directory section and writing data for write- single command into CACHE memory. It is set and reset in accordance with the following Boolean expressions:

SET: HOLD.SET-COGTH 25 RESET: (550 GM: BSY1.NO-HOLD-CAC.CACBSY1 + NO-HOLD-CAC The UGSOGTH flip-flop is the first set in a CPU to SIU sequence. When set, a first data word is put on the DTS lines. It is set for one cycle in accordance with the following Boolean expression:

SET HOLD. DWRT wherein DWRT = CWRT. SNG + CWRT. DBL + CWRT. RMT. 30 The CAOPR flip-flop is set in response to the read for an AOPR response. It is set for one cycle in accordance with the following Boolean expressions:

SET SSET-IN.CI-D-IBUF(C13YP-CAC + BPSD) + CPR-RD.

CBYP-CAG.UP-SD + (CRD-SNG + CR13-DI3LMC13YP.CAC + BPSD) + CRD-CI-R + CRD-RIVIT + CMT-SNG + CWRT-DBL + 35 CWRT-RMT.

The CPR-FF flip-flop is used for determining when the cache unit will respond to a DREQ-CAC signal from processor 700. When this flip-flop is set to a binary ONE during a previous cycle, the cache unit will not respond to a request except in the cases of PREREAD, INST-Fl, INST-F2, LDGUAD, RD-SINGLE or RD-DBL type commands. It is set and reset in accordance with the following Boolean 40 expressions:

SET (CINST-Fl + CINST-F2 + CLD. QUAD + CRD.DI31---+ CRD.SNG).

(CBYP-CAC-BPS5)+CPR-RD-CBYP-CAC.BPSD.

RESET: HOLD = RD-BS' The R13PSD flip-flop is used for turning off the processor 700 in the case of HOLD-ON-MISS or 45 BYP-CAC condition. When the data comes back from the SIU 100, this flip- flop is reset except for an INST-Fl cycle. In the case of IF-1 after 4 words have been received from the SIU, this flip-flop is reset. It is set and reset in accordance with the following Boolean expressions:

SET SSET-IN. HOLD-C;-N. CRP-RIVIT + CRD-CLR + (CINST-Fl + CR1)-SNG + CRD-DBL). (CBYP-CAC + BPSD) 50 GB 2 080 989 A 40 RESET: (HOLD) = THICM. SEC-RCV. Cl NST-F 1 + DATA-RECOV.

INST-171-FF.

The ZC-DL flip-flop is the first set to a binary ON E for initiation of a ZAC buffer to cache ti ming sequence. This flip-flop remains set until all requests requiring completion of such sequences have been 5 processed. It is set and reset in accordance with the following Boolean expressions:

SET SSET-IN. PENBIT + UGCOGTH. CAC-BSY-1 + P R E-0 K. CAC-B SY 1 + TLTH M. CAC-B SY 1 RES HOLD = HOLD-CAC + CAC-BSY-1 + PREOK + UGTLTHM + PENBIT-WAIT.

The PRE-OK flip-flop is the first set to a binary ONE during the ZAC buffer to cache timing 10 sequence. It is set and reset in accordance with the following Boolean expressions:

SET ZC-DL-HOLD-CAC.CAC-BSY-1.PRE.OOKK. K.

TLTHM. PENBIT-WAIT.Ufl RESET: HOLD=HOLD1 CAC.CAC-BSY1.

The UGOK flip-flop is the second set to a binary ONE during the ZAC buffer to cache timing 15 sequence. This flip-flop enables operations similar to those performed during a DREQ-CAC cycle. It is set and reset in accordance with the following Boolean expressions:

SET PRE-OK.CAC-BSY1 -HOLD-CAC RESET: HOLD = HOLD-CAC. CAC-BSY1.

The PENBIT-WAITflip-flop is set to a binary ONE when a read type request specifies the same 20 address as a previous request for which all of the data has not been received from main memory. It is re set when all the outstanding read requests have been processed. It is set and reset in accordance with the following Boolean expressions:

SET: SSET-IN-PENBIT RESET: HOLD= RDBSY.

The PENBIT-FI7 flip-flop is set to a binary ONE in response to a read single or read double request specifying the address of a previous read request whose data has not been received from main memory. It is reset during a P RE-OK cycle of operation. This flip-flop is used for stopping the operation of the processor. It is set and reset in accordance with the following Boolean expressions:

SET SSET-IN. PENBIT. (CRD-DBL + CRD-SNG) RESET: HOLD = PRE-OK + HOLD-CAC + CAC-BSY-1.

The TLTHM flip-flop is the third set to a binary ONE during the ZAC buffer to cache timing sequence. This flip-flop is set in response to a read double command following an OK cycle of operation. It is set and reset in accordance with the following Boolean expressions:

SET: MCAC-BSY1.(13PSD + CRD-DBL) RESET:" HOLD = HOLD-CAC. CAC-BSY1.

35, The FRD-DBL flip-flop is used for establishing TLTHM cycle timing. When CAC-BSY1 is forced to a binary ONE during the TLTHM cycle, a flip-flop MBL-FF is set by the FRD-DBL flip-flop in the case of a read double command. This enables the cache unit tdstop the operation of the processor when it is unable to forward a second word to the processor during the TI- THM cycle. The FRD-DBL 40 flip-flop is set for one cycle in accordance with the following Booiean expression:

SET: CRD-D13L.

41 GB 2 080 989 A 41 CONTROL LOGIC SIGNALS 1. The CPSTOP signal is the-signal which is used to turn off the processor 700.

CPSTOP = F13PS1) = REG CAC. [RIDTYP. RZAC-ALL-BSY + PRFF. (PR-RD-+_ INST-F2 + LDQUAD + RD-SNG + RD-D60 + CAC-BSY1 + CAOPR + UGCOGTHI + R13PSD + DBL.FF + PENBIT.FF + (RD-IBUF/7-DI.CAC-BSY-1) + (RD-IBUF/ZDI.

LD-QUAD-FF) + (UGCOGTH. RD-DBL. CAC-BSY1).

2. The CAC-BSY 'I signal indicates when the cache unit is busy.

CAC-BSY1 = OATB + THUD.

The [F/E-WRT signal is a write enable signal for setting and resetting the full/empty bits.

[F/E-WRT = CAC. BSY1. MCOGTH). UGSOGTH. RD-DBL. BYP-CAU.

DLY-13PSD.ONST-F2 + LD-GUAD).BYP-CAC.DLY-BPSb.

4. The [PEN 1-WRT signal. is a write enable signal for setting the operation pending bits.

1 [PEN1-WRT = CAC-BSY 1. (UGCOGTH). (INST-F2 + LD-QUAD + PR-RD + RD-SNG.DLY-BPSD+RD.DBL.DLY-BPSC)).

5. The [.PEN2-WRT signal is a write enable signal for resetting the pending bits when all data associated with a request has been received from main memory.

[PEN2-WRT = THCFD. SEC-RCV. (INST-F2 + LD-QUAD + PR-RD + RD-SNG + RD-DBL.-EY-P-CAC). 20 6. The RZAC-ALL-BSY signal indicates the busy status of the RZAC buffer established in accordance with the states of the busy bits.

RZAC-ALL-BSY = MB13-00 + R1313-01). (R1313-1 0 + R1313-1 1).

(R1313-20 + RB13-2 1) - (111313-30 + RBB-3 1).

7. The [RMIFS signal is a write strobe signal which allows the multiport identifier bits to be 25 stored when data or status information is received from main memory. These bits identify which location in the RZAC buffer contains the ZAC word associated with the received data (i.e., the data pertains to which of the several possible outstanding read requests).

[RMIFS = ARDA + AST.' 8. The ALTSWO-DT signal enables incoming data from main memory to be saved in the RDO and 30 RD1 registers.

ALTSWO-DT = CAC-BSY 1.

9. The ALTSW2-DT signal enables data from the ZAC buffer to be transferred to the RID0 and RD1 registers.

ALTSW2-DT = DS-ALT + ALTSWO-DT wherein DS-ALT = DS-1 1 + DS-1 2 + DS-1 3.

10. The signals OPSWO-DT through OPSW2-DT control the W1 switch for transfers of data words from cache to processor 700 via the W1 lines.

OP SWO-DT = f D-1 BU F/ZD1 CP SW 1 -DT = RD-1 BU F/M 1 (R EQ-CAC + U G COGTH). WD S E LO.

OPSW2-DT = RD-IBLIF/M1 + WDSEL1 - (RD-SNG + INST-Fl) REQ-CAC.UGCOGTH.INST-Fl REQ-CAC. UGCOGTH. RIDSNG + REQ-CAC. UGCOGTH DBL-FF 11. Te signals ZACSW1 -LC1 and ZACSW2-LC2 control the switch 750-702 which selects 45 the source address for all cache memory chips. The sources are the processor 700 when receiving 42 GB 2 080 989 A 42 commands, the ZAC buffer and the CADR address register.

ZACSW1 -LC 1 = ZACSW1 -LC2f. CAC-BSY-1 - UGCOGTH. ZACSW2-LC2 = CAC-BSY1 + UGCOGTH.

12. The signal DATA-RECOV enables the processor 700 to recover from a stop condition (e.g. 5 restrobe registers).

DATA-RECOV = THCFD. (CiNST-Fl + CRD-SNG). (FM-IFS-1.WDSELO + THCFD. CRDD13L (FSMIFS-1.WDSELO + FMIFS-1 -WDSELO + FIVIIFS-1. WDSELO + CBYP-CAC) + THM. CRD-RIVIT.

13. The RD-BSY signal establishes when certain state flip-flops are reset.

RD-BSY = RBB-00 + R1313-0 1 + RB13-1 0 + RB13-1 1 + RBB-20 + RBB-21 + RBB-30 + R1313-31.

14. The SSET-IN signal is used to set certain state flip-flops.

SSET-IN-RBPSD.jDBL--FF-PENBiT-FF- GCOGTH.UA-OP3-CAC-BSY1.

[CPR-FF. CPR-RD. CINST-F2. CI-D-GUAD. CRO-SNG.UR-D-DBLI. [CRD-TYP - RZACALL-BSY1 - DREQ-CAC 15. SEC-RCV =R-MIFS-2--R-M-IFS- 3 - MBB - 00 @ RBB-01 + RMIFS-2. RMIFS - 3. [RBB - 10 0 RB13-1 1 + RMIFS-2. RMIFS - 3. [RBB G) RBB-21 + RMIFS- 2. RMIFS - 3. [RBB - 30 0 R1313-3 11 16. The BPSD signal indicates a cache hit condition.

3 BPSD=BYP-CAC. 2: (ZAD010-23=SP-i-00--+14). i=o F/Ei.PEM wherein SP-i-00-1 4 corresponds to the address directory outputs (the saved address bits), F/Ei corresponds to the full/empty bit "i" and PENi corresponds to the pending bit "i". It will be appreciated that in the above expressions that the symbols 0 denotes an AND-operation, + denotes an OR operation, and @ denotes an Exclusive OR operation.

Cache Directory Section 750-5 This section includes a 4 level control directory 750-500 and a 4 level set associative address directory 750-502. The directory 750-502 includes 128 columns, each column being divided into 4 levels, 15 bits in length thereby providing space in each column forfour blocks. The control directory 750-500 includes 128 1 0-bit locations, each of which storesa 1 0-bit word of control information.

The control information for each of the blocks includes two round robin (RR) bits, 4 full/empty (F/E) bits and 4 operation pending bits as shown.

The full/empty bits indicate whether a particular directory address has any significance (i.e., is 40 valid). For a cache hit to occur, the F/E bit must be set to a binary ONE. A binary ZERO indicates the presence of an empty block. The round robin bits provide a count which indicates which block was replaced last. This count is incremented by 1 under the control of the full/empty bits by a counter 750-512 and is used to identify the next block to be replaced. As seen from Figure 3, this operation takes place when the round robin and full/empty bits are read out into a pair of output registers 750-504 and 750-506. The full/empty bits are also read into a register 750-510 which controls the incrementing of the round robin bits. That is, the round robin bits are used after all the full/empty bits are set to establish which of the full blocks is to be used for new data. The resulting value (ADDRRO-1) is applied as an input to switch 750-518. All of the full/empty bits are reset by an initialize signal. The fuli/empty bits can beset via a register 750-516. When the processor 700 issues a read request 50 d 43 GB 2 080 989 A 43 which is a miss, during the state UGCOGTH, a value '1 00W is loaded into the register 750-516. This value is written into the control directory 750-500. On the next request, the value " 11 OW is loaded into the register 750-516 and etc. until all the full/empty bits are set.

The operation pending bits are used to indicate when a particular operation is still outstanding. For example, the pending bits when set indicates that all the read data for a particular block has not been 5 received. Accordingly, during a read operation, when the address directory signals a hit, with the pending bit set, the cache unit 750 halts theoperation of processor 700. Hence, no new request is made to main memory.

The network for setting and resetting the operation pending bits includes a 4-bit buffer register 750-520, a block decode register 750-524 and a decoder 750-512. The registers 750-520, 10 during a write cycle of operation, are addressed by the signals PRZACWO-1 via an address register 7 50-522 and signals M 1 FS2-3 during a read cycle. The block decode register 7 50-524 forces different ones of the output signals 13KDCOD0-3 to binary ONES under the following conditions: (1) If at least one full/empty bit is ZERO, when that bit is set to a binary ONE, the corresponding pending bit is set via the decoder 750-512. When all the full/empty bits are set, the next value for the round robin 15 count is encoded and that bit position within the set of four pending bits is set to a binary ONE. A pending bit is reset via the decoder 750-512 only when the cache 750 has received all of the information (i.e., 4 words) from SIU 100. The contents of the registers 750-520 indicate the position of the pending bit to be reset. The pending bits read out from control directory 7 50-500 are applied as an input to decoder 750-514 for updating as required.

The pending bits are set and reset under the following conditions:

SET INSTF2(13Y1PCAC + CACMISS) + I-DQUAD(BYPCAC + CACHEMISS) + PREREAD(BYPCAE-CACIVIISS) + READSINGLE-CACIVIISS + READDBL-BYPCAC.CACMISS.

RESET: INSTF2 + LDGUAD + PREREAD + RDSNG + IRDDI3L.BYPCAC.

The actual control signals are listed previously.

The address directory 750-502, as mentioned, contains 128 sets of 4 words, each 15 bits in length. Each 1 5-bit word corresponds to the address of a 4 word block in the cache storage section 750-7. Whenever, a ZAC command is processed and involves either writing to or reading from cache unit 750, the 15 bits of the block address contained in the ZAC buffers 750-1 hQ or 750-102 are 30 compared on a "set basis" with the address contents of the directory 750- 502, to determine the presence of a hit or miss condition. More specifically, the directory 750- 502 makes its associations on bits 0-14 of the ZAC address for detection of a hit or miss condition. These bits correspond to the address signals applied to either the ZAC 11-18, 20-2 6 lines or to the ZADO/RADO 10-24 lines selected via an input two position ZACSW switch 750-530.

The address of the directory set is defined by a cache address (CADDLO-6) applied via a three position input switch 750-702. This enables the referencing of 4 block addresses which are read out nd applied as one input to each of a group of 4 comparator circuits 750- 536 through 750-542.

Each of the comparator circuits compares its block address with bits 0-14 of the ZAC address. The results generated by the circuits 750-536 through 750-542 are applied to corresponding inputs of a 40 first group of AND gates 750-544 through 750-550 together with corresponding ones of the full/empty bit signals from register 750-506. A second group of AND gates 750-552 through 750-558 combine the outputs from AND gates 750-544 through 750-550 with signals ZEXT13K0-3 indicative of which block is being selected applied via register 750-518.

The AND gates 750-552 through 750-558 provide a group of output block selection signals. 45 (i.e., signals C13SEL0-3) which are applied as inputs to a cache store 750-700 and to a group of directory hit detection circuits of block 750-560. The circuits of block 750-560 include a group of AND gates 750-562 which logically combine signals indicative of the operation pending bits with the block selection signals, the results of which are "ored" by an OR gate 750-564 to provide a directory hit signal on the BIPSD. The circuits of block 750-560 force the line BPSD to a binary ONE when the 50 address bits 0-14 match the directory contents, the corresponding full/empty bit is a binary ONE, and the corresponding pending bit is a binary ZERO. It is assumed there are error conditions.

Cache Storage Section 750-7 The section 750-7 includes a 2 storage unit 750-700 having 2048 (2K), 40- bit word locations organized into 128 sets of 4 blocks. The unit is constructed from bipolar chips, conventional in design. 55 The cache storage unit 750-700 is addressed by the 7-bit address CADDLO-6 applied via the switch 750-702. The address is stored in a holding register 750-704. This causes 4 blocks of 4 words to be applied as inputs to a group of 1 of 4 selection switches (not shown). The appropriate block (level) is determined by the states of the block select signals applied to the C13SEL0-3 lines. The signals applied to the CBYSELO-7 lines via switch 750-708 provide the appropriate selection of even word and odd 60 word bytes. Between words 0, 2 and 1, 3 and byte selection is independent and proceeds as follows:

44 GB 2 080 989 A 44 OBYSELO (byte 0 select) for words 0, 2 5 CBYSEL3 (byte 2 select) for words 0, 2 CBYSEL4 (byte 0 select) for words 1, 3 10 CBYSEL7 (byte 3 select) for words 1, 3.

The signals applied via lines CWSELO-3 via a decoder 750-706 is used for designating the words. This ensures that the contents of the appropriate bit positions of the group of memory chips which comprise the unit 750-700.

The words of a selected block are applied as inputs to a number of sets of OR (NAND) gates 750-712 through 750-716. Each group of gates select the word of the selected block. The word outputs from the OR gates are applied as inputs to an instruction buffer 750-900 via a second position of a two position switch 750-902 and to the first 4 positions of an output W1 switch 750-720 for forwarding to processor 700. The fifth position of the switch applies the word content of registers 750-180 to processor 700 via a ZBP switch 750-902. Lastly, the sixth position of the W1 switch 750-720 applies the output of the instruction buffer 750-900 via the ZIB lines 0-39.

As seen from the Figure, during a write cycle of operation, the word contents from the register 750-180 are applied as inputs to the unit 7 50-700.

Instruction Buffer Section 750-9 This section includes a 16 word instruction buffer 7 50-700 which receives data inputs from the 30 registers 750-180 via the switch 750-902. As mentioned previously, the outputs from cache storage 750-700 are also written into the buffer 750-700 via the switch 750-902. Control signals and address signals supplied via a switch 750-904 are decoded by a decoder 750-906 and are used to set a read address counter 750-908 and a write address counter 950-910 to the appropriate states. The address outputs of the counters are applied via a switch 750- 912 and 750-914 to the 35 buffer 750-900 and used to provide the appropriate addresses during read and write cycles of operation.

Diagnostic Section 750-10 As seen from Figure 4, the cache unit 750 further includes a diagnostic section 750-10. This section is utilized in conjunction with Pi interface for diagnostic and maintenance operations. As seen 40 from Figure 4, section 750-10 includes a 7-bit counter 750-1000, a pair of multilexer detector circuits 750-1004 and 750-1006 and a decoder cicuit 750-1002.

The counter 750-1000 can be loaded via the lines ZPIDT29-35 with signals corresponding to an address for accessing the locations within directory control 750-500 and directory 750-502 via switch 750-702. The decode circuit 750-1002 in response to signals applied via lines ZP1B9-1 0 45 generates output signals which are applied via lines PWO-3 as one input of the switches 750-532 and 750-534 as shown for selection of a particular block.

The switches 750-1004 and 750-1006 receive the sets of address and status signals from the control directory 750-500 and directory 750-502. More specifically, the switch 750-1004 includes 4 sections each having 4 inputs for receiving a particular combination of the signals RSPENO-3, old pend 0-3, RDR F/E0-3, ADDRRO-1 and RDUR0-1. Depending upon the coding of the signals applied to the ZP[B9-1 0 lines, the combination of 4 signals from one of the 4 sections will be selected for application to the lines WIR1 6A through WIR1 5D.

Similarly, the switch 750-1006 has 4 sections each having 15 inputs for receiving one of the 4 sets of address signals SPOO-1 4 through SP30-14. This switch when enabled by a signal ENWIR1 10 applies a set of upper address signals read out from directory 750-502. Parity bit signals not shown are also applied as inputs to the switch 7 50-1006. The output signals from lines WIRO-1 5 of switch 750-1006 as well as the signals from lines Z131F11 6A through 16D of switch 750-1004 are applied to additional inputs included as part of the OR circuits 750-712. These signals are in turn transferred through the circuits of processor 700 via position 1 of W1 switch 60 750-720 of the unit initiating the P1 command. As explained herein, the initiation, transfer and GB 2 080 989 A 45 processing of PI commands through the PI interface takes place in the manner described in U.S. Patent No. 4,006,466 and 4,017,839 and U.S. patent application serial number 755,907 which are assigned to the same assignee as named herein.

DESCRIPTION OF OPERATION 5 With reference to Figures 1---10,the operation of the present invention will now be described in 5 connection with the processing of an edit instruction having the format of Figure 8a. It is assumed that the edit instruction is coded as illustrated in Figure 8b. This instruction is included in a repertoire of instructions having the capabilities for processing bytes, characters and bit strings termed an extended instruction set (EIS). The instruction has a multiword instruction format. The first word is a basic instruction word containing the operations code 10 which is followed by first, second and third descriptor words. The bits 0-17 contain additional information concerning the operation. More specifically, the bits include two 7-bit modification fields coded to specify any address modifications to be performed on operand descriptors. Here, the fields can be assumed as ZEROS.

Bits 18-27 include the op-code value coded to specify an edit operation while bit 28 is an 15 interrupt service bit which is assumed to have the value 0. Bits 29-35 correspond to another 7-bit modification field coded to specify the address modification to be performed for descriptor 1. It is assumed that this field contains all zeros.

The second word contains an 1 8-bit address for descriptor 1, a 3-bit CNI field coded to specify the original character number within the word being referenced, a 2-bitTA field coded to specify which type 20 of alphanumeric characters are in data and a 6-bit N1 field coded to specify the number of characters or bits in the data string or a register that contains the number of characters or bits. The maximum allowable length is 63. The TA field is coded as follows.

Code Data Type 00 9 bit 25 01 6 bit 4 bit The CN field for 9-bit characters are coded as follows.

Code Character Number 000 0 3 The maximum third and fourth words contain similar information for descriptors 2 and 3 respectively. 35 The edit instruction requires microoperations (MOP'S) to perform the editing functions in an efficient manner. The sequence of microsteps to be executed are contained in storage and are referenced by the second operand descriptor word. Some of the microoperators require special characters for insertion in the string of characters being manipulated. These special characters are ddntained in the edit insertion table stored in the scratchpad memory of unit 714. This table is made up 40 of 8 9-bit characters and at the start of each edit instruction, the processor 700 initializes the table to contain the following values:

TABLE ENTRY 1 2 3 4 5 6 7 8 VALUE 0 + - $,. 0.

The operand descriptor for microoperations (OP2) points to a string of 9b,t characters which specify the microoperations to be performed during the edit instruction. Each of the 9-bit characters has a format which includes a 5-bit MOP field coded to specify the microoperation to be performed and a 4 bit IF field coded to specify either the number of source digits to be manipulated (1 -16), or the number of the particular entry in the edit insertion table to be used depending upon the coding of the MOP field.

The microoperations are terminated normally when the. receive string length becomes exhausted (L3). 50 46 GB 2 080 989 A 46 The different fields of the EDIT instruction are coded as indicated in Figure 8. For further information regarding the subject instruction, reference may be made to the publication -Series 60 (Level W/6000 Macro Assembler Program (GIVIAP)- by Honeywell Information Systems Inc. copyright 1977 order number DD0813, Rev. 0.

For this example, it is assumed that the instruction of Figure 8b is stored in the instruction buffer 5 750-700. Also, it is assumed that the operand data specified by descriptors 1, 2 and 3 is not stored in the cache unit 750 but resides in main memory 800.

Referring to Figure 10, it is seen that the first cycle pertinent to the processing of the edit (MVE) instruction is a [end cycle which corresponds to a last cycle of the previous instruction. This cycle is established by forcing an [END control signal to a binary ONE in accordance with the following Boolean 10 expression: [END = FESC 100. DPIPE 1-4 +... The state flip-flop FESC is a binary ONE when the processor 700 is operating under microprogram control such as during the execution of a program instruction. Signal DPIPE1-4 is a binary ONE when bits 38-40 are coded to specify the restarting of the pipeline wherein the processor's registers are loaded with a new instruction (i.e., type 1). Since both FESC1 00 and DPIPE1-4 are binary ONES, the [END cycle is entered via the circuits of block 704-102.

During the [end cycle, the processor 700, under microprograrn control, transfers signals corresponding to the first word of the edit instruction into the RBIR, RSIR, RBASA, FIRDXA and R29 registers of block 704-150 from the buffer 750-900 via the ZIB lines 0-39. in this example, RBASA, RI'll)XA and R29 registers -are set to ZEROS (i.e.,.the fields corresponding to bits 0-2, 32-35 20 and 29 of the EDIT instruction are ZEROS).

Assuming that the previous instruction was not a transfer instruction, the processor 700 applies a signal to the [RDIBUF/MB line for incrementing by one the read out counter 750-910 of the buffer 750-900 for the read out of the next word of the edit instruction (descriptor 1). Concurrently therewith the contents of the ZIB lines are loaded into the RBIR and RSIR registers in response to signals [SRBIR 25 and [$RSIR generated by decoder 704-106 via switches 704-172, 704-170 and 704-173. Bits 0-2 are loaded into the RBASA register 704-144 and bits 32-35 are loaded into the RRDXA register 704-158 in response to signals [$RBASA and [$RWXA via switches Z13ASA,,704-175, 704-176 and 704-177. Bit 29 is loaded cto the R29 register in response to signal [SR29 via switch 704-183. 1 Assuming that the previous instruction was not a transfer instruction or EIS instruction, the contents of the instruction counter 704-310 are incemented by one by adder 704-312 via position 3 of the ZIC-N switch 704-314 (i.e., 001 value).

Next, cycle FPOA is entered in response to the switching of the EPOA state flip-flop of block 704-102 of Figure 3. The FPOA flip-flop is set to a binary ONE under hardware control in accordance 35 with the following Boolean expression:

SET=HOLD1.(DIBFRDY.51-BFE-MTY.[TR-CPR.DXEDRPTS.DPIPE1-4).

That is, the FPOA cycle is entered following an [END cycle when there is no hold condition relating to the pipeline (i.e., signal HOLD100 = 1), the instruction buffer 750- 900 is not empty (i.e., DII3FEWY00 = 1), it has at least one instruction ready for transfer to processor 700 (i.e., D113FRDY1 00 = 1), the previous instruction was not a store compare instruction (i.e., [STRWROO = 1) or an execute/repeat instruction (i.e., DX11DRPTS00 = 1) and the pipeline has been restarted (i.e., DPIPE1-4= 1).

At this time the RBIR register 704-152 stores the edit instruction opcode field as well as the address modification fields MFl, MF2 and MF3 for descriptors 1, 2 and 3 respectively. During this cycle, 45 the flag flip-flops FID and FRI- are set by signals corresponding to bits 30 and 31 of the RBIR register 704-152 applied via the ZIDD switch 708-180 in response to [ZIDD generated by the circuits of block 704-124. Also, the R29 and RWXA registers 704-162 and 704-158 are set by signals corresponding to bits 29 and bits 32-35 of the RBIR register 704-152 applied via ZIDD switch 704-180. Similarly, the RDESC1 flip-flop is reset to a binary ZERO as a consequence of the FPOA state 50 flip-flop having been set to a binary ONE. The values loaded into these registers are ZEROS as seen from Figure 8b.

Under hardware control, the value -00- is forced into the RDESC register 704-170. That is, the RDESCO flip-flop of register 704-140 is set and reset in accordance with the following Boolean expression:

SET: RDESCO = LARGECU field Misc. Reg + Small CU field FIVITD + DESC1 -(DNUM3EDIT).FPOP.

RESET: RDESCO = FPOA + large CU field + small CU field.

In this case, the RDESCO flip-flop is reset to a binary ZERO as aconsequence of the FPOA state flip-flop 60 of block 704-102 being a binary ONE.

The RDESC 1 flip-flop is set and reset in accordance with the following Boolean expres;fon-:, 47 GB 2 080 989 A 47 SET: RDESC1 = large CU field + small CU field + DESCO.FPOP.1VITIV1 MTR. RESET: FPOA + (DESC1. (DNUM3EDIT). FPOP) + large CU field + small CU field.

Additionally, the contents of the next word (descriptor 1) of the edit instruction applied to the lines ZIB 0-39 are loaded into the RSIR register 704-154 in response to control signal [RSIR. Bits 0-2 are loaded into the RBASA register 704-156 from the ZiB lines while bits 21-22 corresponding to the TA1 field are loaded into the RTYP register 704-160 via the ZIB lines in response to the signals and [$RTYP generated by the circuits of block 704-106.

The TA1 field value of 00 specifying a 9-bit character is loaded into the RTYP register 704-160 10 via switches 704-178 and 704-179. ZEROS are also loaded into the RBASA register 704-156 via switches 704-174 and 704-175. Also, the circuits of blocks 704-108 and 704-128 force line [RDIBUF/ZIB to a binary ONE. This increments by one the read counter 750- 910 for read out of the third word of the edit instruction (descriptor 2).

The op-code signals applied via the RBIR register 704-152 to the CCS store 704-200 cause the 15 contents of the designated storage location to be read out into output register 704-202 upon the occurrence of a clocking signal.

As seen from Figure 3, the contents are coded to contain the following control information:

WSO = 000; WSR = 0100; WSS = 11101 and CCSI = don't care.

Since the field CCSO contains ZEROS, the MUM flip-flop of block 704-104 remains a binary

ZERO. The CCSR field is coded to designate a 4 word field and used to increment the instruction counter by the appropriate amount upon completion of the edit instruction.

The 1 0-bit op-code (bits 18-27) in the RBIR register 704-152 is transformed by the CCS store 25 704-200 into a 6-bit code suitable for controlling and selecting the proper control sequences. The WSS field is decoded by the circuits of 704-100 and thereafter establishes the particular sequence as well as causing the FPOP flip-flop to be switched to a binary ONE. That is, the WSS field when decoded indicates that the instruction type is an EIS DEDIT instruction.

The FPOP flip-flop is set and reset in accordance with the following Boolean expression: 30 S ET: FPOP = [R-O--LDI. ([i-EEDDESC. F-POA. DE1S.MBSITT. DIBFRDY + DESCO. FP OP. DEDIT + DP IP E-6) RESET: FPOP = SET.

In this case, the FPOP state flip-flop is set since no descriptor is needed (i.e., NEEDDESCOOO = 1), the FPOA flip-flop is set (FPOA = 1), the CCS field specifies an EIS instruction (DEIS = 1), the CCS bit 35

OBIT = 0 and the instruction buffer 750-900 is in a ready state (i.e., D113FRDY = 1).

During the first FPOP cycle, the address preparation unit 704-3 generates the address specified by the first descriptor word. That is, bits 0-20 (y) of the RSIR register 704-154 are applied as one input to adder 704-322 (i.e., descriptor address) via switch 704-326 and AND gates in response to R29 register 704-162. This value is added to the contents of the address register selected.by the 40 contents of the RBASA register applied via switch 704-328 when a bit R29 is a binary ONE. Since bit R29 is a binary ZERO, the effective address corresponds to the descriptor address. The output of the switch 704-328 is ZEROS as it is disabled by the state of bit 29. The effective address value is added to an address modification field (X or AR) selected via the ZX switch as a function of the contents of the

RRIDXA register 704-158, RTYP register 704-160 and FNUM flip-flop of block 704-104. Since these 45 values are ZEROS, the address modification field is ZEROS.

The resulting value is then stored in the TEAO location as designated by the contents of the RDESC register 704-144 via switch 704-334. The adder 704-320 adds to the same resulting value a base value stored in a temporary base register specified by the contents of the RBAS13 register 704-144. It is assumed that the base value is ZERO. Thus, the resulting address corresponds to the 50 descriptor address. The ZBASE value is also stored in the TBASEO register via switch 704-332.

In accordance with the present invention, under hardware control, the processor 700 issues a cache pre-read command to the cache unit 750. This ensures that it gets loaded immediately with the required data while the processor 700 continues its processing of the edit instruction. As seen from Figure 9, this command causes a first 4 word block of descriptor 1 data stored in locations 1000-1003 to be read from main memory 800 in parallel with instruction processing so when the processor 700 is ready to utilize such data it will reside in cache. That is, the pre-read command permits data required in the performance of an instruction to be fetched in advance concurrently with the processing of the next descriptor of the instruction. This course speeds up the execution of the operation specified by the instruction during the initial phases of operation (i.e., fetch operands). Thus, the 60 48 GB 2 080 989 A 48 arrangement of the present invention has the effect of speeding up the processor in its execution of the subject instruction.

The pre-read command is generated as follows. The descriptor absolute address is loaded into the RADO register via the ZADOB switch in response to the signal [RADO generated by the decoder circuits 704-124. Additionally, the command bits 1-4 and zone bits 5-8 are applied through the switch 704-40 in place of bits 1-8 from switch 704-46 while bits 0 and 9 are forced to ZEROS.

The bits 1-4 from the RMEM register 704-130 are converted to a command code of 0111 by the decoder circuits of block 704-118. This command code specifies a memory read quad operation. Zone bits 5-8 are set to binary ONES via the input switch 704-40 and are not used for a read.

Simultaneously therewith, the circuits of block 704-108 generate the preread code of---0111---which 10 corresponds to the signals [MEMOTB through [MEM3T13. These signals are generated in accordance with the following Booiean expressions:

[MEMOTB = 0 [MEMM [MEM2TI3 = FPOP. EDIT. DI-MZ(DESCO.FRE11+ [MEM3TB1 DESC1.ME2).

Since the FPOP flip-flop is set, the instruction is an edit, the length is not zero (DLNNZ-1 established by FIGNLEN control flag), descriptor, these signals are binary ONES when either the first flip-flop descriptor field (DESCO = 1) (FE1IN = 1) or second descriptor (DESC1) field being processed has not been exhausted (-E-11 or FE2 = 1). Obviously, these values can be assumed to be all binary ONES at the 20 start of instruction processing.

These signals are therafter loaded into the RMEMO-3 register 704-130 via decoder 704-116. The contents of the RMEMO-3 register 704-130 are in turn applied to the DMEMO-3 lines. Also, the circuits of block 704-108 generate signals which force the RSZ register 704-132 to the value "OW' The contents of this register are applied to the DSZ lines to specify a full word write (not 25 used for generation of preread commands). The decoder 704-120 forces the DREQCAC line to a binary ONE upon decoding the DMEM command stored in the register 704-130. The BYPCAC line can be assumed to be a binary ZERO throughout the example.

During the FPOP cycle, signals corresponding to the TA1 field are transferred from the RTYP register 704-160 via switch 720-42 of unit 720 in accordance with the state of the RDESC register 30 704-140. The signals have a value of---00---signifying that the descriptor 1 data field is made up of 9 bit characters. Also, signals corresponding to the N 'I field representative of the length are transferred from the RSIR register 704-154 via the ZLN switch 722-82 into the RLN1 register of bank 722-80. These signals have a value indicating that the descriptor data field has 16 characters.

As seen from the Figure, the RCN 1 register 720-28 of character unit 720 is loaded with the value "102---corresponding to the M1 field of descriptor 1 applied via the lines ASFA 34-36 and RAD register 720-24 from the TEAO register of bank 704-302 which had stored descriptor 1. This value points to character # 2 of the first data word of description 1 as the starting character to begin processing. The RPO register of bank 722-20 of unit 722 is loaded with the character pointer value ---01---via the lines ASFA33-35 and the ZRPA switch 722-23 for the temporary storage thereof.

Next, signals corresponding to the MF2 field are transferred to the R29 register 704-162, the

RRDXA register 704-158, the FID and FRL flip-flops of block 704-110. Again, the signals are applied via the ZIDD switch 704-185 from bit positions 9-17 of the RBIR register 704-152. As seen from Figure 10, these values are all ZEROS indicating that there is no modification for descriptor 1 data. The RDESC register 704-140 is loaded under hardware control with the value--- 012---for designating a 45 descriptor 2 operation. Here, the RDESCO flip-flop remains reset while the RDESC 'I flip-flop is set to a binary ONE since descriptor 1 has been processed (DESCO = 1), the cycle is a FPOP cycle (FPOP 1) and the instruction is not a memory type instruction (MEM to MEM or MEM to REG- IVITMIVITR 1).

Again, the processor 700 applies a control signal to the [RDIBUF/MB line for incrementing the read counter 750-910 of the buffer 750-900 for read out of the next word of the edit instruction (descriptor 3). The buffer descriptor 2 contents applied to the ZIB lines are loaded into the RSIR register 704-154 while bits 0-2 and 21-22 from the ZIB lines are loaded into the RBASA register 704-156 and the TYP register 704-160 respectively.

At this time, the RSIR register 704-154 contains descriptor 2, the R29 register 704-156 contains ZEROS indicating no address register modification and the RTYP register 704-160 contains 55 ZEROS indicating that the descriptor 2 data field is made up of 9-bit characters.

As concerns the cache unit 750, in response to the DREWAC signal, the preread memory command applied to lines ZPSWAO-39 is written into an empty location of the RZAC buffer 750-102 specified by the contents of counter 750-106. As mentioned, the address of the empty location is determined by the state of the busy bits. This entry is made independently of whether there is 60 a hit or miss condition (i.e., state of BPSD). The read ZAC buffer contents is used on a next cycle to supply the address to be written into the control directory 750-500.

Next, the cache command is decoded by the cache decoder 750-166 to establish which orre(s) i --- - 1 1.1 49 GB 2 080 989 A 49 of the control state flip-flops of block 750-3 is to be set. In the case of a pre-read command, a cache miss results in a directory assignment cycle wherein theaddress is written into control directory 750-500, the full/empty bit is set if not set and the appropriate pending bit is set indicating that the operation is now outstanding. As explained herein, the directory assignment cycle is entered where the UGCOGTH state flip-flop is switched to a binary ONE state. It will be noted that it is the cache unit 750 5 which determines whether the processor 700 continues its processing in accordance with the state of the CPSTOPOO line. In the case of a pre-read command, both the turnoff 1 and turnoff signals are binary ZEROS holding the CPSTOPOO fine at a binary ONE. The state of the CPSTOPOO line enables the continued application of clock pulses to the processor's circuits thereby enabling the processor 700 to continue processing. By contrast, the cache unit 750 stops the operation of processor 700 in the case of 10 a cache road command upon the occurrence of a miss.

In parallel, with the command decoding, the cache unit 750 accesses the directories 750-500 and 750-502 and cache storage 750-700. The directories 750-500 and 750-502 and cache storage 750-700 are accessed using the address signals from the RADO lines 25-33 applied via switch 750-702. The comparison circuits 750-536 through 750-542 compare the address which 15 applied from the RADO-ZADO lines with the directory address. Since the first descriptor data is not in cache, the circuits 750-560 cause the hit-miss signal BSPD to remain a binary ZERO. Accordingly, the UGCOGTH flip-flop is switched to a binary ONE by signal SETCOGTH due to the signals BPSD and CPRRD immediately following the processor request when the control directory 750-500 is to be updated.

During the directory assignment cycle, the address written into the RZAC buffer 750-102 is passed through ZAC switch 750-530 and instead of being compared as in the previous cycle is strobed into directory 750-502. When the command is deferred because data is being received from main memory, an alternate state TILTHM flip-flop is set to a binary ONE. The directory assignment cycle is dropped, the data from memory is stored in cache and the directory search and assignment cycle is 25 reexecuted. Stated differently, the command operation is interrupted and restarted via the alternate TLTHM flip-flop.

During the directory search cycle, before it is determined a hit or miss, the ZAC command is loaded into the SIU output register 750-174 via the ZPSWA switch 750-110 and the ZPSW switch 750-178 (cache unit assumes a miss condition).

During the directory assignment cycle, the cache unit 750 makes a request to the SIU 100 for a memory operation under the control of state flip-flop CAOPR. That is, the CAOPR flip-flop forces the AOPR line to a binary ONE signaling the SIU 100 of the memory request. At that time, the ZAC command is applied to the DTS fines together with the appropriate memory identifier signals and steering signals applied to the MITS and SDTS lines. The memory identifier signals are applied via register 750-138 previously loaded from register 750-106 via switch 750-139. The steering signals are generated in a conventional manner by means not shown for designating the processor 700 as the source of the request. For further information regarding the use of steering signals, reference may be made to U.S. Patent No. 4,006,466.

The SIU 100 signals acceptance of the cache memory request by forcing the ARA line to a binary 40 ONE. Thereafter, it forwards the request to the main memory which fetches the 4 word block of descriptor 1 data. Upon transfer of a first pair of data words, the SIU 100 forces the ARDA line to a binary ONE indicating that the even word of the pair is available on the DFS lines. The SIU 100 also forc6s the DPFS line to a binary ONE indicating a double word transfer. This causes the OATB flip-flop to switch to a binary ONE which indicates that the odd data word is available on the DFS lines. 45 Thereafter, the THCFD flip-flop is switched to a binary ONE.

The first data word is loaded into the RP register 750-179. Also, the memory identifier signals applied to the MIFS lines-by the SIU 100 are loaded into the RSPB register 750-124. Bits 2 and 3 are used to access the ZAC read command in the RZAC buffer 750-102. The address is again applied to the cache storage 750-700 and directories 750-500 and 750-502.

In parallel with accessing the directories and cache storage 750-700, the first data word is loaded into the RDO register 750-180. The second word is transferred to the RP register 750-179 and loaded into the RD1 register 750-180. At this time, both words are written into the cache storage 750-700 at the location specified by the ZAC command. Also, the first busy bit is reset in accordance with the coding of the MIFS 1 -3 signals.

The SIU 100 is operative to transfer the next two data words to the cache unit 750 by again forcing the ARDA and DPFS lines to binary ONES, This again switches the OATB flip-flop to a binary ONE which is again followed by the switching of the THCFD flip-flop to a binary ONE. Again, the signals stored in the MIFS register 750-124 access the ZAC command from the ZAC buffer 750-102 for addressing the directories and cache storage 750-700.

In parallel with the addressing, the next two data words are transferred via the RP register 750-179 into the RDO and RD1 registers 750-180. Thereafter, the words are written into the cache storage 750-700 completing the storage of a first block of descriptor 1 data making it available to processor 700. Since the command is a pre-read command, the cache unit 750 does not enable the M1 switch 750-720 enabling the data words to be transferred to processor 700. Also, in parallel with the65 GB 2 080 989 A 50 writing operation, the cache unit 750 resets the second busy bit in accordance with the MIFS signals and the pending bit indicating the completion of the pre-read operation.

As seen from Figure 9 and the flow chart of Figure 10, processor 700 executes a second FPOP cycle. That is, the FPOP flip-flop remains set to a binary ONE because descriptor 1 has been processed (DESCO = 1), the previous cycle was a FPOP cycle (FPOP 1) and the instruction is an edit instruction (DEDIT = 1). Signals corresponding to Y address value of descriptor 2 (RSIRO-20) loaded into the RSIR register 704-154 during the first FPOP cycle are transferred via the ZY switch 704-326 for combination with inde: (X) or address register (AR) values from ZX switch 704-58 and register bank 704-304 respectively by adder 704-322. Since there is no index or address register modification (MF2 = 0), the values applied to the ZARO = 23 lines and ZXO-20 lines are ZEROS. Thus, the 10 descriptor 2 address value is transferred to the TEA1 location of bank 704-302 selected by the contents of the RDESC register 704-144 and to the RADO register 704-46 via the ASFA lines and adder 704-320. It will be appreciated that the appropriate base value is added to the descriptor 2 address in the same manner as described previously in connection with descriptor 1.

15. As seen from Figures 9 and 10, the processor 700 generates another pre-read command wherein 15 the ZAC command word applied to the RADO/ZADO lines includes the descriptor 2 address value 3000 and a memory read quad operation. This command is forwarded to the cache unit 750 and is processed in the same manner as the other command. That is, since it is assumed that the descriptor 2 data is not in cache, the pre-read command causes the first block of descriptor 2 data to be loaded into cache. As seen from Figure 7, this block includes the data characters of the words at addresses 3000-3003. 20 During the cache units' processing of the pre-read command, processor 700 continues processing.

During the second FPOP cycle, the RT172 register 720-46 is loaded with signals corresponding to the TA2 field via the RTYP register 704-160. Again the---OWvalue indicates that the descriptor 2 data consists of 9-bit data characters. The RI-N2 register of bank 722-80 is loaded with signals corresponding to the N2 field via the ZILN switch 722-02 from the RSIR lines. The value indicates that the length of the descriptor 2 data field is 6 characters as indicated in Figure 7.

Additionally, the RM2 register 720-30 is loaded with the value---112--via the ASFA 34-36 lines and the RAD register 720-24. This indicates that the third character of the first data word of descriptor 2 is the first character in the field to be processed. Also, the RP 1 register of bank 722-20 is loaded with the---11 J character pointer value for the temporary storage thereof.

Signals corresponding to the MF3 field bits 0-8 are transferred from the RBIR register 704-152 into the R29 register 704-162, the RWXA register 704-158, FID and FRIL flip-flops via the ZIDD switch 704-180. The ZEROS values indicate no address modification is required for descriptor 2. The RDESC register 704-140 is forced to store a---102---value designating a descriptor 3 operation (see

Boolean expression).

Again, the [RDIBUF/7-IB line is forced to a binary ONE for advancing the read address counter to point to the next instruction. The signals corresponding to descriptor 3 applied to the ZIB lines are loaded into the RSIR register and R29 register 704-162. Also, the RBASA register 704- 156 is loaded with signals from ZIB lines 0-2. Similarly, the RTYP register 704-160 is loaded with ZEROS via the ZiB lines indicating that the descriptor 3 data field consists of 9-bit characters.

During the FPOP cycle, under microprogram control, the first 4 ASCII characters are transferred from location 14(8) of scratchpad memory 714-30 to the RTRH4 (TR4) register of bank 714-10. Also, signals are generated for testing of the control flag indicators FINDA and FINDC and a conditional vector branch operation R132 established by the TA1 field derived from bits 21- 23 RSIR register 704-754 performed by the circuits of block 701 -1. The indicator testing is not pertinent to this instruction and 45 therefore can be ignored.

As seen from the flow chart of Figure 10, a FESC cycle is entered upon the switching of the FESC control state flip-flop to a binary ONE. The FESC flip-flop is set and reset in accordance with the following Boolean equations:

SET: FESC = [R10-LD1WPOP - SETFPOP).

RESET: FESC = DPIPEO-5.

In this case, the FESC flip-flop is set since the FPOP flip-flop is set (FPOP = 1) and the flip-flop is not going to be set again (SETFPOP = 1) as it is assumed that there is no operation start specified by microprogram control (see Boolean expression - DPIPE field).

This cycle is under microprogram control in which the microinstruction word cycle A = 1 field is 55 utilized. During this cycle, the second 4 ASCII characters are transferred from location 158 of scratchpad memory 714-30 to the RTRH5 (TR5) register of bank 714-10. The descriptor 1 character pointer value stored in the RPO register of bank 722-20 is transferred via the ZPA switch 722-27 and adder A1 722-92 into the temporary storage register RI-N3 of bank 722- 80. Also, the descriptor 2 character pointer value stored in the RP 1 register is transferred via the ZPB switch 722-28 and 60 ZRPB switch 722-24 to the RP5 register of bank 722-22.

Also, indicator storage (history) registers, not shown, included within the branch circuits of block 701 -1 are cleared to ZEROS. These registers are used to store the states of input Group 1 indicators 51 GB 2 080 989 A 51 selected via bits 136-139 of a microinstruction word for testing during a subsequent cycle of operation.

As seen from Figure 10, since the TA1 field tested via the vector branch circuits of block 701 -1 has stored the value---00---specifying 9-bit data characters, the processor 700 enters a B1 cycle of operation. During this cycle, under control of a microinstruction word having a type A = 4 field, the number of characters in a word for the descriptor 1 data field is loaded into the FIXPI3 register of bank 722-60. As seen from Figure 10, this value is 4 for 9-bit characters and is generated by the adder 722-72 in response to a constant applied via the ZXPB switch 722-70.

The descriptor 1 data field length stored in the RI-N 'I register is transferred to the RI-N4 register via the adder 722-92. Also, signals corresponding to the first 4 characters of the edit insertion table 10 stored in the TR4 register of bank 714-10 are loaded into the table entry 1 register of bank 720-10 via the ZRESA switch 714-36.

The processor 700 next enters the B3 cycle and carries out the operations specified by a microinstruction word having a second format. During this cycle, signals corresponding to the length of the descriptor 2 data stored in the RI-N2 register of bank 722-80 are applied to the adder 722-92 and tested for zeros. The resulting indication is applied to certain ones of the auxiliary flip flops of block 701-42 and if ZERO causes the switching of one of the exhaust flip-flops (EXH2) to a binary ONE. This inhibits the processor 700 from reading descriptor 2 during a B7 cycle.

Signals corresponding to the next 4 characters of the edit insertion table stored in the TR5 register of bank 714-10 are loaded into the table entry 2 register of bank 720-10 via the WESA switch 20 714-36. Also, bits 44-46 (PIPE field) are coded to specify a type 6 restart wherein the FPOP flip-flop is switched to a binary ONE during the next cycle of operation. Accordingly, there is a transfer of control to hardware control wherein processor 700 begins a third FPOP cycle of operation for processing descriptor 3.

During the FPOPQ) cycle the address bits 0-20 (Y) of the descriptor 3 read into the RSIR register 25 750-154 during the second FPOP cycle, are transferred into the ICI3A register of bank 704-302 via the ZY switch 704-326 adder 704-322 and the MES13 switch 704-334. Since there are no index or address register modifications specified (i.e., MF3 field = ZEROS), the address value corresponds to the descriptor 3 value of 5000. The same value (Z Base = ZEROS) is also loaded into the RADO register 704-46 via the ASFA lines.

* As seen from Figure 10, the PTH flip-flop 720-52 is set to a binary ONE by the detector 720-50 indicating that the descriptor 3 data field consists of 9-bit characters. That is, the "0W value corresponding to the TA3 field applied via the RTYP register 704-160 are decoded by the detector

720-50 and cause it to switch the flip-flop 720-52 to a ONE. Additionally, signals corresponding to the N3 field are transferred from bit positions 30-35 of the RSIR register 750-154 into the RI-M 35 register of bank 722-80 via the ZLN switch 722-82. The RPO register of bank 722-70 is loaded with the descriptor 3 character pointer value of all ZEROS via the ASFA lines indicating that the descriptor 3 data field starts with the number ZERO character (address 5000).

As seen from Figure 10, the processor 700 under microprogram control tests the descriptor 1 1.ength value stored in the RI-N4.register for ZEROS. This is done via testing one of the status indicator 40 flip-flops of block 70 1 -1 which indicates whether the output of adder 722-92 is ZERO or there was no carry out generated. The conditions mentioned cause one of the exhaust flip-flops (EXH 11) to be set to a binary ONE for subsequent testing.

Next, the processor 700 begins a B5 cycle wherein under the control of a microinstruction word utilizing the TYPEA = 4 format, it transfers the difference between the FIXPI3 register value of 4 corresponding to the number of characters in a descriptor 1 data word and the RILW register value (10), which points the character# 2 as the starting character in the data field. The difference value of 2 generated by adder 722-72 is stored in the W2 register and indicates the number of data characters to be read or processed in the first data word of descriptor 1.

The data field length of descriptor 3 is read out of the RLN 1 register and stored in the RLW 50 register via the adder 722-92 and ZLN switch 722-82 for a ZONED write command. Next, the adder AL = 0 indicator is selected for testing. Next, the RDESC register 704- 140 and the RBASB register 704-144 are set to ZEROS for the reading of descriptor 1 data.

The B5 cycle is followed by a 136 cycle of operation wherein the processor 700 under the microprogram control transfers signals (value 1000) corresponding to the sum of address of the first 55 data word of descriptor 1 from the TEAO register and base value from the TBASEO register generated by adder 740-320 to the RADO register via the ASFA lines. The control unit 704-1 sets the ZAC command code bits 1-4 to a code of 0000 to specify a read single command and forces the DMEM lines to a code of 1000 to specify a cache read single operation.

In the manner previously described, the processor 700 forwards the read command to the cache 60 unit 750. As seen from Figures 7 and 9, this data was previously fetched from main memory 800 and stored in cache. Accordingly, when cache unit 750 decodes the read single command, accesses the directories and cache storage 750-700, the hit-miss detection circuit 750- 560 force the BPSD line to a binary ONE indicative of a cache hit. None of the control state flip- flops are set in this instance. The cache unit 750 conditions signals OPSWO-2 for enabling the transfer of the data word at address 52 GB 2 080 989 A 1000 to processor 700 via the WO switch 750-9 during a subsequent cycle. Thus, the previous processing of the pre-read command by the cache unit 750 eliminates stopping the operation of the processor 700 to wait for the requested data word. This would occur in the case of a read single command where a miss was detected.

Also, the processor 700 subtracts from the descriptor 1 length value (16), the number of characters in the data word (2) via the AL adder 722-92 and stores the value indicative of the number of remaining descriptor 1 characters in the RXPD register of bank 722-60 via the ZXP switch 722-62.

During this operation, if the RI-N4 value is ZERO (ALZ = 1 or ja-rF -out), one of the indicator flip-flops of block 701 -1, (EXH 11) is set to a binary ONE.

Additionally, under microprogram control, processor 700 sets the RDESC register 704-140 and 10 RBAS13 register 704-144 of control unit 704-1 to the value---01---(i.e., the NXTD field). This specifies a read of descriptor 2 information.

The B6 cycle is followed by a B7 cycle upon testing of the length of the descriptor 3 field via an indicator (ALZ) which would have been set during the B5 cycle. Since the ALZ indicator is not set, the processor 700 begins the B7 cycle. The first data word of descriptor 1 (operand 1) previously fetched from address 1000 and applied to the W1 lines 0-35 is loaded into the RDI register 704-164 via switch 704-182. Also, the length of descriptor 1 is read out from the RI- N4 register and stored in the RXPA register via the ZXPB switch 722-70 and adder 722-72. In a similar fashion, a copy of descriptor 3 length is read out from the RI-N 1 register and stored in the Ri-N4 register via the adder 722-92.

The resulting descriptor 2 address generated by summing the contents of the TEA1 and TBASE1 registers generated by adder 704-320 is transferred to the RADO register 704-46. The processor 700 is operative to generate another cache read single command for forwarding to cache unit 750. The command is generated in the manner previously described. However, in this case, the ZAC command specifies the address of the descriptor 2 (operand 2) data (i.e., address 3002) for bringing in the operand 2 data. This data corresponds to the string of control words (MOP) characters of Figure 8. As seen from Figure 9 and as discussed previously, the cache unit 750 previously fetched a block of operand 2/descriptor 2 data in response to a previously issued pre-read command. Therefore, when the cache unit 750 decodes the read single command, accesses the directories and cache storage 750-700, the circuits 750-560 again force the 13PSD line to a binary ONE signaling a--- hit.---It thereafter reads out 30 the first data word of operand 2 which it applies to the ZDI lines in the manner previously described.

Again, under microprogram control (via the NXT13 field), the processor 700 loads the RDESC and RBAS13 registers with the value -0- for selecting descriptor 1 temporary registers.

As seen from Figure 10, the processor 700 begins a B8 cycle wherein a microinstruction word having TYPEA = 2 format is executed. During this cycle, the first word of descriptor 1 (operand 1) data 35 is transferred from the RDI register 704-164 into the OP 1 register of the character unit register bank 720-10 the execution unit ALU 714-20, the ZRESA switch 714-36 on the ZRESA lines 0-35.

Next, the value 4 is subtracted from the character pointer value read out of the RP5 register and added to the value read ofit of the RI-N2 register. This operation is carried out by AL adder 722-92 which receives the appropriate values via the ZI-NA position of the ZALA switch 722-88 and the last 40 position of the ZALB switch 722-90. The result provided by the state of ALZ or no carry out signal indicative of the remaining number of descriptor 2 characters to be fetched, is used to set one of the indicator flip-flops (EXH2) for subsequent testing of an exhaust condition.

Also, the first word of the descriptor 2 (operand 2) applied to the W1 lines by the cache unit 750 is loaded into the RDI register 704-164. The constant value of 120, is generated by the AP adder 45 722-34 and written into the RP3 register of bank 722-20. This value corresponds to the scratch-pad address designating the location in scratchpad memory 714-30 into which the second operand 1 (descriptor 1) data word is to be stored.

The first operand 2 data word applied to the W1 lines from cache unit 750 is loaded into the RDI register 704-164. The CSO adder 704-322 increments by 1 (1 word) the descrilptor 1 address read out 50 from the TEAO register and the sum is restored in the TEAO register. Also, adder 704-320 sums the incremented value to the base value read out from the TBASO register and the resulting address (1001) is loaded into the RADO register 704-46. As seen from Figures 7 and 8, this address specifies the second word-of operand 1 having the 4 9-bit data characters shown in Figure 8.

Again, the processor 700 is operative to generate another cache read single command to cache 55 unit 750. In this case, the ZAC command specifies the address 1001 for fetching the second word of operand 1 (descriptor 1). As a consequence of the pre-read command forwarded to the cache unit 750, this second word also resides in "cache".

As seen from Figure 10, the processor 700 via its test and branch circuits tests the state of the exhaust indicator selected flip-flop EXH 11 via a vector branch operation (i.e., RIDW) register 722-106. 60 Since this indicator is not set, the processor 700 enters a B 13 cycle of operation. During this cycle, the first word of operand 2 is transferred from the RDI register 704-164 into the OP2 register of character unit.bank 720-10 via the execution unit 714.

Next, the AXP adder 722-72 subtracts the value stored in thd RXPB register indicative of the number of characters per word from the present descriptor 1 length value (14) stored in the WD 65 53 GB 2 080 989 A.53 register and stores the result (10) in the RXPD register via the W switch 722-62. Since the output of the AXP adder 722-22 is not ZERO (i.e., AXPZ indicator or no carry signal not ZERO), the exhaust flip flop EXH 11 remains reset. During this cycle, the second word of operand 1 (address 1001) read out from the cache unit 750 and applied to the W1 lines is loaded into the RDI register 704-164.

Also, the constant value 117. is generated by the AP adder 722-34 and loaded into the RP5 register via the ZRPB switch 722-24. This value serves as a starting scratchpad address for transferring operand 2 data to the character unit 720. Lastly, under microprograrn control, processor 700 loads the RDESC and RBAS13 registers 704-140 and 704-144 with the value "00---for selecting descriptor 1 temporary registers.

As seen from Figure 10, the processor 700 enters a two microinstruction sequence which includes 10 cycles B 14 and B 15. This sequence is used to load the scratchpad memory 714-30 with the remaining data characters of opera nd/descriptor 1. The scratchpad memory 714-30 is able to store up to 63 characters. Since the length of the string is 16 data characters or 4 words, the sequence is repeated several times.

During the first pass through the B1 4 cycle, the processor 700 under control of a microinstruction 15 word having a format wherein AAW = 0. transfers the second word of operand 1 from the RDI register 750-164 into the scratchpad input RSPB register via the ZRESB switch 714- 38. Again, the adder 704-322 increments by 1 (word) the contents read out from the TEAO register which is returned to that register. Also, the adder 704-320 adds the incremented value to the contents of the TBASEO register and the result address is loaded into the RADO register 704-46 via the ASFA lines. 20 The address (1002) which points to the third data word of operand 1 is included in another read single command which is generated and forwarded to the cache unit 750. This data word also resides in cache storage 750-700.

As seen from Figure 10, the AP adder 722-34 increments the contents of the RP5 register by 1 and the resulting address of 12Q, for descriptor 1 is rewritten into the RP5 register via the Z13PB switch 25 722-24 and into scratchpad address RSPA register 722-102 via the ZSPA switch 722-100. Under microprogram control (field NXTD), the processor 700 loads the value 102-- -into the RDESC and RBAS13 registers 704-140 and 704-144. This value specifies the selection of the descriptor 3 temporary registers (i.e., TBASEA, ICBA) and is not used until the data words have been loaded into the scratchpad memory 714-30. This value in cycle B '15 to select the descriptor 1 temporary registers (yalue "001 30 for generation of futher descriptor 1 addresses.

As seen from Figure 10, the processor 700 tests for the end or exhaust of the operand 1 data string in a previous cycle via examining the states of the AP adder indicators to detect whether the adder output was ZERO or there was no carry out. Since the operand 1 data string was not exhausted, the processor 700 begins the B 15 cycle. During the B 15 cycle, the AXP adder 722-72 substracts the 35 number of characters per word value stored in the RXPB register from the present descriptor 1 length value (10) stored in the FIXPI3 register and stores the result (6) in the RM register via the W switch 722-62. The resulting length value is tested and since it is still not ZERO, the exhaust flip-flop EXH 11 remains reset.

Next, the third word of operand 1 applied by the cache unit 750 to the WO lines is loaded into the 40 DI register 750-164 and thereafter loaded into the RSPB scratchpad buffer 714-32 to be written into the location specified by address 120, stored in the RSPA register 722-102.

Again, the AP adder indicators are selected for subsequent testing and the RDESC and RBASB_ register are set to---00---for selection of the descriptor 1 temporary registers.

The processor 700 returns to cycle B 14 and repeats the operations indicated resulting in the 45 generation of the second group of values. Next, the processor 700 repeats the operations in the B1 5 cycle producing the second group of values shown. This is followed by another pass through the B1 4 and B 15 cycles which produces the third group of values.

During the third pass through the B '14 cycle, the processor 700, under microprogram control, issues a read single command to the cache unit 750 to fetch the fifth data word of operand 1. As seen 50 from Figure 8, this word resides in main memory 800 and not in cache.

The cache unit 750 in response to the read single command is operative to fetch from main memory 800 another block of data words corresponding to addresses 1004- 1007 in a similar manner as described in connection with the pre-read command. However, in this case, since the command is a readsingle command, the cache unit 750 forces the CPSTOPOO line to a binary ZERO. This forces the 55 1HOLD00 and EHOLDOO signals to binary ZEROS stopping the operation of processor 700.

That is, since the contents of all processor registers are unable to be altered, the processor 700 remains in the same state until the cache unit 700 has fetched the requested data words. That is, when the cache unit 750 receives the data words which include the addressed words, it forces a DATA RECOV control signal to a binary ONE which in turn resets the R13PSD state flip-flop which turned off 60 processor 700. This results in the cache unit 750 forcing the CPSTOPOO line to a binary ONE enabling the processor 700 to continue its operation.

Since the processor 700 is at a point in the processing of the EDIT instruction where it requires the data requested and it cannot perform another operation, stopping the processor's operation does not alter the efficiency at which instructions are executed. IrT cases where the processor 700 can begin 1. z -1 V 1 54 GB 2 080 989 A 54 another operation, it may be advantageous to allow for generation of further pre-read commands during the execution of the B 14 and B 1 5cycles. Of course, where the operand 1 data string is 16 characters or less, the generation of the single pre-read command under hardware control is all that is necessary.

During the third pass through the B1 5 cycle, when the AXP adder 722-72 subtracts the number of characters per word value stored in the RXP B register from the present descriptor 1 length value (2) stored in the RXPD, the result is negative producing no carry out. This causes the exhaust flip-flop EXH 11 to be switched to a binary ONE in addition to causing a branch to a B1 6 cycle following completion of a fourth B '14 cycle.

As seen from Figure 10, during the third pass through the B1 5 cycle, the fifth data word obtained from main memory 800 by the cache unit 750 is loaded into the RDI register 704-164. Also, the negative result generated by the AXP adder 722-72 causes the exhaust flip-flop EXH 11 to be set to a binary ONE. The fourth data word previously stored in the RSPB buffer register 714-32 is written into the location of scratchpad memory 714-30 having address 1003. Following the selection of the AXP adder indicators, and the loading of the RDESC and RBASB registers 704-140 and 704-144, the processor 700 begins its last pass through the B 14 cycle.

During the last B1 4 cycle, the processor 700 repeats the indicated operations producing the fourth group of values shown in Figure 10. Briefly, it loads the fifth data word (1004) into the RSPB buffer register 714-32, increments and stores the scratchpad address in the-RP5 and RSPA registers. However, since the exhaust flip-flop EXH 11 was previously set, the processor 700 inhibits the generation of another read single command specified by the small CL) field of the microinstruction word. 20 That is, the exhaust condition causes an all ZEROS code to be applied to the DMEM lines. Next, under microprograrn control, the processor 700 sets the value '10,- into the RDESC and RBASB registers for read out of the descriptor 3 temporary registers.

At the end of the B1 4 cycle, the processor 700 branches to cycle B1 6 wherein it writes the last word of the operand 1 data string into the location designated by scratchpad address 123, This cycle is followed by the W8 cycle wherein the lengths of both operands 1 and 2 are tested via the AL and AXP adders 722-92 and 722-72 to ensure that neither operand 1.nor operand 2 has a field of ZERO number of characters indicative of a default condition. Since this is not the case, no default indication is generated.

The processor 700 reads out the descriptor 3 starting address contents of the ICI3A register. The 30 adder 704-322 decrements the ICI3A address value by one and the resulting address is stored back into the ICI3A register. The same address before it is used is incremented by one during the processor's execution of cycles of a common edit routine. The resulting address is transferred via the ZZ switch 704-328 and Z130 switch 704-340 to the RTRH7 register of the execution unit's register bank 714-10 and stored therein. At the end of this cycle, the processor 700 does a vector branch of the 35 contents of the R 1 DW register 722-106 which corresponds to the TA3 value stored in bit positions 21-23 of the RSIR register 704-154 transferred thereto during the EPOP3 cycle.

The processor 700 now begins a C2 cycle of operation. During this cycle, the processor 700 utilizing the AP adder 722-34 subtracts the descriptor 3 starting character pointer value---Wread out of the RPO register from the constant value of 4 which specifies the number of characters per operand 3 40 data word. The result of 4 is then stored in the RP2 register. Also the character pointer value read out from the RPO register is written into the RP 6 register. Next, the AXP adder indicator AXPZ is selected for testing the length of operand 1 during subsequent cycles. The state of this indicator as established in cycle W8 is stored in a history register, not shown, HR4, to enable the subsequent testing thereof.

As seen from Figure 10, the processor 700 executes another vector branch operation using the 45 TA3 contents of the R1 DW register 722-106 and enters a D 1 cycle (9-bit characters) to begin execution of a MOP set up operation. During this cycle, a constant value-- -0110or 6 is loaded into the RRDXB register via the switch 704-188 for selection by the section 704-5 of the RAAU register for use in the execution unit 714 during subsequent cycles.

The contents of the OP2 register are read out from the bank 720-10 and the first MOP character 50 selected by the contents of the RCN2 register 720-30 is loaded into the RMOP register 720-70 and the RIF register 720-63 via the ZCV switch 720-18. In this xample, the EDIT instruction results in replacing zeros with asterisk characters. Thus, the RMOP register 720-70 stores the micro-op code specifying the replacement of "0" characters to the left with asterisks. The RIF register 720-63 stores information defining the length of the operand 1 field on which this micro-op code operation will take place. In this example, this character is used for processing 3 operand 1 characters.

Next, the value stored in the RCi\12 register 720-30 is tested for an over-flow by conditioning adder 720-30 to add a value of a = 2 to it. The results is restored in the WN2 register 720-30. Since KN2 register 720-30 is pointing to character # 3 of word 3002 of operand 2, the detector 720-38 forces the Cl\120W output to a binary ONE. This means that at this time another word of operand 2 is required in order to have a minimum of 4 words stored and ready for processing. This is seen from Figure 7.

Next, bits 0-4 of entry 8 of the edit insertion table previously stored in table entry 1 register of unit register bank 720-10 are read out during the next cycle of operation and loaded into the RTE8 - -t GB 2 080 989 A 55 register 720-68. Also, an indication of the CN20W condition detected during this cycle is stored in a history register, not shown, for testing during a subsequent cycle of operation. The Cl\120W indicator is also selected for testing under microprograrn control during a subsequent branch operation.

At the end of the D 'I cycle, the length of operand 1 is tested via the AXP adder indicator (AXPZ). Since the length is not zero, the processor 700 begins cycle D2. During this cycle, the AL adder 722-92 decrements by one the operand 2 length value of 6 read out from the RI-N2 register and rewrites the resulting value of 5 in the RI-N2 register. Next, a constant value of 27 is generated via the AP adder 722-34 and loaded as a shift count into the RSC register 722-40 in addition to being written into the RP7 register via the ZRP B switch 722-24. This is in preparation for carrying out a shift operation by execution unit shifter 714-24. The shifter 714-24 includes two registers whose 10 contents are shifted relative to one another. By shifting 27 bit positions, this enables the selection of an amount equal to one data character corresponding to the 9 most significant bits.

Next, the processor 700 under microprogram control sets the RDESC and RBAS13 registers 704-140 and 704-144 to the value "01 " for selection of the descriptor 2 temporary registers. At the completion of this cycle, the processor 700 performs a conditional vector branch operation based on the 15 state of the M2 overflow indicator. Since this indicator was previously set, the processor 700 begins a D3 cycle of operation.

As seen from Figure 10, during cycle D3, the adder 704-322 increments by one (1 word) the descriptor 2 address read out from the TEA1 register and rewrites the resulting address into the TEA1 register. Also, the resulting word address 3003 is added to the base value read out from the TBASE 1 20 register by adder 704-320 which is then loaded into the RADO register 70446. Next, the processor 700 generates a cache read single command for fetching the second word of operand 2 since the word is needed immediately for processing. As seen from Figure 7, this word which includes characters 1 through 4 was previously read into cache storage 750-700 in response to the hardware generated pre-read command. Hence, the operation of the processor 700 is permitted to continue and the cache 25 unit 700 is operative to fetch the requested word and apply it to the WO lines.

During the D3 cycle, the present value corresponding to the length of operand 2 is read out from the RI-N2 register and tested for zero by the AL adder 722-92. Since the value is -5-, the AL adder indicator ALZ is not set to a binary ONE. At this time, this indicator is selected for testing during a subsequent cycle.

The next cycle is a D '10 cycle wherein the AL adder 722-92 decrements by 4 the operand 2 length value of 5 read out from the RI-N2 register to test whether the operand 2 is exhausted. Since the value is not zero, the output AL adder indicators ALZ or no carry out do not set the exhaust flip-flop EXH2 to a binary ONE. The second word (3003) of operand 2 read out from cache storage 750-700 is loaded into the RDI register 704-164.

Next, adder 704-322 increments the descriptor 2 address read out from the TEA1 register by 4 words. The adder 704-320 adds the value read out from the TBASE1 register to the incremented address and the resulting address is loaded into the RADO register 704-46. However, the address value in the TEA1 register remains unchanged. Under microprograrn control, Ahe processor 700 generates a pre-read command (0110) in accordance with the coading of the MEM field of the small CU 40 field of a microinstruction word having format 1. Format 1 is used because it lends itself to more complete control of the auxiliary unit 722. However, it will be appreciated that the pre-read command could also have been generated by a microinstruction having the alternate format shown in Figure 6b.

The pre-read command fetches the next 4 word block (addresses 3004-3007). Since the ZAC command specifies address 3007, the cache unit 750 by forwarding such ZAC command to main memory 800 causes the memory to read out the block of data which includes the specified word.

As previously explained, while the cache unit 750 is processing the preread command generated under microprograrn control, the processor 700 is permitted to continue its execution of the edit instruction. That is, the cache unit 750 holds the CPSTOPOO line in a binary ONE state. This, in turn, speeds up the execution of the edit instruction.

As seen from Figure 10, the processor 700 executes a condition vector branch based upon the state of the AL adder indicator AL1 Since the operand 2 length was not zero, the processor 700 begins a D1 1 cycle of operation. In this cycle, the second word of operand 2 (at address 3003 in Figure 7), stored in the. RDI register 704-164, is written into the OP2 register of bank 720-10 via the execution unit ALU 714-20 on the ZRESA lines.

At the end of the D 11 cycle, the processor 700 executes a conditional vector branch operation based on the TA3 value stored in the RIDW register 722-106. The result is that the processor 700 begins an E1 cycle of operation in which character unit 720 performs the execution of the type of edit operation specified by the coding of the first MOP control character.

During the E1 cycle, under the control of a microinstruction word having an AAW = 3 format, the 60 AXP adder 722-72 decrements by 1 the operand 1 length value read out from the RXPA register with the resulting value (15) being re-written back into the RXPA register. Similarly, the AL adder 722-92 decrements by 1, the operand 3 length value read out of the RI-N 'I register with the resulting value (16) also being rewritten back into the RI-N 1 register. Also, the AP adder 722-34 decrements by 1, the 56 GB 2 080 989 A 56 complement of the CN3 value read out from the RP2 register and the resulting value (3) is rewritten into the RP2 register.

Under hardware control, the contents of the RCN 1 register 720-38 are updated by the value 2 (010) via the adder 720-34 indicating selection of the next 9-bit character. Since only the upper two bits are used, the remaining bit will be ignored. Thus, it will appear that the increment value = 1. 5 The contents of the WN2 register 720-30 remains set at ZERO until the value stored in the RIF register 720-63 decrements to ZERO.

As seen from Figure 10, the number (3) indicative of the remaining characters to be processed by the first MOP control character stored in the RIF register 720-63 is decremented by 1 via the circuit 720-60 and returned to the register.

The decoder 720-74 is operative to decode the MOP control character and generate signals for controlling the operation of character unit 720. During operation, the first character is read out of the OP 1 register and when it is a ZERO as signaled by detector 720-82, it is replaced by the asterisk character read out from the second character position of the table entry 1 register of bank 720-20.

15. Since the first data character is a ZERO as seen from Figure 8, the asterisk character is selected via the 15 ZOC switch 720-20 and loaded into the RAAU register 722-46 via switch 722- 44.

Also, the processor 700 under microprogram control sets the RV130 and RV13Z registers in accordance with the states of the MOP indicators MOPIA and MOPIB for subsequent branch operations. The MOPIA indicator signals the processor 700 to continue execution of MOP execute cycles, to process the next MOP control character and to determine whether more processing is to be done using 20 the same MOP character. The MOPIB indicator signals the processor 700 to terminate operations.

Additionally, several history registers, not shown, HROA and 3 are set in accordance with the statL-s of the control indicators W 1 OW, CN20W and END for subsequent testing. Here, the values are ZEROS.

As seen from Figure 10, the processor 700 begins an E2 cycle of operation during which the asterisk contents of the RAAU register 722-46 are applied to the ZEB lines via the ZX13Q switch 704-59 of section 704-5. From there, the asterisk character is applied to the shifter 714-24 via the ZOP13 switch 714-17 while the contents of the TRO register is applied via the ZOPA switch 714-15 and the switch 714-28. The shifter 714-24 shifts these signals by 27 bit positions under the.control of the shift count from the unit 722. The shifted result which corresponds to the first character of operand 3 in Figure 8 is then loaded into the TRO register via the ZRESBO switch 714-38. 30 At the end of the E2 cycle, the processor 700 tests the state of the control indicator MOP IA by a vector branch operation. Since the MOPIA value is 00, the processor 700 begins an F1 cycle followed by an F2. cycle of operation. During the F1 cycle, the processor 700 execute operations similar to those executed during the previous E1 cycle of operation. This results in the group of values shown. That is, the RXPA, RI-N 1 and RP2 registers stores the values 14, 14 and 2 respectively.

Also, during the F1 cycle, under hardware control, the character unit adder increments the WN 'I register 720-28 by 1 which causes a CN1 OW condition stored in a history register HRO, not shown, for subsequent testing. This indicates that the second word of operand 1 is needed to be fetched from scratchpad memory 714-30 and stored in the OP 1 register. The KN2 register 720-30 remains at ZERO and the RIF register after being decremented by 1 stores the value ', l ". Again, an asterisk character is selected via the ZOC switch 720-20 to place the second operand 1 ZERO data character. The vector branch registers RVBO and RV132 are set in accordance with the MOPIB and MOPIA indicators respectively. The RV130 register is set to 010 signaling the testing for M1 OW condition. The RV132 register is set to the value 10 indicating that the MOPIB indicators are to be tested during a subsequent cycle of operation.

During the F2 cycle, the second asterisk character is applied to the ZEB lines via the ZX132 switch 704-59 from the RAAU register 722-46. Again, the contents of the TRO register and the asterisk character are applied as inputs to shifter 714-24, shifted 27-bit positions with the result being written into the TRO register. The result corresponds to the first two characters of operand 3 shown in Figure 8.

At the end of the F2 cycle, the MOPIA indicator is tested via a conditional branch operation and the processor 700 begins an F4 cycle.

During the F4 cycle, under microprogram control, the processor 700 sets up the states of the various indicators for a subsequent branch operation. Indications as to L1 under-flow, L3 underflow and CN3 overflow are set by read out of the contents of the RXPA, RI-N 1 and RP2 registers to the AXP, A] and AP adders and storing the status of the adder output ZERO indicators (AXPZ, ALZ and AP4 in history registers HR4, 5 and 7, not shown. The AXPZ and ALZ indicators are selected and the RV132 register is set by the TA3 contents of the R1 D register 722-106.

At the end of the F4 cycle, the processor 700 performs a vector branch operation based upon the state of the MOPIB indicator and enters a J1 cycle. During this cycle, the CN1 OW storage register (HRO) is selected for testing. At the end of this cycle, the processor 700 performs a branch based upon 60 the status of the previous selected adder indicators AXPZ and ALZ. Since neither the length of operand 1 or 3 was not zero, the processor 700 enters a J7 cycle.

During the J7 cycle, under microprogram control, the processor 700 loads the scratchpad address for operand 1 read out from the RP3 register into the RSPA register 722- 102 via the AP adder 722-34. The processor 700 also selects the end indicator storage register H R3, not shown, for 65 57 GB 2 080 989 A 57 subsequent testing. At the end of the J7 cycle, the processor 700 performs a branch based upon the stored status of the CN 1 OW indicator. Since the indicator was previously set, the processor enters a P 1 cycle. During the P 1 cycle, the second word of operand 1 previously stored in address 100 1 is read out of address 120. of scratchpad memory 714-30 and loaded into the OP 1 register of bank 720-10 via 5 the ZRESA lines. As seen from Figure 8, this word includes the data characters 4060 wherein the editing of the first character is performed under the control of the first MOP control character while the editing of the next three characters is performed under control of the next MOP control character of Figure 8. 10 Also, during the P 1 cycle, the operand 1 scratchpad address value is read out of the RP3 register, 10 incremented by 1 by the AP adder 722-34 and the resulting address 121. is rewritten into the RP3 register via the ZRPC switch 722-32. The processor 700 also selects for subsequent testing, the history register, HR7, which stores the W30W status. At the end of the P 1 cycle, the processor 700 executes a branch operation based upon the testing of the state of the end indicator. Since this indicator is not set, the processor 700 enters a P2 cycle.

During this cycle, operand 1 length stored in the RXPA register is tested for zero via the AXP adder 722-72 for detection of a default condition. The shift constant 27 stored in the RP7 register is loaded into the RSC register 722-40 for controlling the shifter 714-24 during subsequent cycles of operation.

At the end of the P2 cycle, the processor 700 performs a conditional vector branch operation 20 based upon the status of the CWOW condition previously selected for testing. Since there was no CN3 overflow condition ' detected, processor 700 begins another MOP execute sequence starting with cycle F1 which is followed by another E2 cycle.

During the E1 cycle, the processor 700 sets the RXPA, RI-M and RP2 registers to the values 13, 13 and 1 respectively as illustrated in Figure 10. Again, under hardware control, the RCN 'I register 720-28 is incremented to a value 01, the RCN2 register 720-34 remains the same and value stored in the RIF register 720-63 is decremented to ZERO. The decrementing of the RIF register contents to ZERO causes a value of 0 1 for MOP IA to be loaded into the RV132 register. This causes the process 700 to read in the next MOP control character which corresponds to the operand 2 character at address 3003 previously written into the OP2 register during the D1 1 cycle. 30 Since there was no zero character detected, the data character having the value "4- is selected via the ZOC switch 720-20 for loading into the RAAU register 722-46. Again, the result of the microoperation specified by the contents of the RMOP register 720-70 indicated by the states of the MOPIA, MOPIB and END indicators is stored in history registers HRO, 1 and 3 for later testing during a subsequent cycle of operation. 35 During the second E2 cycle, the data character -4- is applied to the ZEB lines via the ZX13Z switch 704-58. The data character and contents read out from the TRO register applied to shifter 714-24 are shifted left by 27 bit positions and the result is written back into the TRO register. At this time, the register contains the values 4 and the RP2 register contains the value 1. This indicates that one more Qperand 1 data character can be processed and stored in the TRO register.

At the end of the E2 cycle, the processor 700 performs another vector branch operation based on the states of the MOP IA indicators. Since the value is---0 '1 -, the processor 700 now begins a F3 cycle.

During this cycle, the A1 adder 722-92 tests the value 5 stored in the RIN2 register indicating the number of remaining operand 2 characters (L2) for detection of a fault condition. Also, the AXP adder 722-22 tests the value 13 stored in the RXPA register indicative of the number of characters remaining in the operand 1 or descriptor 1 data field (L1). The result of this test is denoted by the state of the AXPZ indicator which the processor 700 selects for testing during a subsequent cycle.

After loading the TA3 value stored in the R 1 DW register 722-106 into the RV132 register, the processor 700 performs another vector branch and begins another D 'I cycle of operation. Since the processor 700 performs the same operations as previously described only the pertinent results will be 50 discussed herein relative to the cycles previously described.

During this cycle, character # 0 of the descriptor 2 word stored at address 3003 is selected by ZCV switch 720-18 and loaaed-into the RMOP register 720-70 and the RIF register 720-63 when the word is read out from the DP2 register. Also, the value stored in the RC1\12 register 720-30 is advanced from -002" to "012" designating character #1. In the OP2 register as the next MOP control 55 character to be read out.

During the D2 cycle, processor 700 decrements by one the contents of the FILN2 register so that it indicates that there are 4 more operand 2 MOP control characters to be processed. As seen from Figure 10, since there is no CN2 overflow condition, the processor 700 begins another E1 cycle. During this cycle, the values for L1 and L3 stored in the RXPA and FILN 1 registers are decremented to 12. Also, the 60 value stored in the RP2 reffister-is decremented to ZERO indicating that the TRO register now stores a complete 4 character word which should be written into the first position of the operand 3 data field.

Under hardware control, the value stored in the RCN 1 register is increased to - 10,- indicating that the data character---Wis the next character to be selected from the OP 1 register. The RW2 register - 720-30 remains at -01 - indicating the next MOP control character while the contents of the RIF 58 GB 2 080 989 A 58 register is decremented from a value of 3 to the value 2. This indicates that 2 operand 1 data characters are to be processed by the presently stored MOP control character.

Since the selected data character is a ZERO, this causes the control logic circuits 720-76 to condition the ZOC switch 720-20 to select another asterisk character to be loaded into the RAAU register 722-46. This results in the replacement of character # 1 at address 100 1 in Figure 8 with an 5 asterisk.

Since the value stored in the RP2 register is ZERO, the processor 700 sets the MOPIA and MOPIB indicators to the value---0 '1 During the next E2 cycle, the asterisk character is loaded into the TRO register. At this time, the TRO register stores the values 4. In the manner previously described, the processor 700 begins a second F4 cycle based upon the status of the MOP IA and MOP IB indicators.

During this cycle, the contents of the RP2 register is tested for zero and the history register HR7 is set to indicate the occurrence of a W30V17 condition (RP2 = 0). Next, processor 700 begins a second J 1 cycle during which the stored status of the CNIOW indicator (HRO) is selected for testing during a subsequent cycle. The processor 700 begins a second J7 cycle in which the RDESC and RBASA registers 704-140 and 704-144 are again set to the value 10, for selection of descriptor 3 temporary registers.

Since there was no W l overflow condition, processor 700 begins a first J8 cycle. During this cycle, the descriptor 3 address (4777) read out from the ICI3A register is incremented by 1 (word) via adder 704-322 and the result (5000) is written back into the ICI3A register. The base value stored in the]BASE A register address 5000 is added to the address 5000 by adder 704-320 and the resulting 20 address 5000 is loaded into the RADO register 704---46. The processor 700 generates a write single zoned command under microprogram control. More specifically, the processor 700 forces bits 5-8 to a value 1111 specifying the bytes of the word to be written at address 5000 in response to the write command. Also, the processor 700, under microprogram control, forces command bits 1-4 to a code of 1000 specifying that the ZAC command is of the write single zoned type. The ZAC command is 25 forwarded to the cache unit 750 for processing.

Additionally, processor 700 under the control of the MEMADR field forces the DMEM lines to a code of 1100 signaling the cache unit 750 that it is to perform a write single operation. Further, it forces the DREWAC line to a binary ONE signaling the cache unit 750 of the command. The processor 700 via the AL adder 722-92 decrements by 4 the operand 3 length value stored in the RLN3 register and writes back the resulting value---112---into the RILW register. Next, the processor 700 performs a vector branch operation based upon the value of the TA3 field stored in the RIDW register 722-106 and begins a first Q1 cycle.

During the Q1 cycle, the first data word of descriptor 3 4) is read out from the TRO register and loaded into the RADO register 704 4 6 via ALU 714-20 and the ZRESB lines. Next, the AP adder 35 722-34 loads a value 4 into the RP2 register used for counting the next 4 characters to be written into the TR4 register. The RP6 register is loaded with ZEROS as was it stated previously. At the end of the Q1 cycles, the precurssor 700 performs a branched based

upon the state of the previously stored END indicator status. Since the indicator was not set, the processor 700 returns to an E1 cycle by a vector branch operation based upon the TA3 field value stored in the RIDW register 40

722-106.

The cache unit 750 processes the write single command in a manner similar to that used in the processing of a read command. More specifically, in response to the DREWAC line being set to a binary ONE, the cache unit 750 loads the ZAC command word transferred to the RADO register 704---46by processor 700 during the J8 cycle into the first location of the WZAC buffer 750-100. The write address counter 750-104 contents are incremented by one. The data word read out from the TRO register and loaded into the RADO register 704-46 during the 0.1 cycle is written into the second location of the W2AC buffer 750-100.

In the manner previously described, the directories and cache storage 750700 are accessed by the signals applied via the RADO lines. Assuming that the block including address 5000 does not reside 50 in cache, the hit/miss detector circuits 750-560 do not force the 13PSD line to a binary ONE.

Upon the decoding of the write single command by the decoder 750-166, the UGCOGTH and CAOPR control state flip-flops are switched to binary ONE states. The UGCOGTH flip-flop when set permits the processor data word to be written into cache storage 750-700 when the block containing the word resides in cache. The CAOPR flip-flop when set forces the AOPR line to a binary ONE state. At 55 this time, the first ZAC command word is loaded into the ZIU output register 750-174.

Additionally, the cache unit 750 switches the UGSOGTH control state flipflop to a binary ONE upon the receipt of binary ONE signal on the ARA line from the SIU 100. The cache unit 750 completes the operation by loading the data word into the SIU output register which remains on the DIS fines until the occurrence of a next clock pulse.

Since the cache command was a write command, processor 700 can continue its execution of the edit instruction following its completion of transferring the data portion of the command. As seen from Figure 10, the processor 700 begins a fourth E1 cycle. This results in the unit 722 setting the RXPA, RLNI and RP2 registers to values of 11, 11 and 3 respectively. Also, the RCNI register 720-28 is set to the value 112 while the KN2 register 720-30 remains set to the value 01, The RIF register 720-6365 59 GB 2 080 989 A 59 following decrementing stores the value 1. The operand 1 data character # 2 having the value 6 is selected by the ZOC switch 720-20 for transfer to the RAAU register 722--- 46upon read out of the contents of the OP 2 register.

During the fourth E2 cycle, the selected data character applied to the ZEB lines is shifted by the shifter 714-24 and the result---W'is written back into the TRO register. The processor 700 branches to 5 begin a fourth F1 cycle followed by F4, J 1, J7 and P 1 cycles.

During the FI cycle, the registers are set as follows: RXPA = 10; RI-NI = 10; RP2 = 2; RCN 1 = 00.

RC1\12 = 0 1 and RIF = 0. The status of the CN 1 overflow indicator produced by RCNI = 0 is stored in the history register, HRO not shown. The status of the END indicator produced by RIF = 0 is stored in the history register HR3, not shown.

Also, the operand 1 data character#. 3 having the value "0" is selected by the ZOC switch 720-20 for transfer to the RAA11 register 722-46 upon read out of the OP2 register contents. Since the---Wcharacter appears at the right of non-zero data character, an asterisk character is not substituted for the -0- data character.

During the F2 cycle, the -0- character is stored in the TRO register with the resulting content ---60---. In the J7 cycle, the scratchpad address value 121. is loaded into the RSPA register 720-102 and the third word of descriptor 1 at address 1002 is loaded into the OP 1 register from the addressed location (121 j of scratchpad memory 714-30 during cycle P 1. Also, during the P 1 cycle, the scratchpad address is incremented by one and the resulting address 122. is written back into the RP3 register.

As seen from Figure 10, since the END indicator was set during a previous cycle, the processor 700 branches to begin a first P4 cycle. In this cycle, the processor 700 tests the length of operand 2 (L2) for zero to detect a default condition. During the remainder of the cycle, operations identical to those in cycle P2 are performed. Next, the processor 700 begins another D1 cycle followed by D2, El, E2, F1, F2, F4, J7, J8 and Q1 cycles.

Briefly, during the D 1 cycle, the next MOP character (char# 1-3003) is loaded into the RMOP and RIF registers and the RCN2 register is incremented to a value 102. During cycle D2, the processor 700 tests for the end of the operand 2 field and decrements the RI-N2 register to a value 3. In cycle E1, the registers are set to the following values: RXPA, RI-N 1 = 1; RP2 = 1; RCW = 012; KN2 = 102 and

RIF = 2. Also, the operand 1 data character # 0 having the value 1 is selected to be loaded into the RAAU register.

During the E2 cycle, the data character is written into the TRO register which now stores the values "601 ". In the F1 cycle, the above mentioned registers are set as follows: RXPA, RLNi = 8; RP2 = 0; RCNI = 102 KN2 = 10. and RIF = 1. Also, the operand 1 data character #1 having the value 2 is selected for loading into the RAA11 register. During the F2 cycle, the data character is written into 35 the TRO register which now contains a full word---6012".

Accordingly, during cycle J7, the RDESC and RBAS13 registers are set to the value ',l 0---for selecting descriptor 3 temporary registers. In the J8 cycle, the processor 700 loads the address 5001 into the ICI3A register and into the RADO register. Another write single zoned command is generated and transferred to the cache unit 750. Also, the PLN3 register contents are decremented to the value 8. 40 During the Q1 cycle, the data word corresponding to the second word F3 descriptor 3 is loaded into the RADO register for forwarding to the cache unit 750. This results in the values 6012 being written into the location having address 5001.

The Q1 cycle is followed by El, E2, F3, D1 and D2 cycles. Briefly, during the E1 cycle, the different registers are set to the following values: RXPA, RI-N1 = 7; RP2 = 3; IRCW = 11,; RC1\12 = 102 and RIF = 0. Also, operand 1 data character# 2 having a value---Wis selected to be loaded into the RAAU register. During the E2 cycle, the data character is written into the TRO register. In the F3 cycle, the L1 and L2 indicators are tested for the value "0".

The next MOP character (char # 2-3003) is loaded into the RMOP and RiF registers during the D1 cycle. Also, the IRW2 register is incremented to a value 112 1 n cycle D2, the RLN2 register is decremented to a value 2. The D2 cycle is followed by El, E2, F4, J 1, J7 and P 1 cycles.

During the E1 cycle, the registers are set to the following values: RXPA, RLN 1 = 6; RP2 = 2; RCN 1 = 00, (signals CN 1 OW condition; WN2 = 112 and RIF = 2. Also, an asterisk character is selected for loading into the RAAU register in place of data character # 3 (1002) having a zero value.

During the E2 cycle, the asterisk character is written into the TRO register which now stores the values 55 11011.

During the P 1 cycle, the next data word of operand 1 containing the values 1357 are read out from the location 122. of scratchpad memory 714-30 into the Opl register. Also, the scratchpad address is incremented by one and the result 123. is written back into the RP3 register.

The P 1 cycle is followed by El, E2, F1, F2, F4, J 1, J7, J8 Q1 and Q2 cycles. During the E1 cycle, 60 the registers are set as follows: RXPA, RI-N1 = 5; RP2 = 1; RW1 = 012; RC1\12 = 112 and RIF = 1. Also, the data character # 0 (1003) of operand 1 having a value 1 is selected to be loaded into the RAAU register. During the E2 cycle, this character is written into the TRO register which now stores the values 11011.

11 V, ' i. ' GB 2 080 989 A 60 During the F3 cycle, the above registers are set to the following values: RXPA, RLN 1 = 4; RP2 = 0; RW l= 10,; IRW2 = 11, and R] F= 0 (signa ling finished with the MOP character). Also, the data character #1 having the value 3 is selected for loading into the RAAU register. Further, the status of the indicator is stored in history register HR3. During the F2 cycle, the data character is written into the TRO register which now contains the values -0 13---..

During the J7 cycle the RDESC and RBAS13 registers are set to---10- to select the descriptor 3 temporary registers. In cycle J8, the descriptor 3 address 5002 is loaded into the ICI3A register and into the RADO register. At this time, the processor 700 generates another write single zoned command for having the cache unit 750 write the third word of descriptor 3 into main memory 800. Also, the FILN3 register is decremented to store the value 4. During the 0.1 cycle, the contents of the TRO register are loaded into the RADO register for transfer to cache unit 750. Also, the RP2 register is again loaded with the value 4. In cycle Q2, the length of operand 2 (L2) is tested.

The Q2 cycle is followed by D1, D2, D3, D10, D1 1, El, E2, F1, F2, F4,J1, J7 and P1 cycles. During the D 'I cycle, the next MOP control character# 3 (3003) is loaded into the RMOP and R IF registers (720-70 and 720-63. Also, the IRCN2 register 720-30 is incremented to a value "00- which 15 causes the Cl\120W indicator to be set to a binary ONE.

In cycle D2, the RI-N2 register is decremented to the value 1 and the RDESC and RBASB registers 704-140 and 704-144 are set to the value 01 to select descriptor 2 temporary registers. During cycle D3, the processor 700 loads the address 3004 into the TEA1 register and into the RADO register 704-46. Again, under microprogram control, the processor 700 generates a read single command to 20 cache unit 750 for fetching the data word at address 3004.

Since the 4 word block including the word was fetched by cache unit 750 in response to a cache pre-read command, the cache unit 750 upon completing the directory search cycle forces the BPSD line to a binary ONE indicative ot a "hit". Therefore, the CPSTOPOO line remains a binary ONE enabling the processor 700 continues its processing of the edit instruction.

During the D1 0 cycle, the value stored in the RLN2 register is decremented by 4 which results in the value -2. This forces the no carry out indicator to a binary ONE which switches the EXH2 indicator to a binary ONE. The data word at address 3004 including the value -9W applied to the W1 lines by cache unit 750 is loaded into the RDI register 704-164. The processor 700 increments the descriptor 2 address by 4 (words) and loads the resulting address 3008 into the RADO register 704-46. Another 30 cache pre-read command specifying reading of the next 4 word block (addresses 3008-30011) is generated by the processor 700 under microprogram control.

From the foregoing, it is seen that through the use of pre-read commands, the processor 700 is able to perform the edit operation more expeditiously in that the required operand 2 data will always be brought into cache storage 750-700 in advance making it available to the processor 700 as it is 35 needed. Thus, the processor 700 can continue processing without interruption.

During the D1 1 cycle, the data word fetched by the cache unit 750 is transferred from the RDI register 704-164 to the OP2 register of character unit 720. In the next E1 cycle, the registers are set as follows: RXPA, FILW = 3; RP2 = 3; RCW = 11,; WN2 = 00, and RIF = 2. Also, the operand 1 data character# 2 having the value -5" is selected for transfer into the RAAU register 622-46. In cycle E2, 40 the data character is shifted and written into the TRO register.

The execution of the F1 cycle results in the above registers being set to the following values:

RXPA, FILN 1 = 2, RP2 = 2; RCN 1 = 00, (signals CNIOW condition); RCN2 = 00, and RIF = 1. Also, the operand 1 data character # 3 having the value -7" is selected for transfer into the RAAU register 722-46. In cycle F2, the data character is written into the TRO register. Lastly, in the P 1 cycle, the operand 1 data word at address 1004 in Figure 8 which includes data characters "90- is read out scratchpad location having address 123, and loaded into the OP 1 register.

The P 1 cycle is followed by another series of El, E2, F3, D 1, D2, El, E2 and F4 cycles. At the completion of the E1 cycle, the registers contain the following values: RXPA, RI-N 1 = 1; RP2 = 1; WN1 = 0 1,; RC1\12 = 00, and RIF = 0 (signals that a new MOP character is needed). During the E1 50 cycle, the operand 1 data chartacter # 0 (address 1004) having the value "9- is selected for transfer to the RAAU register 722-46. In cycle E2, the data character is written into the TRO register which at this time stores the values -579---.

During the D1 cycle, the next MOP control character, (char # 0) in Figure 8 is loaded into the RMOP and the RIF registers 720-70 and 720-63. Also, the RCN2 register 720- 30 is incremented 55 to the value---0 '12'. During the D2 cycle, the RI-N2 register is decremented to the value 0. This signals that the operand 2 string has been exhausted (L2 = 0).

In cycle El, the last character of operand 1 (char # 1 at address 1004 in Figure 8) is processed by character unit 720. Since the character is the first character to be processed under control of the MOP control character loaded into the RMOP register 720-70 in cycle D1, its zero value is detected and an 60 asterisk character is selected for loading into the RAAU register 722-46. At the completion of cycle El, the register values are as follows: RXPA, RLW = 0; RP2 = 0; RCN 1 = 102; RCN2 = 01, and RIF = 0 (the MOP character was coded to specify processing of 1 character).

In cycle E2, the asterisk character is written into the TRO register which at this time contains a full word (i.e., "5790"). In cycle F4, when the adders test the values in the RXPA, RI-N 1 and RP2 registers, 65 61 GB 2 080 989 A 61 this results in the setting of the AXPZ, ALZ and APZ indicators to binary ONES. The status of these indicators are stored in history registers HR4, HR5 and HR7, not shown. Also, the zero value in the RP2 register is stored in the RP5 register.

Next, the processor 700 executes a J1 cycle wherein the status of the CNIMF indicator (HRO) is selected for testing in a subsequent cycle. At the end of the J 1 cycle, the status of the AXPZ and AL 5 indicators are tested. Since both are set, the processor 700 sequences to cycle J2.

In cycle J2, the processor 700 selects the ALZ indicator (HR5) for testing in a subsequent cycle and begins cycle J3. As seen from Figure 10, the value 102 is loaded into the RDESC and RBASB registers 704-140 and 704-144 for selection of operand 3 temporary registers. Also, the END indicator is selected for testing during a subsequent cycle.

At the end of the J3 cycle, the processor 700 performs a conditional vector branch operation based on the state of the ALZ indicator. Since the indicator was set, the processor 700 branches to cycle G7 based upon the TA3 contents of the R1 DW register 722-106. During cycle Q7, the processor 700 increments by 1 (word) the descriptor 3 address read out from the ICBA register. The resulting address 5003 is written back into the ICBA register. Also, this address is added to the TBASEA address by adder 704-320 and the resulting address (5003) is loaded into the RADO register 704-46.

As seen from Figure 10, the processor 700 generates a last write signal zoned command which is forwarded to the cache unit 750. At this time, the processor 700 sets the EXH3 indicator to a binary ONE. Also, the AP adder 722-34 generates a shift count value by subtracting from the value (0) stored in the RP5 register from a constant value 36 with the result being loaded into the RSC register 20 722-40.

Next, processor 700 begins a Q8 cycle wherein the contents of the TRO register are shifted by 36 bit positions via the shifter 714-24. The resulting data word having the values 579 is loaded into the RADO register 704-46 for writing into the location having address 5003 as shown in Figure 8. As seen from Figure 10, the processor 700 begins cycle Q9 wherein it restarts the instruction pipeline in 25 response to a microinstruction word having the second format illustrated in Figure 6b.

In greater detail, the PIPE field of the microinstruction word is coded to specify a type 1 restart.

Upon the decoding thereof, the process 700 sets the [END signal to a binary ONE which starts the beginning of the next instruction.

As seen from the foregoing description, the arrangement of the present invention is able to speed 30 up the execution of various instructions required to be executed by a data processing unit. By having a processor execute sequences which include pre-read commands for types of instructions whose execution can be facilitated, the overall efficiency of the processor is increased.

It will be appreciated that the subject matter of the present invention is not directed to any particular manner of microprogramming a given instruction. By contrast, the microprogrammer is free to 35 select those cycles which should be coded to include a pre-read command.

In accordance with the teachings of the present invention, pre-read commands should be included in those cycles where advance calls to a cache unit for data can be carried out while the processor performs operations which does not require immediate use of the data. For example, as illustrated, this can be done where the processor is generating addresses or is carrying out an editing or translation operation. Thus, in accordance with the teachings of the present invention, pre-read commands are generated under hardware control during the initial portion of a multiword instruction enabling the generation of addresses of certain descriptors to proceed in parallel in the development of addresses for other descriptors.

With reference to Figures 1-6b and 11-1 3d, the operation of the present invention will now be 45 described in connection with the processing of several different types of instructions having formats illustrated in Figures 1 3a to 1 3d.

However, before discussing these instructions, reference will first be made to the state diagram of Figure 11. This diagram illustrates the sequencing of the 1 cycle control state storage circuits of block 704-102 as a function of the codin g of the---CCS-sequence field applied via the lines 704-210. As 50 seen from Figure 11, the control state FPOA is a beginning state for processing all instructions.

The FPOA state is entered when the FPOA control state flip-flop of block 704-102 of Figure 3 switches to a binary ONE. This flip-flop is set to a binary ONE under hardware control in accordance with the following Boolean expression:

SET= [RUL-DI-(DIBFRDY.DIBF "9-f-Y.[ DXEDRPTS.DPIPE1-4).

That is, the FPOA cySIentered following an [END cycle when there is no hold condition relating to t_ line (i.e., signal HOLD] = 1), the instruction buffer 750-900 is not empty (i.e., _p.pl D1i3FEIVITY= 1), it has at least one instruction ready for transfer to processor 700 (i.e., D113FRDY = 1), the previous instruction did not produce a store compare condition (i.e., [STRCPR = 1), is not an execute or repeat instruction (i.e., UX--EDRF-r = 1) and the pipeline has been restarted (i.e., DPIPE1 -4 = 1).60 62 GB 2 080 989 A 62 When in control state FPOA, the RBIR register 704-152 stores the instruction op-code as well as the remainder of the instruction word having one of the formats illustrated in Figures 13a and 13b. Also, the RSIR register 704-154 stores the same instruction word. In the case of an instruction having the format of Figure 13a, the RBASA register 704-156 stores the upper three bits of the y field while the 5 RRDX-A register 704-158 stores the td portion of the instruction word TAG field. The R29 flip-flop 704-162 stores the value of the AR bit 29 of the instruction word.

During control state FPOA, the hardware circuits of block 704-101 decode the CCS sequence field read out from the ' CS control store 704-200 in response to the 1 0-bit op-code (bits 18-27) applied via the RBIR register 704-152. It is the coding of the CCS sequence field which establishes what path the processing of the instruction is to follow. Accordingly, the coding of the CCS sequence 10 field determines the types of operations performed during the FPOA and subsequent cycles which complete as much processing of each instruction as possible under hardware control. Examples of the specific operations are set forth in the section -Hardwired Control State Actions- included herein.

Considering the paths in greater detail, it is seen from Figure 11 that the hardware circuits of block 704-102 sequence from the FPOA state to control state FTRF-NG when a control flag flip-flop 1 FT13F.TST indicates that the previous instruction was within the transfer class and that the condition for transfer or branching was not met dT-RGO 1). During control state FTRF-NG, the processor hardware circuits generate signals for reinitializing the instruction buffer as a function of the contents of the instruction counter. This enables the discontinuance of that stream of instructions and a change back to the current stream of instructions whose address is indicated by the instruction buffer circuits. The 20 FTRF-NG control state is then followed by one of the cycles RI-INIT through FW17-IBUF as a function of the coding of the 1 buffer status lines.

In the case of normal instruction procEsig, the path followed as a consequence of decoding the [TRGO. This path indicates that the previous CCS sequence field is that labelled FT13F-TST + instruction was not within the transfer class (FTI1F-TST = 1) or if it was within such class the condition 25 for transfer is going to be met ([TPIG0 = 1). Hence, this path indicates continued processing of a transfer class instruction under hardware control. It will be noted that if the previous instruction was a transfer class instruction (FTRF-TST = 1) and if the current instruction is a transfer class instruction (TRF), then the hardware circuits of block 704-102 remain in control state FPOA (i.e., follow path TRF to FTRF-TST).

The point X in Figure 11 denotes from the coding of the CCS sequence field whether the particular instruction is in the EIS class, the ESC class or TRF - E-A class, the E- IS - ES-C - [-EA.TRF class or the U-S- -1-SC - [EA class. In the case of the EIS class, the coding of CCS sequence field determines how many descriptors are needed for that particular EIS instruction. Each of the EIS instructions has the multi-word format illustrated in Figure 1 3b and can require up to three descriptors. The CCS fields for all instructions requiring one, two and three descriptors are grouped together within the decoding circuits.

Additionally, signals applied via address lines of the instruction buffer circuits of the cache unit 750 are decoded to determine how many descriptor values or words are presently stored in the instruction buffer. These sets of signals are compared and when there are not enough descriptors presently in the 1 buffer to complete the instruction, then the circuits of block 704-102 switch from FPOA to contro.1 40 state FPIM-EIS. During control state RIM-ElS, the processor circuits generate signals for conditioning the cache unit 750 to perform an instruction fetch operation for fetching four more words from main memory or backing store which are loaded into the instruction buffer.

Once the required numbers of descriptors have been fetched and the cache unit 750 signals that the instruction buffer is ready (IBUFRDY = 1), the hardware circuits of block 704-102 are at point C. If 45 the instruction buffer is not ready (IBU -R-O-Y = 1), the hardware circuits 704-102 switch to control state FWF-DESC wherein the processor 700 waits for the descriptor. When the instruction buffer is ready (IBURDY = 1), the hardware circuits are again at point C.

It will be noted that all EIS type instructions (CCS codes 110000-111111) follow a path to point C. If the CCS field indicates that the instruction is a bit type EIS instruction (BIT = 1), then the hardware 50 circuits 704-102 switch control state (FESC) without performing any FPOP cycles of operation. If the CCS sequence field indicates that the instruction is not within the bit type class (i.e., BIT = 1), the hardware circuits 704-102 switch to control state FPOP for one cycle of operation. It will be appreciated that the number of descriptors within the EIS multi-word instruction determines the number of FPOP cycles.

A maximum number of descriptors are processed under hardware control before the circuits 704-102 switch to control state FESC enabling control to be transferred to a microprogram routine within the execution control store 701-2. For those EIS multiword instructions which require address preparation on three descriptors, the hardware circuits 704-102 remain in the FPOP control state for executing two cycles during which the processor circuits generate addresses for the first and second 60 descriptors before switching to control state FESC.

It is seen from Figure 11 that depending upon the type of instruction as defined by control sequence field and the type of address preparation required, address preparation for the different descriptors proceeds until it is determined that address preparation can no longer continue under hardware control. More specifically, during the FPOP cycle, address preparation is performed for i- '' 63 GB 2 080 989 A 62 descriptors of the classes of instructions which include instruction types NUM2 through IVIVT conditioned on the fact that the descriptor is not an indirect descriptor (i-D = 1), that the descriptor does not specify an indirect length (-FRL = 1) and it is not a Type 6 descriptor (TYM6 = 1) or address preparation is to be completed under hardware control (FiNH-ADR = 1) in addition to other unusual situations which cannot be handled under hardware control (i.e., FAFI = 1). When the circuits of block 704-104 force signal FINH-ADR to a binary ZERO, this indicates that the address preparation had been completed under microprogram control and therefore does not have to be performed during a FPOP cycle.

The circuits of block 704-110 force signal -Anto a binary ONE when the address preparation can be accomplished during the FPOP cycle and there are no special conditions such as the occurrence of a mid instruction interrupt.

Lastly, the condition RDESC = 00 is defined by the states of flip-flops of block 704-142 and indicates the occurrence of a first FPOP cycle during which the processor circuits prepare the address of the first descriptor.

In the event that there are some special type of conditions presently defined by the function f, the15 hardware circuits of block 704-102 switch to control state FESC. This enables the transfer of control to routines stored in the ECS control store 701-2 for continuing the processing of the instruction under microprogram control.

Additionally, in accordance with the preferred embodiment of the present invention, the circuits of block 704-102 include flip-flops which provide control states FIDESC and FWF-MESC for processing under hardware control indirect operand descriptors for EIS instructions.

For a first indirect descriptor, it becomes necessary to hold up completion of the 1 cycle for a cycle and let the execution 714 complete its operation. As soon as the E cycle is completed, the processor circuits under hardware control fetch the indirect descriptor. In greater detail, when the CCS field indicates that the instruction is an EIS instruction and bit 31 of the RSIR register is a binary ONE (see 25 Figure 1 3c), this means that the first descriptor of the EIS instruction i's an indirect operand.

During control state FPOA, the hardware circuits of block 704-102 hold upcompletion of the 1 cycle (i.e., HOLD-1 = 1) for one cycle. That is, a control flip-flop FPOAID included within block 704-102 is switched to a binary ONE in response to a first clock pulse which forces the [HOLD100 signal to a binary ZERO. Upon the occurrence of a next clock pulse, the FPOAID flip-flop is reset to a 30 binary ZERO which allows the [HOLD100 signal to be forced to a binary ONE (see expressions listed under FPOA control state in -Hardwired Control State Actions" section).

For the remaining EIS descriptors, the hardware circuits of block 704-102 do not hold up the completion of any more 1 cycles following control state FPOA. From Figure 11, it is seen that the control state FPOP is entered. However, the hardware circuits of block 704-102 immediately switch to control state FIDESC upon detection of an indirect descriptor. This state is followed by a switching to control state FWF- 113ESC and a return to control state FPOP completing the processing of a first indirect operand descriptor. These states are repeated for each descriptor word specified by the MF field of the instruction word as having an indirect operand (see Figure 1 3b).

40, Considering instructions other than EIS type instructions, it will be noted from Figure 11 that when 40 the CCS sequence field indicates that the instruction is within the escape class or within the transfer class and require indirect address modification, the hardware circuits 704-102 immediately switch from control state FPOA to the FESC control state. As mentioned, control is transferred to the appropriate microprogram routines stored in ECS control store 701-2. Thereafter processing of the instruction proceeds under microprogram control. As indicated in Figure 11, the occurrence of certain 45 microinstruction codes causes the hardware circuits 704-102 to switch to control state FPOP.

For the purpose of the present invention, the hardware circuits of block 704-102 passes control to the ECS control store 701-2 for completion of certain types of instructions which cannot be executed in a pipeline mode of operation.

The above mentioned instructions include EIS type instructions as well as those instructions in which the hardware circuits of block 704-102 switch to control state FESC during the processing thereof. It will be noted that in accordance with the present invention, the particular coding of the CCS sequence field enables the processor 700 to detect an early point in time whether an instruction can be executed in the pipeline mode of operation.

It can also be seen from Figure 11 that non-EiS type instructions other than transfer class 55 instructions (T-RF = 1) which require indirect addressing and are not within the escape class (IES-C = 1) follow a path which causes the hardware control, circuits of block 704- 102 to switch to control state FWF-IND. For execute double and repeat instructions, XED or RPT, the hardware control circuits 704-102 switch to control store FESC. Thereafter, indirect address preparation is performed under microprogram control.

In accordance with the preferrred embodiment of the present invention, indirect address modification operations for instructions having the format shown in Figure 1 3a are performed under hardware control. These include register then indirect (M), indirect then register OR) and indirect then tally (IT). Other IT address modification operations requiring other than indirection are performed under microprogram control.

64 GB 2 080 989 A 64 As seen from Figure 11, when register indirect address modification is required (i.e., the tm field specifies a register than indirect type modification), the hardware control circuits of block 704-102 switch from the FWF-IND control state to the FPOA control state provided that the CCS field indicates that the instruction is not an execute double or repeat instruction (i.e., = 1).

The RI address modification is a 2T operation (i.e., FPOA (R1)---+ FWFINT -4 FPOA). During control state FPOA, when the tm portion of the instruction word contents of the RSIR register 704-158 indicate RI address modification, the processor circuits inhibit the loading of the CCS field address into the ECS address register 701 -10 of Figure 3b. Also, the processor 700 takes action to fetch from memory the indirect word specified by the effective address resulting under R type modification (i.e., generates a read single memory command as explained herein).

During control state FWF-iNT, the processor 700 under hardware control transfers in for the indirect word, having the format shown in Figure 13d, from cache unit 750 and forces the RI flip-flop of block 704-110 to a binary ONE. The RI flip-flop remains a binary ONE for the duration of the next FPOA control state. This flip-flop is used to force the R29 register 704-162 to a binary ZERO since the indirect word fetched from memory has its AR bit 29 set to a binary ONE (see Figure 1 3d).

As seen from Figure 11, when the tm field of the instruction specifies an indirect then register address indirect modification and the instruction is other than an execute double or repeat (i.e., OR + FIR) -XED. RPTS = ll the hardware control circuits of block 704-102 switch from the FWIZ- IND control state to the FIRT control state. The IR modification is a 3T operation (i.e.,

FPOMIR) --> FWF-IND --> FIRT---+ FPOA). The same operations mentioned in connection with RI modification are carried out during control state FPOA.

During control state FWF-IND, the control state flip-flop FIRT and the FIR flip-flop are forced to binary ONES. This state is followed by control state FIRT during which the original contents of the UDXA register 704-158 saved in the RRDXAS register 704-159 are transformed to RRI)XA register 704-158 where the address modification specified by the indirect word is either of R or IT type. At-this 2d point, the development of an effective address is complete (last indirection).

Also, the control flip-flop FIRL is forced to a binary ONE. The FIRL (flip-flop indirect fast) flip-flop remains a binary ONE for the duration of the next FPOA control state. Since the operation is not complete, the FIR flip-flop remains at a binary ONE during control state FPOA.

During the next control state FPOA, the FIRL flip-flop forces the R29 register 704-162 and RSIR 30 tag bits 30-31 to binary ZEROS. This completes the 1 cycle of operation for that instruction. A similar.

sequence is followed in the case of a non-execute double or repeat instruction requiring an indirect then tally address modification. This is a 3T operation (i.e., FPOA (IT) --> FWF-IND ---> FIT-1 -) FPOA). During control state FWF-IND, in addition to loading the indirect word into the processor registers (i.e., ZDI --,> RSIR, RDI and RIRDX-A, R29), the control state flip-flop FIT-[ is forced to a binary ONE and the 35 RRDXAS register 704-159 is forced to ZEROS.

During control state FIT-i, the ZERO contents of 13RDXAS register 704-159 are loaded into 11RDXA register 704-158. Also, the FIRL flip-flop is forced to a binary ONE. Similar to that described above, the R29 register 704-162 and RSIR tag bits 30-31 are forced to binary ZEROS by the FIRL flip-flop. The -Hardwired Control State Actions- section illustrates the various operations described above in greater detail. As seen from Figure 11, non-EIS type instructions which are not within the escape class and do not require generation of an effective address CE-IS - US-C - EA) follow a path to point XX. These instructions have the format of Figure 13a and their tm portion of their TAG fields are coded to specify no indirection (i.e., 00 code). As indicated, the tm portion of an instruction is tested for indirection during the FPOA cycle and when indirection is not specified, the control flag [EA is forced to 45 a binary ONE state.

As seen from Figure 11, the various groups of instructions following this path are those which reference CCS sequence fields coded to specify sequences listed within group A, group B, group C, TRF,

STR-SG1-, STR-HWU and STR-D13L. Instructions requiring group A sequences as well as those instructions whose processing has reached point B follow the path to point XXX. Point XXX in Figure 11 50 indicates the point at which processor 700 has completed the 1 cycle processing of an instruction and must then fetch the next instruction from the 1 buffer for processing. Before that can be done, the processor 700 must make certain that the instruction just completed has not placed it in an execute double or repeat loop (i.e., the instruction is not an XED or RPT instruction). If the processor 700 has been placed in a loop, the hardware circuits of block 704-102 switch to control state FXRPT followed 55 by control state FESC. This ensures that the processor 700 does not fetch the next instruction but instead control is transferred to the ECS control store 701-2 wherein the next operation(s) are carried out under microprogram control. More specifically, during control state FXRPT, the processor 700 under hardwired control forces the ECS control store 701-2 to the appropriate address and during control state FESC transfers control from the hardware circuits.

When the CCS sequence field indicates that the instruction is not an execute double or repeat type of instruction and that the control flag STR-CPR is a binary ONE indicating that the instruction buffer must be reloaded because of a store operation, the hardware circuits of block 704102 switch to control state FM-INIT. The STR-CPR flag is set to a binary ONE during a cache write operation when the address of the cache command equals the address of the instruction block. During this state, GB 2 080 989 A IS5 the processor 700 initializes the instruction buffer via the circuits of block 704-128. Thereafter, the hardware circuits of block 704-102 switch to control state FPIM-2 to fetch the next instruction. This state is followed by a return to control state FPOA as shown in Figure 11.

When the CCS sequence field indicates that the instruction is neither an, execute double or repeat instruction and the instruction buffer does not have to be reloaded because of a store compare operation ([T-R-CPR = 1), the hardware circuits of block 704-102 switch to one of three control states RIM-1, FPOA and FWF-IBUF as shown. In the case where the instruction buffer is empty (IBUF-EMPTY = 1), it switches to control state FPIM-1 to enable the fetching of instructions to fill the instruction buffer. After the instruction buffer has been filled, the hardware circuits of block

704-102 switch to control state FPOA to begin the processing of the next instruction. In the case 10 where the buffer is not empty, (IBUF-EMP = 1) but is ready for read out of the next instruction (IBURDY = 1) the hardware circuits of block 704- 102 immediately switch back to control state FPOA.

It will be noted from Figure 11 that in the event the instruction buffer is not in a ready condition 15. (IBUFRDY = 1), the hardware circuits of block 704-102 switch to the FWF-IBUF control state and 15 remain in that state until the instruction buffer is ready (IBUF-RDY = 1). When it is ready, the hardware circuits of block 704-102 switch to control state FPOA.

It will be noted that instructions which reference CCS fields coded to specify the sequences listed in group B follow the path labelled group B wherein the hardware circuits of block 704-102 switch from control state FPOA to control state FESC. Similarly, instructions which reference CCS fields coded 20 to specify the sequences listed in group C cause the hardware circuits of block 704-102 to switch to control state MEL followed by control state FESC. In each case, these instructions require operations which cannot be executed by processor 700 under hardware control but which required certain microinstruction routines for completing the processing thereof. 25 As seen from Figure 11, the instructions which reference CCS fields coded to specify STR-SGi- 25 or STR-HWU sequences are processed under hardware control provided these instructions do not require character address modifications (FCHAR = 1). In such cases, the hardware circuits of block 704-102 switch to control state FSTR. Those instructions which reference CCS field codes specifying an STR-DBL sequence, the 30 hardware circuits of block 704-102 switch from control state FPOA to the FSTR-DBL control state 30 followed by control state FSTR. In the case of each of three types of sequences mentioned, the hardware circuits of block 704- 102 follow a path back to point B for fetching the next instruction from the instruction buffer. In accordance with the preferred embodiment, the path labelled TSXn is followed when the CCS field is coded to specify the TSX instructions within the class. Initially, the path is the same as that followed by instructions within the ESC-EA class. Hence, similar operations in generating an effective address are performed by processor 700 during control state FPOA. Additionally, the instruction counter is updated by being incremented by one.

The hardware circuits of block 704-102 then switch to control state FTSM. During this state, the updated instruction counter contents are loaded into the BD] register 704-164. The hardware 40 circuits of block 704-102 switch control flag flip-flop FTSX2 to a binary ONE and thereafter switch to control state RI-INIT. The control flag flip-flop FTSX2 causes the processor 700 to reference effective address generated during control state FPOA and stored in TEAO during control state FP I-INIT. It will be appreciated that normally, the processor 700 references the address value IC + 0 + 0 during control state M-INIT. The hardware circuits of block 704-102 then switch to control state RIM-2 45 followed by control state FPOA.

It will be appreciated that Figure 11 only discloses the hardware operations relative to the 1 cycle of operation. As mentioned, the processing of a given instruction is performed to the extent possible under hardware control. Depending upon the class into which an instruction falls as specified by the CCS field establishes the operations performed during the FPOA control state and subsequent control 50 states. As explained herein and as seen from the section, Hardwired Control State Actions, the hardware circuits of block 704-102 as a function of the coding of the CCS sequence field, generates the appropriate type of cache command during control state FPOA. This action as well as the other actions occurring during the control states of Figure 11 are as indicated in the following section.

-:,: t-. 11 '.:

66 GB 2 080 989 A 66 HARDWIRED CONTROL STATE ACTIONS SECTION FP OA CO NTRO L STATE 1. If FINH-ADR = 1 then M29) + X(RRDX-A) + ADR(29)l --.> ASEA; if RSIRIO-31 00 te - n 1 EA; If RSIR,._, 00-then 0 EA; RBAS-M29) RSPP; 2. If FINH-ADR = 1 then [0 + 0 + R EA-TI -4 AS EA; 11 11. 1 + ZBASE --> ASFA; 1, EA 3. ASEA -4 REA; ASFA ---> RADO [$CACHE-REG = 1 If FTRF-TST= 1 then 0 --.> FTNGO If FMSK-29 = 1 then MASK R29 to 0 If FIRL = 1 then MASK RSIR 30, 31 to 00 0 --> FIR 1 4. 15 5.

6.

1 + ZBASE --> ASFA; 0 FRI 0 FIRL If (FTRF-TST. FT-RGo).TR--F-7EA-.-91-S = 1 and if EA. (I-D-SGI- + LD-HWU + RD-CLR + EFF-ADR + NO-OP) then 1 --> END; and if EA - (STR-SGL + STR-HWU + STR-DBL) = 1 then ZREG -+ RRDX-A; 0 ---> R29; and if TSXn - EA = 1 then]C + 1 --.> IC CCS -+ CCS-REG; CCS-00-1---+ RTYP,_1 and if EA [DEL-STR-SGL + DEL-STR-DRD + TSXn + INST-GRI + [E-A-.ES-Cl = 1 where INST-GR = LD-SGL-ESC + I-D-DBL- ESC + LD-HWLI-ESC + EFF-ADR-ESC + ESC-EA then 00 RBAS-B 7. If FT9F--TST.TRF. EA= 1 then a. []NIT-IBUF = 1; b. CCS CCS-REG; 8. If FTRF-TST. [TRGO. EIS If FREQ-DIR = 1 then [HOLD 1 = 1 If F-R-EG-DIR = 1 then RBIR.7=., -+ ZIDD27-35 R29, RRDX-A, FID, FRL; If BIT= 1 then 0 1 --> RTYP,-1; If IVITIVI-MTR = 1 then 00---+ RTYP,-1; If BIT. MTIVI-IVITIR = 1 then ZI B RTYPO-1 W30 -3, FAR ZI B --3 R S 1 R, R BAS-A; If (NEED-DESC). (IBUF-RDY) 1 then FTRF-TST = 1 then [READ-IBUF/ZIB (CUR) = 1 FTRF-TST = 1 then [READ-IBUF/ZiB (OPS) = 1 CCS -4 CCS-REG 9. If FPOA-0. RSIR31 then HOLD-1 ---.> 1 If FPOA-ID. RSIR - [ROLD- E then 1---+ FPOA-ID; If FP OA-1 D. [ffi-E then 0---+ FP OA-1 D 10. If FTW-TST = 1 and If [TRGO = 1 then Toggle FABUF-ACTV; If XED-RPTS 1 then 1 - FTRGP if [END = 1 then [RD1/ZRES13 = 1 If [T--RQ--U= 1 then Inhibit]C Strobe; 1 --. FTNGO 12. 0 -> FTR F-TST The bracket sign has been omitted from the term EDA throughout for sake of clarity.

67 GB 2 080 989 A 67 DMEM AND VALUES GENERATED DURING CONTROL STATE FPOA [MEM, [SZ for FPOA If FTRF-TST. [TRGO = 1 then [MEM = None; If [FTRF-TST + [TRGO). ESC = 1 then [MEM = None; If (FT-RF---M + [TRGO). EIS = 1 then [MEM = None; If (FTRF-TST + ffiR-GO)ESC. EIS wl-A = 1 then [MEM = Read Single; [SZ = S91; (FT-RF-TST + [TRGO) - EA If ESC-EA + DEL-STR-SGI--- + TSXn + DEL-STR-DI3L + NO-OP 1 then [MEM = None; If LD-SGI--- + LD-SGL-ESC + LD-SGL-DEL then FCHA. RRDX-A = DU. DL = 1 then [M EM = Read Single; [SZ = Sgi; FCHAR. RRDX-A = DU 1 then [M EM Direct; [S2= HWU; FC-HAR. R13DX-A = DL 1 then [MEM Direct; [SZ = HWL; FCHAR = 1 then [MEM = None If LD-HWU + LD-HWLI-ESC + LD-HWLI-DEL = 1 then If TRF = 1 then RRDX-A = 5O.WE = 1 then [MEM = Read Single; [SZ = HWU RRDX-A = DU = 1 then [MEM Direct; [SZ HWU RI3DX-A = DL = 1 then [MEM Direct; [SZ ZERO If STR-SGI--- = 1 then if FCHAR = 1 then [M EM =Write Single; [SZ Sgi and if FCHAR = 1 then [MEM = None if FT-RF--fS-T. FABUF-ACTV = 1 then (MEM = Inst. Fetch-l; [SZ = B and if FTRF-TST. FABLIF-AUT-V = 1 then [MEM = Inst. Fetch-l; [SZ = A and if FTRF-TST = 1 then [MEM = None If EFF-ADR + EFF-ADR-ESC = 1 then [MEM = Direct; [SZ = HWU If LD-DBL + LD-DBL-ESC + LD-DBL-FP-ESC = 1 then [MEM = Read Double If RD-CLR = 1 then [MEM = Read Clear If STR-DBL = 1 then [MEM = Write Double; [SZ DBL If STR-HWU = 1 then [MEM = Write Single; [SZ HWU If LD/STR-SGL-ESC = 1 then [MEM = Read Single; [SZ = Sgi; [R/W = 1 If LD/STR-HWLI-ESC = 1 then [MEM = Read Single; [SZ = HWU; [R/W = 1 FSTR CONTROL STATE 1. REG(RRDX-A) - ZX; 2. [ENAB-ZX-A2 = 1; 3. ZX, ZX-A2 --. ZDO; 4. ZRES13 -4 RADO; 5. [END = 1.

1. REGMDX-A) -) ZX; 2. [ENA13-ZX-A2 = 1; 3. ZX, ZX-A2 - ZDO; 4. ZFIESB -) RADO; 5. 00 10 --.> R13DX-A; 6. 1 ---> R29.

FSTR-D131---CONTROL STATE 68 GB 2 080 989 A 68 FESC CONTROL STATE 1. If [DIBUIF/P1PE = 10 + 11 or [PIPE = 001 + 1001 then [END = 1.

2.If [DIBUF/P1PE = 11 or [PIPE = 100] then 1 --.> FW17-REL.

FWF-IND CONTROL STATE M1 ---y RDI If (RI + [R + IT-P = 1 then Z131 RSIR Z131 -+ RRDX-A, R29 If R] -(5XED-RPTS) = 1 then 1 FRI If (IT-]). = 1 then 0 -4 RMXAS,-3 If IR. - = 1 then RRDX-A -+ ZRDXAS,-, and 1 ---> FIR.

FIT-1 CONTROL STATE 1. RRI)XAS --> RRDX-A,-3 15 2. 1 > FIRL FIRT CONTROL STATE 1. If RSIR-31 = 1 then RIRMAS --.> RR1DX-A and 1 --> FIRL 1. CS --> CCS-REG 1. IC -) ZX 2. ZX --. ZDO 3. MES13-+RD1 4. 1 >FTSX2 MPT CONTROL STATE FTSM CONTROL STATE FDEL CONTROL STATE 1. [0 + 0 + REA-TI -> ASEA; and [0 + 0 + REA-TI + ZBAS E --. AS FA.

2. ASEA ---> REA; ASFA -, RADO; and ZBASE33-35 ---> RBASE33-3.; and 3. [$CACHE-REG = 1.

4. If DEL-STR-SGI- = 1 then [MEM = WRITE SGL; [SZ = SGI---.

5. If DEL-STR-D131- = 1 then [MEM = WRITE DBL; [SZ = DBL.

6. If DEL-STR-SGL. DEL-STR-D-BI = 1 then [MEM = NONE.

7. If I-D-SGL-DEL + LD-DBL + LDHWU-DEL + 1 then [END.

M-INIT CONTROL STATE 1. If FTSX2 = 1 then [0 + RIC + 01 -> ASEA; If FTSX2 = 1 then [0 + 0 + REA-TI --.> ASEA; ASEA + ZBASE --> ASFA.

2. 0 --), FTSX2 40 3. ASEA->REA; ASIFA-YRADO.

4. [$CACHE-REG = 1.

5. AS EA --> R EA-T.

6. Toggle FABUF-ACTV.

7. [MEM = INST-FETCH1. 45 8. [HT-IBUF-OPS = 1.

MF CONTROL STATE 1. [4 + 0 + REA-TI---+ ASEA and [4 + 0 + REA-TI + ABASE --i, ASEA.

2. ASEA --> REA; ASFA -+ RADO (force 00 -) RADO 32-33) 3.' [$CACHE-REG = 1. 4. RBAS-B --> Z13AS-C; 0, REA ---> RDI; 1 ---> MF-TST. 5. M1 -4 RBIR, RSIR, RBAS-A, RRDX-A, R29. 6. [READ-IBUF/Z113 (OPS) = 1.

35.

69 GB 2 080 989 A H MF-NG CONTROL STATE 1. [0 + 0 + REA-TI --i, ASEA; and [0 + 0 + REA-TI + ZBASE -> ASFA.

2. [END= 1.

FPIM-1 CONTROL STATE 1. [4 + 0 + REA-TI --.> ASEA and [4 (forces 00 ---> RADO,,j + 0 + REA-TI + ZBASE --> ASFA.

2. ASEA->REMSFA > RADO (force 00 ---> RAD03.-33) and [$DCACHE-REG = 1.

3. ASEA -> REA-T; and [MEM = INST-FETCH1; and RBAS-B -> WAS-C.

FPIM-2 CONTROL STATE 1. [4+0+REA-T->ASEA.

2. ASEA---.> REA; and ASFA-> RADO (force 00 > RAD032-33); and [$CACHE-REG.

3. If ASFA-C27 = 1 then ASEA-> REA-T; ASFA, ZWS __+ RIB-VA, RI13-WS; and [MEM = INST-FETCH2; IPTR-CUR-SEL --> [SZ; and If ASFA-C27 = 1 then [MEM = NONE; and RBAS-B---+ Z13AS-C, and Z131 - RBIR, RSIR, RBAS-A, R13DX-A, R29, and [READ--iBUF/ZIB 1.

FWF-IBLIF CONTROL STATE 1. If IBUF-RDY = 1 then [READ-IBUF/IB (CUR), and ZIB --- > RBIR, RSIR, RBAS-A, RWX-A, R29.

FPIM-EIS CONTROL STATE 1. [4 + 0 + REA-TI --. ASEA; and [4 + 0 + REA-TI + ZBASE -y ASFA.

2. ASEA --> REA, and ASFA -+ RADO (force 00 -) RAD032-33); [$CACHE-REG = 1.

3. AS EA R EA-T; a n d [MEM INST-FETCH1; and RBAS-B, WAS-C; AiFA-C27, FEIS-STR-CP R; and ZIB --.> RSiR, RBAS-A; and If BIT. MTM-MTR- = 1 then ZIB - RTYP,-l; and If iBUF-RDY = 1 then [READ-IBUF/ZIB, and CCs---+ CCS-REG.

FWF-DESC CONTROL STATE 1. If IBUF-RDY = 1 then [READ-IBUF/ZIB; and CCS CCS-REG. ZIB _ RSIR, RBAS-A; and If BIT. WM-WITR- = 1 then ZIB ---> RTYP,11 FPOP CONTROL STATE 1. If FINH-AD = 1 then M29) EIS + X (RRDX-A, RTYP, FNUM) + ADR (29, RTYP')l - ASEA; M29) EIS + X (RRDX-A, RTYP, FNUM) + ADR (29, RTYP,)l + ZBASE-ASFA.

If FiNH-ADR = 1 then [0 + 0 + REA-TI --> ASEA; [0 + 0 + REA-TI + WASE >ASFA.

3. If FID = 1 then HOLD-E = 1 RSIR --.> ZIDD ZIDD -) RWX-A, R29 GB 2 080 989 A 70 FPOP CONTROL STATE - Continued 5.

A.

4. ASEA ---> REA; ASFA ---> RADO; [$CACHE-REG = 1; If FIG-LEN = 1 then ZLN --> RLEN ASEA --> REA-T (RDESQ [FID + FRI--- + FAFI] -). FINDA; (TYP = 6).FINH-ADR --> FINDC; TYP = 9 + FINH-A --), FINDB; FINDC + [SET-FINDC DINDC; FINDA + [SET-FINDA--, DINDA; FINDB + [SET-FINDB --> DINDB. 10 6. RDES = 00 (First Descriptor) If FNUM. EDIT= 1 then RS 1 R21-23 --. R 1 DW; RTYP,_1 ---> RTF 1; If FIG-LEN = 1 then RSI R24-35 --> RXPA, RLN 1 If FINH-ADR = 1 then ASFA34-,5 RP4 ASFAU-3. RPO if RSIR21 1 ASFA34-3. > RPO if RSIR21 1.

If 71TW. EDIT= 1 then RSIR21-23 --3 Rl DW; RTYP,_1 -+ RTFl; ASFA34-3. RM 10-2 RSIR24-29 --3, RXPA; If FIG-LEN = 1 then RSIRW-35 --.> R LN 1 If RSIR2, = 1 then ASFA34-., RPO If RSIR2, = 1 then AS17A.4-36 RPO.

If FNUM = 1 then RSIR24-29 _) RXPA; RSIR21-23 Rl DW; RTYPO(O) -> RTFl; ASFA34-3. - RCN 10-2 If FIG-LE = 1 then RSI R30-35 ---> RLN 1 I f R P-R21 = 1 then ASFA34-3. RPO If RSIR = 1 then ASFA34 36 RPO.

If [FM.VRILI. F7 A-Fl. (TYP = 6 + F] M-ADR)l = 1 then 1. 0 --. FINH-ADR, FIG-LEN 2. If MTIVI-MTR wherein DREV = MRL + TCTR + SCAN-REV 1 then 1 [READ- IBUF/ZIB; ZIB - RSIR, RBAS-A; 01 -+ RDESC; If TRAN = 1 then 11330 ---> FAF1; KTRANC= 1 then RBIR,-17-+ZIDD,7-,,---R29, R13DX,A, FID, FRL; If TRNAC = 1 then ZIB --> R29, RRDX-A; If SCAN. CMPC. CMPCT = 1 then ZIB --y RTYP; If EDIT = 1 then 0 ---> FNUM.

3. If [TCT + SCAN-FWD + MVT + CONVI IZLN24-35 = 0 + FIG-LENI.-E-l1 then MEM = PRE-READ.

4. If (NUM2 + NUM3 + EDIT) (ZLNW-., = 0 + FiG-LEN). FE1 1 then [MEM = PREREAD.

5. If M LR (ZLi\124-35 = 0 + F] G-LEN) - FE 11 = 1 the n (TYP = 9) - FESCD = 1 then [MEM = LD QUAD; 1 = [INIT-IBUF; and if (TYP = 9 " FESCD = 1 then [MEM = PRE-READ.

6. If (CMPC + CMPCT) (ZLi\124-35 = 0 + FIG-LEN). FE1 1 = 1 then (TYP = 9). FESCID = 1 then [MEM = RDSGL; [SZ = ZONED; (TYP = 9. FESCID = 1 then [MEM = PRE-READ.

7. If OTHERWISE = 1 then [MEM = NONE.

B. if [-FFD. TRIL - F-AFF1 - (TWYP = 6 + F[ N H-ADR)l = 1 then 1. [MEM =NONE.

7. RDESC = 01 (Second Descriptor) If EDIT. FNUM = 1 then 15.

RSIR21-23 _ R DW, TRYPO-1---+ RTF2; If FINH-ADR and RSIR21 = 1 then ASFA 34-35 RP 1 RSIR21 = 1 then ASFA34-36 RP 1 ASFAM-3. __+ RP6.

71 GB 2 080 989 A 71- FPOP CONTROL STATE - Continued If FNUM. EDIT= 1 then RSM21-23---+ R2DW, RTYPO-1 -) RTF2; ASFA RCN20-'2' If Fi -LE 1 then IRSIRW_., - RILN2.

A.

If FNUM = 1 then If FNUM = 1 then RSIR24-29 --- > RX1PB; RSIR21-23 --> R21)W1.

RTYPO, (0) - RTF2; ASFA34-., --> IRC1\120-2' If FIG-LEN = 1 then RSIRM-3. - FILN2.

If -lD. F151. P'A-Fl. (TYP = 6 + FI NH-ADR) = 1 then 1. 0 ---> FINH-ADR, FiG-LEN.

* 2. If (NUM3 + EDIT) = 1 then RBIRO-8 --. Zi DD27-35 --, R29, RIRDX-A, FID, FRIL; [READ-IBUF/ZIB (CUR); IR30 -+ FAF1 ZIB --> RSIR, RBAS-A, RTYP.

If (NUM2 + NUM3 41 EDIT) (ZLNW-3. = 0 + FIG-LEM.FE21 then [MEM = PRE-READ, 10 -Y PDESC if NUM2 + NUM3.

4. (ZLN24-35 = 0 + FIG-LEN). FE2 1.

5. If (CIVIPC + CIVIPCT) = 1 then [MEM = PRE-RD.

6. If OTHERWISE = 1 then [MEM = NONE.

3.

B. If T5D. F-RL. F-AFI(TYP = 6 + FINH-ADR) = 1 then 1. [MEM =NONE.

8.RDESC = 10 (Third Descriptor) If FNUM. EDIT= 1 then RSIR21-23 --> R 'I DW, If RTYPO-1 00 = 1 then 1 RTF3 If RTYPO-1 00 = 1 then 0 RTF3 If FIG-LEN = 1 then IRSIR24-35 + RILN 1 If FINH-ADR = 1 then ASFA.4-3. -+ RP4; If RSIR21 = 1 then ASFA34-3. IRPO if RSIR21 = 1 then ASFAb4-31 RPO.

If FNUM -EDIT= 1 then RSIR21-23 --'3' Rl DW, if RTYPO-1 00 = 1 then 1 > RTF3 If RTYPO-1 00 =A 1 then 0 ---> RTF3 If FIG-LEN = 1 then IRSIRM-., RILN 1 If RSIR2, 1 then ASFA34-3. Rpo IF RSIR21 1 then ASFA34-3. RPO.

RSIR21-23 --.> Rl DW; If RTYPO = 0 = 1 then 1 RTF3 If RTYPO:L- 0 = 1 then 0 RTF3 If FIG-LEN = 1 then RSIRM-3. --.> IRLW If RSIR21 = 1 then AS17A34-3. RPO If RS]RziI 1 then ASFA34-11 RPO.

A. If [RD. FRL F-A-FIRYP = 6 + FINH-ADR)l = 1 then 1. [MEM = NONE.

B. If [SET-FESC = 1 then 1 -+ FESCD.

FIDESC CONTROL STATE 1.[Y(29) + XffiRDX-A) + ADR(29)l ---> ASEA; ASEA --i REA; ASFA RADO; [CACHE REG = 1; If DU + D = 1 then [MEM = READ-SNGL; [SZ = SINGLE); 1 HOLD-E; 0 > FID; RBIR30 > FAFI; If RDESC = 00 then RBIR27-., > ZIDD --> R29, RRDX-A, FRL; If RDESC = 01 then RBIR 9-17 -> ZIDD -Y R29, IRRI)XA, FRIL; if RDESC = 10 then RBIR,_. - ZIDD---+ R29, R1RDX-A, FRIL.

1 + ZBASE --- ASFA; 72 GB 2 080 989 A 72 1. W1---+ RBIR, RBAS-A; HOLD-E 1 if RDESC 00 and FW17-1DESC CONTROL STATE if W7. WT-M-MTR = 1 then W1 = RTYP 5 If RDESC = 01 and if (SCAN + CMPC + CMPCT) = 1 then W1---4 RTYP If RDESC = 10 then W1 - RTYP.

ABBREVIATIONS OF TERMS USED IN THE HARDWIRED CONTROL STATE ACTIONS SECTION 10 1. Y(29) = R29 = RSIR0=17 -> ZY R29 = RSIR3.3.3.3-17 ---> ZY 2. Y(29) EIS = R2 9 = RS 1 RO-20 -) ZY R29 = RSIR3.3.3.3-20 ---> ZY 3. X(RRDX-A) = RSIR30 = ENA13-ZX as a function of 15 R13DX-A ESIR30 = DISABLE ZX 4. ADR(29) = R29 = 0 ---> ZZO-20 R29 = ZARO-19---+ ZZO-19; 0 - ZZ20 5. RBAS-M29) 20.

RSPP R29=0010-+RSPPO-3 R29 = 1,RBAS-A,-2 --> RSPPO-3 6. [READ-IBUF/ ZIB(CUR) = [READ-IBUF/ZIB FABUF-ACTV = 0 > DRDB 25 FABUF-ACTV = 1 DRDB 7. [READ-IBUF/ XIB(OPS) = [READ-IBUF/ZIB FABUF-ACTV = 1 DRDB FABUF-ACTV = 0 DRDB 30 8. [END = 1 f 7E-D RP-T -fP-L 5RD X E C t h e n ZIB---+ RBIR, RSIR, RBAS-A, RRDX-A, R29; If FT13F-TST. [TRGO = 1 and If (f-BO-F-EMPTY. IBUF-RDY) = 1 then [READ-IBUF/ZIB(OPS); 35 If FTRF-TST = 1 and If El-S + FTRFNG = 1 then]C + 1 - IC; If EIS. FTRFNG = 1 then]C + CCS-RO813 Now, the operation of the apparatus of the present invention will be described with reference to several instructions. Byway of example discussed.with specific reference to the flow chart of Figure 12, 40 it is assumed that the instruction buffer contains a pair of instructions which correspond to a load A (LDA) followed by an add to A (ADA) instruction. These instructions have the format shown in Figure 130. For ease of explanation and the description given above, it will be assumed that the tm portion of the tag field of each instruction does not specify an indirect address operation. Also, it is assumed that the instructions do not specify a direct upper (DU) or direct lower WL) type of operation.

The first instruction (LDA) is assumed to have an address specifying the first word (0) of a 4 word block which does not reside in cache unit 750 while the second instruction (ADA) has an address specifying the third word of the same 4 word block. The fastesttime that a block can be forwarded by main memory 800 to cache unit 750 is two words followed by afree cycle during which no information is forwarded which is followed by two more words. During that free cycle, the processor 700 is able to 50 execute the ADA instruction except that as explained herein the required data word will have not been received from main memory 800. The following example illustrates how the arrangement of the present invention prevents interference between commands resulting from processing the two instructions and eliminates the issuance of duplicate commands. This is done while the amount of overlap necessary in processing instructions in a pipelined fashion.

The operation codes of the LDA and ADA instructions referenced locations in the CCS control store 701-2 including CCSS fields having the code 000000. This means that the LDA and ADA instructions are included within the I-D-SGI- class.

Referring to Figure 11, it is seen that the processor hardware circuits in completing the 1 cycle operation takes path FPOA--. point XXX-.> FPOA. During the FPOA control state, the processor 700 60 performs under hardware control the following operations. It generates an effective address as a 73 GB 2 080 989 A 73.

function of the contents of R29 register 704-162, RBAS-A register 704-156 and R13DX-A register 704-158. The resulting effective address is loaded into the REA register. It is also added to the base address and thereafter loaded into the RADO register 704-46 of Figure 3e. Since the trn portion, the instruction tag field does not specify indirection, the control flag EA is forced on a binary ONE. Also, a code (RBIR 24-26) specifying the A register is loaded into RREG register 714-42 of Figure 39.

As mentioned, the CCS field referenced by the LDA instruction is coded to specify a I-D-SG1 sequence. Since the td portion of the tag field of the instruction does not specify a DU or DL operation, the processor circuits of block 704-108 generate a read single command to be issued to cache unit 750 under hardware control.

In greater detail, the generated address corresponding to the descriptor absolute address loaded 10 into the RADO register 704-46 serves as the command address. Additionally, command bits 104 and zone bits 5-8 are generated by the circuits 704-118 of Figure 3c and switch 704-40. These signals are applied through switch 704-40 in place of bits 1-8 from switch 704-46 while bits 0 and 9 are forced to ZEROS. The zone bits 5-8 are set to binary ONES since they are not used for read commands. Command bits 1-4 are converted to a command code of 0111 by the decoder circuits of 15 block 704-118. This command code specifies a memory read quad operative forfetching a 4 word block from main memory 800.

The circuits of block 704-108 in response to the CCS field and control state signals from block

704-102 operate to generate hardware cache memory command control signals [MEMOTB through [MEM3T13. In the case of a cache read single command, the signals [MEMOTB through [MEM3TI3 20 correspond to a code of---1000---. The circuits of block 704-108 generate the signals [MEMOTB through [MEM3T13 in accordance with the following Booiean expressions:

[MEMO-TB = FDEL. DELSTRG + T ER M G. [A.-[-l-S.-E-SC.-f-RF TERMG. FCHAR. EA. DU-DI---. (STRG + RDCLR I-DDI3LG + I-DHWUG + LDSGLG).

WEM 1 FPOA.TRF. EA. FTRF-T9T FTRF + F1PIM-2 + FPI-INIT + F1PIM-1 F1PIM-ElS+ FDEL. DELSTRG + FPOA - TERIVIG. EA. FCHAR. STRG 30 + EIS TERMA + EIS TERMB [MEM2-TB = TERMG. EA. [I-DDI3LG + STRDBL FDEL. DEL-STR-DBL1 EIS TERMA + EIS TERMB.

[MEM3-TI3 = FTRIF + F1PIM2 + TERIVIG. EA. [(DU-DL) -R-HAR + RD-CLR + EFFADRG1 + EISTERMA.

wherein TERMG = FPOA. (FTRF-TST + [TRGO); EIS TERMA = FPOP. DESCO. FE1 1 N.(CMPC + CIVIPCT + SCAN-FWD + MW + TCT + CONV + DNUM2 + DNUM3 + EDIT) 40 + FPOP - DESC 1. FE2N (DNUM2 + DNUM3 + EDIT + CMPC + CIVIPCT); and, EIS TERMB = FPOP - DESCO. FE1 1 N. MLR.

These expressions show the relationship between the CCS codes and the command signals applied to the DNEM lines.

Other circuits included within block 704-108 decode the CCS field and generate the [SZ signals which indicate which half of the RDI register 704-164 is to be loaded. The [SZ signa ' Is serve as a size indicator providing information as to whether it is a direct upper (DU) or direct lower (DL) operation or single operation. In the case of a read single operation, the [SZ signals are binary ZEROS.

The circuits of block 704-106 force the register strobe signals [CACHEREG and [CCS to binary 50 ONES. The signal [CACHE-REG loads the read single command code into the RMEM register 704-130 while the [CCS signal loads the address of the CCS word applied via the bus 704-204 to be loaded into the ECS address register 701-10 of Figure 3b. The cache command code stored in RMEM register 704-130 is applied via the decoder circuits of block 704- 118 to the DMEM lines while the command word loaded into the RADO register 704-46 is applied to the cache unit 750 via 55 the RADO/ZADO lines. Also, the decoder 704-120 in response to signals [MEMOTB through [MEM3TI3 forces REOCAC flip-flop 704-134 to a binary ONE. This signals the cache unit 750 of the command. During control state FPOA, the processor 700 under hardware control performs an [END operation wherein it updates the instruction counter and loads the next instruction (ADA) into the RBIR, RSIR, 74 GB 2 080 989 A 74 RBAS - A, RRM-A and R29 registers. Also, the hardware circuits of block 704-102 switch back to control state FPOA to begin execution of the ADA instruction during the next or second cycle of operation.

The ADA instruction also requires one cycle for completion. The processor 700 carries out the ' same operations as discussed in connection with the LDA instruction. The only difference is in the E 5 cycle wherein a different micro-instruction is specified by the CCS address.

During the next cycle which corresponds to a second FPOA cycle, the cache unit 750 executes a cache cycle of operation in parallel with the 1 cycle operations.

As concerns cache unit 750, in response to the DRE12CAC line being switched to a binary ONE, the read single (ZAC) command applied to lines ZPSWAO-39 is written into an empty location of the RZAC buffer 750-102 specified by the contents of counter 750-106. As mentioned, the address of this location is determined by the states of the busy bits. However, by way of example, it is assumed that the buffer 750-102 is empty and all the busy bits are reset. Therefore, the ZAC command is written into location 0. This entry is made independently of whether there is a hit or miss condition (i.e., state of BPSD).

Referring to Figure 12, it is seen that when the RE12CAC line is a binary ONE, the cache unit 750 accesses the directories 750-500 and 750-502 and cache storage 750-700 utilizing the address signals from the RADO lines 25-33 applied via switch 750-702. This is done with the decoding of the cache command applied to the lines DIVIEM0-3 by decoder 750-166.

The comparison circuits 750-536 through 750-542 compare the LDA instruction address with 20 the address read out from directory 7 50-502. Since the word specified by the LDA instruction is not in cache, the circuits 750-560 hold hit signal BSPD at a binary ZERO. However, during the directory search cycle, before the cache unit 750 detects a hit or miss condition, the ZAC command is loaded into SIU output register 750-174 via the ZPSWA switch 750-110 and ZPSW switch 750-178. The cache unit 750 assumes a miss condition.

As seen from Figure 12, since the result of the directory search cycle is a miss, the decoding of the read single cache command causes the control state flip-flops CAOPR, UGCOGTH and R13PSD of blocks 750-3 to be set to binary ONES. This causes the cache unit 750 to execute the three parallel operations indicated in Figure 12 during the next cycle of operation which corresponds to a directory assignment cycle. Because of the miss condition, the cache unit 750 sets the busy bits (a pair) and advances by one the address pointer (not shown) to the next empty location (location 1). Since this is read quad command, a pair of busy bits are set to binary ONES and the resulting value is loaded into the MIFS register 750-138. This coding is used to identify which words of the read quad command are outstanding.

Under the control of the UGCOGTH control state flip-flop, the cache unit 750 performs a directory 35 assignment cycle wherein the upper address bit signals included with the ZAC command address previously written into RZAC buffer 750-102 are passed through ZAC switch 750-152 and instead of being compared as in the previous cycle are written into directory 750- 502 at the location specified by the address applied CADDLO-6 of the block designated by the contents of block register 750-524. The block address as described above is generated in accordance with the state of the 40 full/empty (F/E) bits or the round roben (RR) bit when all of the full/empty bits are set indicating that all of the blocks are full and one must be replaced. As mentioned, these bits are read out during the directory search cycle and decoded to establish the available block address.

As seen from Figure 12, the cache unit 750 generates signals which set the full/empty bit corresponding to the specified block to a binary ONE thereby indicating that the location contains valid 45 data. Also, the cache unit 750 sets the pending bit corresponding to that same block to a binary ONE in accordance with the state of signals BI(DICD0-3. These signals are applied via an OR circuit or block 750-512. It will be noted from Figure 4, that decode of the block location being written into corresponding to signals BK13CD0-3 are also written into a register location of,block 750-520 specified by address signals PRZACWO-1. This indicates which pending bit to reset at a later time when the 4 word of the requested block have been received.

The pending bit when set indicates that the operation is n6w outstanding. Additionally, during the directory assignment operation, the cache unit 750 under the control of the CAOPR flip-flop makes a request to the SIU 100 for a memo operation.

In greater detail, the CAOPR flip-flop forces the AOPR to a binary ONE signaling the SIU 100 of the 55 memory request. At that time, the cache unit 750 applies the ZAC command to the DT'S lines together with the appropriate memory identifier signals and steering signals being applied to the MITS and WTS lines respectively. The memory identifier signals generated by the setting of the busy bits in response to the read quad command are applied via the MITS register 750-138 previously loaded via register 750-106 and switch 750-139. The steering signals are generated in a conventional manner by means, not shown. For further information regarding the use of steering signals, references may be made to U.S. Patent No. 4,006,466.

The SIU 100 signals acceptance of the cache memory request by forcing line ARA to a binary ONE. As seen from Figure 12, the cache unit 750 under the control of the R13PS1) flip-flop turns off processor 700 by forcing the CPSTOPOO line to a binary ZERO. This completes the series of parallel GB 2 080 989 A 75 actions generated in response to the signal applied to the DREWAC line which is indicated by the END symbols.

At this time, all flip-flops except the R13PSD flip-flop (i.e., CAOPR, UGCOGTH, etc.) are reset to binary ZEROS until the occurrence of a next cache request.

As seen from Figure 12, the remaining operations performed by cache unit 750 occur as a result 5 of responses from main memory 800 indicated by forcing the ARDA line to a binary ONE. It is assumed here that the main memory 800 is able to process the cache read quad command immediately wherein it is operative during a next cycle to transfer a first pair of data words of the requested block. Upon such transfer, the SIU 100 forces the ARDA line to a binary ONE indicating that the even word of the pair (assume word 0) is available on the DFS lines. The SIU 100 also forces the DPFS line to a binary ONE 10 indicating a double word transfer.

During the time the ARDA line is a binary ONE, the cache unit 750 loads the first data word into the RP register 750-179. Also, multiport identifier signals from the MIFS lines indicating the pair of words being transferred are loaded into the RMIFS register 750-125. It is assumed that the MIFS signals indicate that word 0 and 1 of the desired 4 word block are being received (e.g. a code of 000). 15 Bits 2 and 3 of the MIFS signals stored in register 750-125 are used to access the ZAC read command stored in location 0 of the RZAC buffer 750-102. The address is applied via the ZAC switch 750-152 to the cache storage 750-700 and directories 750-500 and 750-502.

In parallel, with accessing directories 750-500 and 750-502 and cache storage 750-700, the first data word is transferred to the RDO register 750-180. The signal applied to the DPFS line 20 switches the OATB flip-flop to a binary ONE. Under control of this flip- flop, the second word (word 1) is loaded into RP register 750-179. Thereafter, it is loaded into the RD1 register 750-180. Upon the occurrence of a next clock pulse, the THM flip-flop switches to a binary ONE. Under the control of this flip-flop, the pair of words (words 0 and 1) are written into the block location of cache storage 750-700 specified by the ZAC command address bits via ZAC switch 750-152. Also, the first busy 25 bit is reset in accordance with the coding of the MIFS 1 -3 signals.

As seen from Figure 12, the cache unit 750 transfers the requested data word (word 0) to the processor 700 by forcing signals OPSWO-2 to predetermined pattern for enabling the transfer of word 0 via WO switch 750-9 and ZBP switch 750-902.

Also, the cache unit 750 forces the DATA-RECOV signal to a binary ONE enabling the data word 30 to be strobed into the processor's register. At the end of the THCFD cycle, the RBPSD flip-flop is permitted to reset to a binary ZERO. This causes the CPSTOPOO line to switch to a binary ONE turning on processor 700. However, the processor 700 does not perform any operations until the following cycle.

At this point, only the first pair of words has been received and there are still two words outstanding. The processor 700 having completed the 1 cycle operations relative to the ADA instruction will have generated another ZAC read command in the same manner previously described. The difference is that this comand includes an address specifying word 3 of the block being fetched.

However, since the processor 700 was being turned off, cache unit 750 did not accept the seocnd read command applied to the RADO/ZADO lines. Once the processor 700 is turned on, the cache unit 750 is 40 operative to accept the read command coded to specify a read quad operation applied to the RADO/ZADO lines. At this time, the DMEM lines are again set to specify a cache read single command while the DREXAC line is set to a binary ONE. In a similar manner, the cache unit 750 writes the second read command into location 1. Also, during this cycle, processor 700 completes its execution of the LDA. Instruction under microprogram control. That is, the requested data word is loaded into the A 45 register as a function of the contents of the RWX-B register.

In the manner previously described, the cache unit 750 performs a directory search by applying the upper address bits to the directories 750-500 and 750-502. This time, while the comparator circuits of blocks 750-536 through 750-542 generate an output indicative of a hit, the pending bit inhibits the directory hit/miss detection circuits 750-560 from forcing signal BPSD to a binary ONE. 50 Also, the signal PENBIT used to generate the signals for setting the busy bit indications is a binary ZERO.

This inhibits the setting of such indications within the registers 750120 and 750-122.

As seen from Figure 12, since pending bit for the requested block has been set to a binary ONE, cache unit 750 is operative to perform the 4 sets of indicated parallel actions. Of course, when the pending bit is not set to a binary ONE, the cache unit 750 transfers the requested word to processor 700. First, the set pending bit causes the P13PS1) flip-flop to be switched to a binary ONE which in turn results in the processor 700 being turned off. It remains turned off until the requested data word is received from main memory 800.

Also the set pending bit inhibits control flip-flop CAOPR from being set to a binary ONE. Thus, from the operation of the circuits generating requests to main memory 800, the command is viewed 60 effectively as a miss forced by the set pending bit. This action prevents the issuance of a duplicate command to main memory 800.

It can be seen from Figure 12 that the set pending bit causes the ZCDL, the PENBIT-WAIT and PENBIT flip-flops to be set to binary ONES. The WDL flip-flop establishes a waiting state used as explained herein to reinitiate the execution of other corrpmands stored in the FIZAC buffer 750-102. 65 76 GB 2 080 989 A 76 Thus, when conflicts concerning redundant commans or overlap conditions which could result in transferring incorrect data to processor 700 are detected by the cache unit 750 resulting in the setting of a pending bits, this causes the ZC-DL flip-flop to be set to binary ONE.

The PENBIT-WAIT flip-flop when set to a binary ONE defers the execution of the sequence of operations beginning with state PRE-OK until all outstanding memory commands requesting data from main memory whose. execution has been blocked by the setting of the pending bit have been processed. Of course, this is with the exception of the command currently being executed by cache unit 750.

The PENBITflip-flop when set essentially establishes the conditions that existed during the initial receipt of the command (DREGCAC) that were not responded to because of the pending bit being set to 10 a binary ONE. Until requested data has been received, the ZCDL flip-flop remains set to a binary ONE. While a binary ONE, it ensures that processor 700 remains turned off in all cases.

In the present example, next the main memory 800 forwards the first word (word 2) of the requested 4 word block to cache unit 750. That is, upon such transfer the SIU 100 again forces the ARDA line.to a binary ONE indicating that the even word of the pair (word 3) is available on the DFS lines. Again, the SIU 100 also forces the DPFS line to a binary ONE indicating a double word transfer.

Duri.ng the time the ARDA line is a binary ONE, the cache unit 750 loads the third data word into the RP register 750-179. Also, multiport identifier signals from lines MIFS coded to indicate the transfer of a second pair of words of the requested block are loaded into the RMIFS register 750-125.

That is, the MIFS signals indicate that words 2 and 3 are being received (e.g. code of 100).

Additionally, the MIFS signals select the portion corresponding to location 0 to establish whether the word pair being received is the second pair. Since it is the exclusive OR circuit 750-131 forces the BB set signal to a binary ONE. This causes signal SECRCV to be forced to a binary ONE. In the manner previously described, MIFS bit signals 2 and 3 are used to access location 0 of RZAC buffer 750-102 which stores the first ZAC read command now being executed. The command address is applied via the 25 ZAC switch 750-152 to the cache storage 750- 152 to the cache storage 750-700 and directories 750-500 and 750-502.

In parallel with such accessing, word 3 is transferred to the RDO register 750-180.

Upon the switching of the OATB flip-flop, the second word (word 3) is loaded into the RP register 750-179. Thereafter, it is loaded into the RD l register 750-180. Upon the occurrence of a next clock pulse, the THCFD flip-flop switches to a binary ONE. Under the control of this flip-flop, the second pair of words (words 2 and 3) are written into the block location of cache storage 7 50-700 specified by the ZAC command address bits applied from ZAC switch 7 50-152.

Also, the second busy bit is reset in accordance with the coding of the MIFS1 -3 signals at the end of cycle THM. Since signal SECRCV is a binary ONE,Ahis causes the pending bit to be reset to a binary ZERO. Resetting takes place via an AND circuit included within block 750-512. The circuit ANDs the complemented signals PSPENO-3 with the present contents of the pending bit signals read out from the read pending section of directory control 750-500. The RMIF bit signals 2 and 3 are used to select the register storing the previously written BKDCDO-3 signals, the complement of which correspond to signals RSPENO-3. The result is that the previously set pending bit is masked out and 40 the resulting value is written back into directory control 750-500. Thus, only the previously set pending bit is reset to a binary ZERO.

As seen from Figure 12, upon completing the execution of the first read single command, the PENBIT-WAITflip-flop is permitted to reset to abinary ZERO. The reason is at this time there are no outstanding read commands involving main memory (i.e., not awaiting receipt of further data from memory). The operations for this series of actions are completed as indicated by the END symbol. The resetting of the PENBIT-WAIT flip-flop enables the cache unit 750 to initiate the timing sequence following state ZCDL.

Since processor 700 has not completed the processing of the second read command, the read address pointer value supplied from an out counter, not shown, has not been advanced. Thus, when this 50 value is compared against the address indicative of the next empty location, the result indicates there is still a read command residing in RZAC buffer 750-102.

Accordingly, the PRE-OK flip-flop is switched to a binary ONE. When set, this flip-flop indicates that the cache unit 750 tried to execute a read command and formed the pending bit set which corresponds to the block specified by the command address. Under the control of the PRE-OK flip-flop, 55 thd read command stored in location 1 specified by the out counter (COUT) is accessed and the command address is aplied via ZAC switch 750-152 to the directories 750- 500 and 750-502 and cache storage 750-700.

Following the fetching of the command, the PRE-OK flip-flop is reset while the UG-OK flip-flop is set to a binary ONE. This flip-flop enables the cache unit 750 to perform operations similar to those 60 performed in response to the setting of the DREO.CAC line. However, such actions will not include the turning off of processor 700, the making of a directory assignment and the sending of a memory request.

Under the control of the UG-OK flip-flop, the cache unit 7 50 performs a directory search 1 operation. Since the initiation of this sequence of operations is being performed fora read. command 65 till 77 GB 2 080 989 A 77 whose operation was deferred, the comparator circuits of blocks 750-536 through 750-542 generate an output indicative of a hit condition. Since the pending bit associated with the specified block has been reset, the cache unit 750 performs the remaining operations indicated.

It will be noted that when the UG-OK flip-flop was set to a binary ONE, this enabled the PENBIT flip-flop to be reset to a binary ZERO (i.e., UGOK. LDCAC.CAC 1 = 1). This in turn completed the actions associated with the PENBIT flip-flop as indicated by the END symbol. Accordingly, this permits the processor 700 to be turned on during state UG-OK. However, before that, the out counter address is incremented by one and the requested data word (word 3) is transferred to processor 700. At that time, the signal DATARECOV is forced to a binary ONE enabling the strobing of the processor's registers. This completes the sequence of actions at the end of which the UG-OK flip-flop is reset to a 10 binary ZERO. During the next cycle of operation, processor 700 under microprogram control executed the ADA instruction. That is, the execution unit adder 714-20 adds the contents of the A register selected as a function of the RRM13 register contents applied to the ZEB lines to the value applied to the RDI lines by cache unit 750. The result is transferred to the A register via the ZRESA bus and switch 15, 714-36.

It will be appreciated that if there are more deferred commands, the same sequence is executed but the ZCDL flip-flop is not permitted to reset to a binary ZERO. The ZCDL flip-flop is only permitted to reset when there are no more commands outstanding. An example where additional read commands may be deferred is the situation where processor 700 issues two pre-read commands followed by a read single command.

Additionally, it will be noted that the arrangement of the present invention prevents conflicts during the fetching of new instructions. For example, it is assumed that processor 700 begins the processing of a transfer instruction. During the 1 cycle operation, the processor 700 generates a pair of commands accompanied by cache 1 fetch 1 and 1 fetch 2 commands applied via the DMEM lines. In the manner previously described, the cache unit 750 is operative to set a first pending bit in response to the 25 1 fetch 1 command and a second different pending bit in response to the 1 fetch 2 command. When the cache unit 750 receives the 4 words of a block from main memory 800, it turns on processor 700 which begins the execution of a first instruction within the first fetched block. That is, the 1 fetch 2 command is handled similar to a pre-read command in that the processor 700 can continue its operation during the fetch operation.

Such instruction is assumed to be a load A instruction which includes an address designating one of the words of the block being fetched in response to the 1 fetch 2 cache command.

Accordingly, the cache unit 750 in response to the read single command generated in response to the load A instruction is operative upon detecting the presence of the set pending bit to defer execution of the read command until ail of the words of the block specified by the 1 fetch 2 command have been 35 received. Also, the processor 700 is turned off. When the words of the second block have been received, the cache unit 75performs operations similar to those described in connection with the second read command discussed above.

From the foregoing, it is seen how the arrangement of the present invention prevents interference between memory commands as well as the issuance of duplicate commands. Additionally, the rrangement of the invention can be used to facilitate diagnosis of the cause of processor errors or failures. In the system of Figure 1, the input/output processor 200 has the capability to issue PI commands for the purpose of examining the contents of different registers within processor 700.

Additionally, this includes the capability of examining the contents of storage sections within cache unit 750. Assuming the presence of an apparent failure within processor 700, the processor 700, 45 the processor 200 would issue a PI command coded to specify that the flush counter 750-1000 be loaded with a particular address.

Upon the decoding of the PI command, the appropriate signals are generated which cause an address value applied to lines ZPIDT29-35 to be loaded into the counter 750-1000.

Next, the processor 200 issues a second P] command coded to specify a read operation. A predetermined portion of command signals are applied via the ZP1139-1 0 to the decoder circuits 750-1002. During cache read operation, the circuit 750-1002 generates signals which select the appropriate set of control directory signals (i.e., signals RSPENO-3, OLDPENDO-3, RDR F/E0-3, em). These signals together with the upper address signals from directory 750-502 are applied to the OR circuits of block 750-712 and forwarded to the processor 200 via the PDTS lines of P] interface 55 602. By examining the states of the pending bit signals, the processor 200 is able to establish unsuccessful completion of the process of issuing a memory request and receiving back all of the words of a block. In such an instance, the processor 200 fetches from directory 750-502 the addresscorresponding to a set pending bit. Upon receiving such address signals and appending the signals to the lower address signals, processor 200 could then access main memory 800 to find out what instruction or data was being executed or accessed at the time of failure. Thus, by being able to examine the pending bit contents of control directory 750-500, it is possible within a short amount of time to narrow down the problem to a particular area.

78, GB 2 080 989 A 78 APPENDIX A SINGLE WORD INSTRUCTIONS DATA MOVEMENT' LDA Load A 5 LDT Load Q LDAQ Load AQ LDAC Load A and Clear I-DGC Load Q and Clear LDXn Load Xn (n = 0, 1 7) 10 LXLn Load Xn from Lower (n = 0, 1.... 7) LCA Load Complement A LREG Load Registers LCO. Load Complement Q LCAG Load Complement AQ 15 I-CXn Load Complement Xn (n = 0, 1, 7) EAA Effective Address to A EAQ Effective Address to Q EAXn Effective Address to Xn (n = 0, 1 7) LDI Load Indicator Register STA Store A 20 STQ Store Q STAQ Store AQ STXn Store Xn into Upper (n = 0, 1, 7) SXLn StoreXn into Lower (n = 0, 1---. 7) SREG Store Register 25 STAC Store Character of A (6 bit) STCQ Store Character of Q (6 bit) STBA Store Character of A (9 bit) STBO, Store Character of Q (9 bit) 30 STI Store Indicator Register STT Store Timer Register SBAR Store Base Address Register STZ Store Zero STC1 Store Instruction Counter plus 1 35 STC2 Store Instruction Counter plus 2 ARS A Right Shift GRS Q Right Shift LRS Long Right Shift ALS A Left Shift QLS Q Left Shift 40 LLS Long Left Shift ARL A Right Logic O.RL Q Right Logic LRL Long Right Logic 45 ARL A Left Rotate 0LR Q Left Rotate LLR Long Left Rotate ADA ADO ADAQ ADXn ASA ASQ ASXn ADLA ADLQ ADLAQ ADLXn AWCA FIXED POINT ARITHMEtIC Add to A Add to Q Add to AQ Add to Xn (n = 0, 1---. 7) Add Stored to A Add Stored to Q Add Stored to Xn (p = 0, 1,.. 7) Add Logic to A Add Logic to Q Add Logic to AQ Add Logic to Xn (n = 0, 1.... 7) Add With Carry to A GB 2 080 989 A 79 APPENDIX A (cont'd) SINGLE WORD INSTRUCTIONS FIXED POINT ARITHMETIC (contd) AWCQ, Add with Carry to G ADL Add Low to AQ. 5 AOS Add One to Storage SBA Subtract from A S130, Subtract from Q SBAQ Subtract from AQ SBXn Subtract from Xn (n = 0, 1 7) 10 SSA Subtract Stored from A SSO. Subtract Stored from G SSXn Subtract Stored from Xn (N = 0, 1 7) SBLA Subtract Logic from A SBLQ Subtract Logic from Q 15 SBLAQ Subtract Logic from AQ S131-Xn Subtract Logic from Xn (n = 0, 1.... 7) SWCA Subtract With Carry from A SWCQ Subtract With Carry from G Mpy Multiply Integer 20 MPF Multiply Fraction DIV Divide Integer DVF Divide Fraction NEG Negate A NEGI- Negate Long 25 BOOLEAN OPERATIONS ANA AND to A ANG, AND to Q ANAQ AND to AQ ANXn AND to Xn (n = 0,.1 7) 30 ANSA AND to Storage A ANSO, AND to Storage Q ANSXn AND to Storage Xn (n = 0, 1 7) ORA OR to A ORQ OR to Q 35 6RAQ OR to AQ ORXn OR to Xn (n = 0, 1 7) ORSA OR to Storage A ORSQ OR to Storage Q ORSXn OR to Storage Xn (n = 0, 1 7) 40 ERA Exclusive OR to A ERO, Exclusive OR to Q ERAQ Exclusive OR to AQ EFIXn Exclusive OR to Xn (n = 0, 1 7) ERSA Exclusive OR to Storage A 45 ERSQ Exclusive OR to Storage G ERSXn Exclusive OR to Storage Xn (n = 0, 1 7) COMPARE CMPA Compare With A CIVIPO, Compare With Q 50 CMPAQ Compare With AQ CMPXn Compare With Xn (n = 0, 17) CWL Compare With Limits CMG Compare With Magnitude CIVIK Compare Masked 55 SZN Set Zero Negative Indicators from Memory SZNC Set Zero Negative Indicator from Storage and Clear GB 2 080 989 A 80 APPENDIX A (cont'd) SINGLE WORD INSTRUCTIONS COMPARE (cont'd) CANA Comparative AND With A CANQ Comparative AND With Q 5 CACAQ Comparative AND With AQ CACXn Comparative AND With Xn (n = 0, 1 7) CNAA Comparative NOT With A CNAQ Comparative NOT With Q CNAAQ Comparative NOT With AQ 10 CNAXn Comparative NOT With Xn (n = 0, 1 7) FLOATING POINT FLD Floating Load DFLD Double Precision Floating Load LDE Load Exponent Register 15 FST Floating Store DFST Double Precision Floating Store STE Store Exponent Register FSTR Floating Store Rounded 20 DFSTR Double Precision Floating Store Rounded FAD Floating Add UFA Unnormalized Floating Add DFAD Double Precision Floating Add DUFA Double Precision Unnormaiized Floating Add ADE- Add to Exponent Register 25 FS13 Floating Subtract UFS Unnormalized Floating Subtract DFS13 Double Precision Floating Subtract DUFS Double Precision Unnormalized Floating Subtract FIVIP Floating Multiply 30 UFM Unnormalized Floating Multiply DFIVIP Double Precision Floating Multiply DUFM Double Precision Unnormalized Floating Multiply FDV Floating Divide F1)l Floating Devide Inverted 35 DFDV Double Precision Floating Divide DF131 Double Precision Floating Divide Inverted FNEG Floating Negate FNO Floating Normalize 40 FRD Floating Round DFRD Double Precision Floating Round FCMP Floating Compare FCMG Floating Compare Magnitude DFCIVIP Double Precision Floating Compare 45 DFCMG Double Precision Floating Compare Magnitude FSZN Floating Set Zero and Netative Indicators from Memory TRANSFER OF CONTROL TRA Transfer Unconditionally TSXn Transfer and Set Index Register TSS Transfer and Set Slave 50 RET Return TZE Transfer on Zero TNZ Transfer on Not Zero TMI Transfer on Minus TPL Transfer on Plus 55 TRC Transfer on Carry TNC Transfer On No Carry TOV Transfer on Overflow 81 GB 2 080 989 A 81APPENDIX A (cont'd) SINGLE WORD INSTRUCTIONS TRANSFER OF CONTROL (cont'd) TEO Transfer on Exponent Overflow 5 TEU Transfer on Exponent Underflow TTF Transfer on Tally Runout Indicator OFF TTN Transfer on Tally Runout Indicator ON TPNZ Transfer on Plus and Nonzero TMOZ Transfer on Minus or Zero TRTN Transfer on Truncation Indicator ON 10 TRTF Transfer on Truncation Indicator OFF MISCELLANEOUS NOP No Operation BCD Binary To Binary-Coded-Decimal GTB Gray to Binary 15 XEC Execute XED Execute Double MME Master Mode Entry DRL Derail RPT Repeat 20 RPD Repeat Double RPL Repeat Link FICCL Read Calendar Clock SPL Store Pointers and Lengths LPL Load Pointers and Lengths 25 ADDRESS REGISTER LARn Load Address Register n LAREG Load Address Registers SARn Store Address Register n 30 SAREG Store Address Registers AWD Add Word Displacement to Specified AR A9BD Add 9-bit Character Displacement To Specified AR A6BD Add 6-bit Character Displacement To Specified AR A4BD Add 4-bit CharacterDisplacement To Specified AR ABD Add Bit Displacement to Specified AR 35 SWD Subtract Word Displacement from Specified AR S9BD Subtract 9-bit Character Displacement from Specified AR S6BD Subtract 6-bit Character Displacement from Specified AR S4BD Subtract 4-bit Character Displacement from Specified AR SBD Subtract Bit Displacement from Specified AR 40 AARn Alphanumeric Descriptor to ARn NARn Numeric Descriptor to ARn ARAn ARn to Alphanumeric Descriptor ARNn ARn to Numeric Descriptor MASTER MODE 45 DIS Delay Until Interrupt LBAR Load Base Address Register LDT Load Timer Register LLUF Load Lockup Fault Register SCPR Replaced with SFR 50 SFR Store Fault Register LCCL Load Calendar Clock RIMR Read Interrupt Mask Register LIMR Load Interrupt Mask Register RRES Read Reserved Memory 55 CIOC Connect 1/0 Channel 82 GB 2 080 989 A 82 APPENDIX A (cont'd) SINGLE WORD INSTRUCTIONS EXTENDED MEMORY LBER Load Base Extension Register LMBA Load Master Bar A 5 LMBB Load Master Bar B SBER Store Base Extension Register SMBA Store Master Bar A SMBB Store Master Bar B MI-DA Master Load A 10 MI-DQ, Master Load Q MI-DA0 Master Load AQ MSTA Master Store A MSTQ Master Store Q MSTAQ Master Store AQ 15 RPN Read Processor Number HALT Halt MULTIWORD INSTRUCTIONS ALPHANUMERIC MLR Move Alphanumeric Left to Right 20 MRL Move Alphanumeric Right to Left MVT Move Alphanumeric With Translation CMPC Compare Alphanumeric Character String SCD Scan Character Double SCDR Scan Character Double in Reverse 25 TCT Test Character and Translate TCTR Test Character and Translate in Reserve SCM Scan With Mask SCMR Scan With Mask in Reserve NUMERIC 301 MV N Nove Numeric CMPN Compare Numeric AD3D Add Using three Decimal Operands AD2D Add Using two Decimal Operands SB3D Subtract Using 3 Decimal Operands 35 SB2D Subtract Using 2 Decimal Operands MP3D Multiply Using 3 Decimal Operands MP2D Multiply Using 2 Decimal Operands DV3D Divide Using 3 Decimal Operands DV21) Divide Using 2 Decimal Operands 40 BIT STRING CSI- Combine Bit Strings Left CSR Combine Bit Strings Right SZTL Set Zero and Truncation Indicator with Bit Strings Left SZTR Set Zero and Truncation Indicator with Bit Strings Right 45 CMPB Compare Bit Strings CONVERSION DTB Decimal to Binary Convert BTD Binary to Decimal Convert 83 GB 2 080 989 A 83- APPENDIX A (cont'd) MULTIWORD INSTRUCTIONS MVE Move Alphanumeric Edited MVNE Move Numeric Edited EDIT MOVE MULTIWORD CMPCT Compare Characters and Translate MTR Move to Register MTM Move to Memory 10 MVNX Move Numeric Extended CMPNX Compare Numeric Extended AD3DX Add Using three Decimal Operands Extended AD2DX Add Using two Decimal Operands Extended SB3DX Subtract Using 3 Decimal Operands Extended 15 SB2DX Subtract Using 2 Decimal Operands Extended MP3DX Multiply Using 3 Decimal Operands Extended MP2DX Multiply Using 2 Decimal Operands Extended DV3DX Divide Using 3 Decimal Operands Extended DV213X Divide Using 2 Decimal Operands Extended 20 MVNEX Move Numeric Edited Extended VIRTUAL MEMORY MANAGEMENT PRIVILEGED INSTRUCTIONS LDWS Load Working Space Registers STWS Store Working Space Registers LDSS Load Safe Store Register 25 STSS Store Safe Store Register LDAS Load Argument Stack Register LDPS Load Parameter.Stack Register LPDBR Load Page Table Directory Base Register SPDBR Store Page Table Directory Base Register 30 LDDSD Load Data Stack Descriptor Register STDSD Store Date Stack Descriptor Register 11DDSA Load Data Stack Address Register STDSA Store Data Stack Address Register CAMP Clear Associative Memory Paged 35 CCAC Clear Cache EPAT Effective Address and Pointer to Test ALL MODE INSTRUCTIONS I-DO Load Option Register STO Store Option Register 40 STPS Store Parameter Stack Register STAS Store Argument Stack Register PAS POP Argument Stack LDDn Load Descriptor (Register) n SDRn Store Descriptor Register n 45 STPn Store Pointer n LDPn Load Pointer (Register) n STDn Store Descriptor Register n EPPRn Effective Pointer to Pointer (Register) n LDEAn Load Extended Address n 50 CLIMB Domain Transfer 84 GB 2 080 989 A 84

Claims

1. A data processing system comprising:

an addressable main store having a plurality of word locations for storing information including data and instructions; high speed buffer storage means coupled to said main store for providing immediate access and to data and instructions fetched from said main store, said buffer storage means having a plurality of addressable locations, and said buffer storage means including control means for fetching information from said main store; and, processing means coupled to said high speed buffer storage means, said processing means for processing instructions, each instruction including an operation code portion, said processing means including control means for generating signals including memory commands required for the execution of said instructions, said control means including decoder circuit means responsive to signals indicative of an operation code portion coded to specify a predetermined class of instruction to generate memory command signals accompanied by coded command signals specifying a predetermined type of buffer storage read operation and said buffer storage control means being operative in response to said coded command signals to generate signals for forwarding said memory command signals to said main store to fetch the data specified by said command signals when said data is stored in said buffer storage means, such data being fetched for storage in advance of its required use in said buffer storage means without interrupting the operation of said processing means facilitating the execution of each predetermined 20 class of instruction.

2. The system of claim 1 wherein said buffer storage control means includes interfaces signaling means coupled to said processing control means for inhibiting the operation of said processing means when said buffer storage means is unable to provide immediate access to said requested data, said buffer storage control means including means operative in response to signals coded to specify said predetermined type of buffer read operation to inhibit the switching of said interface signaling means so as to enable said processing control means to continue the processing of said instruction in parallel with the fetching of said data from said main store.

3. The system of claim 1 or claim 2 wherein each instruction further includes a number of address portions and wherein said main store is organized into a plurality of sets of blocks of word locations, 30 said memory command signals including a command code specifying the type of main store read operation and an address generated from one of said address portions specifying the data word to be fetched and said decoder circuit means including circuit means operative to generate signals corresponding to said command code coded to specify the reading out from main store of a block of data words including said data word specified by said command address. 35

4. The system of claim 3 wherein each main store set being defined by a set address correspondong to the low order portion of said command address and each main store block being identified by a block address.corresponding to the high order portion of said command address and wherein said buffer storage plurality of addressable word locations are arranged in a plurality of sets of blocks of word locations defined by said set addresses and block addresses, said buffer storage 40 means further including:

register means for storing said memory read command from said processor; a data directory having a plurality of locations corresponding in number to the number of sets in said buffer storage means and being addressable-by said set addresses, each location of said data directory storing the block addresses of blocks of words within the associated set stored in said buffer 45 storage means, said data directory responsive to said low order portion of said command address from said processing means to read out said block addresses corresponding to said high order portion of said command address; and, comparison means coupled to said data directory and to said processing means for comparing said block addresses read from said data directory with the high order portion of said command address 50 and generating a hit-miss detection signal indicative of whether or not the data word being requested is stored in said buffer storage means, said buffer storage control means in response to said miss signal generating signals for transferring said memory read command to said main store for fetching the words of block containing said requested data word for inhibiting said means from switching said bistate interface means signals 55 for storing said words of said block into said buffer storage means without transfer of data words to said processing means.

5. The system of claim 3 or claim 4 wherein said processing unit further includes address preparation means coupled to said processing control means for generating command addresses from said instruction address portions and output means for applying said memory requests to said buffer 60 storage means, said output means being coupled to said circuit means, said address preparation means, said processing control means and to said buffer storage means, said processing control means being operative in response to said operation code portion having said predetermined code to generate signals for conditioning said address preparation means to generate said command address portion and for Z GB 2 080 989 A 85 conditioning said output means to apply said command code and said command address to said buffer storage means.

6. The system of any preceding claim wherein said processing control means further includes:

cycle control means including said decoder circuit means for generating signals which define processor cycles required for controlling the operation of said processing means during the certain ones of different phases of processing of each of said instructions, said cycle control means in response to said signals indicative of said predetermined class of instruction being operative to condition said decoder circuit means during a first one of said different phases for generating said coded command signals specifying said predetermined type of buffer storage operation.

7. The system of claim 6 wherein said different phases of processing include an instruction cycle (110 cycle) wherein. i nstru ctio n operand addresses are generated, a cache cycle (C cycle) wherein said buffer in response to processor command signals fetches a number of operands specified by said instruction and an execution cycle (E cycle) wherein the manipulations specified by said instruction operation code to be performed upon said operands are executed by said processing means and wherein said first different phases corresponds to said 1 cycle.

8. The system of claim 7 wherein said cycle control means further includes instructiun cycle control state means for generating signals corresponding to sequences of control states in accordance with the coding of the operation code portions of said instructions defining the sequences of operations to be performed by said processing means during said 1 cycle phase of operation, said 1 cycle control means in response to the operation code specifying said predetermined class of instruction generating 20 one of said sequences including a predetermined control state and said decoder circuit means being conditioned during said predetermined control state to generate said coded command signals specifying said predetermined type of buffer storage operation.

9. The -System of claim 8 wherein said predetermined class of instruction includes a number of address portions for specifying the locations of a corresponding number of operands respectively and 25 wherein said processing unit further includes address preparation means coupled to said processing control means for generating command addresses from said instruction address portions, said 1 cycle control means in response to said predetermined type of instruction operation code portion being operative.to generate a number of said predetermined control states and said decoder circuit means being conditioned during each of said number of predetermined control states to generate said coded 30 command signals specifying said predetermined type of buffer storage operation for fetching in advance data words corresponding to a different one of said number of operands and to generate signals for conditioning said address preparation means during each of said number of predetermined control states to generate a command address from a different one of said number of address portions enabling said processing means to perform address preparation and operand fetching operations concurrently. 35

10. The system of any of claims 7-9 wherein said control means further includes microprogram control means including:

an addressable address store coupled to receive signals corresponding to said operation code portion said address store including a plurality of locations, each for storing a word including at least a first adress identifying a first microinstruction of a different one of a plurality of execution sequences 40 and an output register connected to said store for storing the word contents of a location specified by said operation code portion; and, a cycled addressable control store including a plurality of locations storing at least one microinstruction of a different one of said plurality of execution sequences required for controlling the operation of said processing means during the execution of said instructions during said E cycle phase 45 of operation and an output register connected to said control store and to said decoder circuit means, said output register for temporarily storing the microinstruction contents of an accessed location during a cycle of operation of said control store.

11. The system of claim 10 wherein one of said plurality of execution sequences includes a number of microinstructions coded for conditioning said processing unit during execution of the 50 operation specified by said operation code portion specifying said predetermined class of instruction, each of said microinstructions including a number of fields, at least one of said number of fields being used to specify buffer storage commands and decoder circuit means being coupled to said control store output register, said decoder circuit means being operative in response to signals from said one field of each microinstruction read out from said control store containing a predetermined code to generate 55 additional command signals specifying said predetermined type of buffer storage read operation included in said memory read request for fetching operand data specified by said memory request for storage in advance during the execution of said predetermined type of instruction by said processing means under microprogram control.

12. The system of any of claims 7-11 wherein during said E cycle phase of operation said control 60 store reads out a microinstruction including said one field coded to specify buffer storage read single operation included within said memory request for fetching an operand data word previously fetched in response to coded command signals generated during said 1 cycle phase of operation specifying said predetermined type of buffer storage operation; said data directory being operative in response to úaid low order portion of said command address 65 86 GB 2 080 989 A 86 from said processing means to read out said block addresses corresponding to said low order portion of said command address; said comparison means upon comparing said block addresses read from said data directory with the high order portion of said command address generating a hit detection signal indicating that the word beig requested is now stored in said buffer storage means; and, said buffer storage control means in response to said hit detection signal generating signals for transferring said requested data word to said processing means and for processing said request as requiring no operation whereby said processing means is able to continue execution of said predetermined class of instruction by having immediate access to said requested data word.

13. The system of claim 11 or claim 12 wherein said processing unit further includes execution 10 means for executing the operations specified by the operation code portions of said instructions, said execution means being coupled to said control store output register for receiving signals corresponding to certain fields of each microinstructions read out from said control store during said E cycle of operation and said execution means being conditioned by each microinstruction containing said predetermined code in said one field to execute the operation specified by said predetermined type of instruction upon said operands concurrent with fetching said operand data.

14. The system of any of claims 10-13, wherein said microprograrn control means further includes branch control means having a number of test inputs and coupled to said control store for conditioning said control store to branch to microinstructions within said sequence in accordance with signals applied to said inputs and said branch control means in response to signals from said execution 20 means applied to certain ones of said test inputs to condition said control store to branch to locations within said control store for repeating the execution of said microinstructions containing said predetermined codes for generating a succession of coded command signals, each specifying said predetermined type of buffer storage read operation.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1982. Published by the Patent Office. 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.