JPS55121554A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS55121554A
JPS55121554A JP2842979A JP2842979A JPS55121554A JP S55121554 A JPS55121554 A JP S55121554A JP 2842979 A JP2842979 A JP 2842979A JP 2842979 A JP2842979 A JP 2842979A JP S55121554 A JPS55121554 A JP S55121554A
Authority
JP
Japan
Prior art keywords
write
via control
contents
registers
control lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2842979A
Other languages
Japanese (ja)
Inventor
Masanobu Akagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2842979A priority Critical patent/JPS55121554A/en
Publication of JPS55121554A publication Critical patent/JPS55121554A/en
Pending legal-status Critical Current

Links

Landscapes

  • Retry When Errors Occur (AREA)

Abstract

PURPOSE: To make it possible to initialize a write buffer when a fault occurs by storing the write buffer with data to be written in a main memory unit supplied through a sequence of operations, the retry unit of a processor, during a period of the retry unit and then by leaving the content of the main memory unit unchanged.
CONSTITUTION: Write control circuit 300, when processor 10 indicates its initialization via control line 102, sends an initialization indication via control lines 3001W 3008 to clear the contents of write address registers 101W104, and write data registers 111W114, thereby emptying rite buffer 100. Once a write operation indication is supplied via control line 1002, registers 111W114 are indicated via control lines 3001W3007 that the contents supplied via buses 1005W1131 should be inputted, namely, the contents should be shifted, stage by stage. At the same time, registers 101W104 are indicated via control lines 3002W3008 that the contents supplied via buses 1004W1031 respectively should be inputted and shifted.
COPYRIGHT: (C)1980,JPO&Japio
JP2842979A 1979-03-12 1979-03-12 Information processing system Pending JPS55121554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2842979A JPS55121554A (en) 1979-03-12 1979-03-12 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2842979A JPS55121554A (en) 1979-03-12 1979-03-12 Information processing system

Publications (1)

Publication Number Publication Date
JPS55121554A true JPS55121554A (en) 1980-09-18

Family

ID=12248409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2842979A Pending JPS55121554A (en) 1979-03-12 1979-03-12 Information processing system

Country Status (1)

Country Link
JP (1) JPS55121554A (en)

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