JPS5580896A - Memory initial setting system - Google Patents

Memory initial setting system

Info

Publication number
JPS5580896A
JPS5580896A JP15206378A JP15206378A JPS5580896A JP S5580896 A JPS5580896 A JP S5580896A JP 15206378 A JP15206378 A JP 15206378A JP 15206378 A JP15206378 A JP 15206378A JP S5580896 A JPS5580896 A JP S5580896A
Authority
JP
Japan
Prior art keywords
register
written
value
address
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15206378A
Other languages
Japanese (ja)
Inventor
Hiroshi Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15206378A priority Critical patent/JPS5580896A/en
Publication of JPS5580896A publication Critical patent/JPS5580896A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the misrecognition of the memory fault by writing the specified data into the all addresses or the specified area of the volatile memory before or after loading of the initial program.
CONSTITUTION: The total number of the address into which 0 is to be written is set first at working register WR301, and then delivered through signal line 302 when the contents of register WR301 becomes zero. Then the address into which 0 is written first is set, and memory address register 102 and memory buffer register 103 are selected through register selection part 204. And the 0-value is designated to arithmetic circuit 111 via control signal part 205, and then the 0-value is written into the address of register 102. After this, 1 is subtracted from the value of WR301, and the necessary process is repeated until the fact is detected that the value of WR301 becomes zero. In such way, 0 is written into all addresses into which 0 is not written by the initial program load.
COPYRIGHT: (C)1980,JPO&Japio
JP15206378A 1978-12-11 1978-12-11 Memory initial setting system Pending JPS5580896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15206378A JPS5580896A (en) 1978-12-11 1978-12-11 Memory initial setting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15206378A JPS5580896A (en) 1978-12-11 1978-12-11 Memory initial setting system

Publications (1)

Publication Number Publication Date
JPS5580896A true JPS5580896A (en) 1980-06-18

Family

ID=15532237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15206378A Pending JPS5580896A (en) 1978-12-11 1978-12-11 Memory initial setting system

Country Status (1)

Country Link
JP (1) JPS5580896A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57105037A (en) * 1980-12-22 1982-06-30 Nec Corp Loading system of microprogram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57105037A (en) * 1980-12-22 1982-06-30 Nec Corp Loading system of microprogram

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