JPS567162A - Memory sharing device for arithmetic control unit - Google Patents

Memory sharing device for arithmetic control unit

Info

Publication number
JPS567162A
JPS567162A JP8244179A JP8244179A JPS567162A JP S567162 A JPS567162 A JP S567162A JP 8244179 A JP8244179 A JP 8244179A JP 8244179 A JP8244179 A JP 8244179A JP S567162 A JPS567162 A JP S567162A
Authority
JP
Japan
Prior art keywords
ram9
cpu1
signal
data
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8244179A
Other languages
Japanese (ja)
Inventor
Jun Miyazaki
Kazuyasu Nagatomi
Yoshitaka Shimamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8244179A priority Critical patent/JPS567162A/en
Publication of JPS567162A publication Critical patent/JPS567162A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Digital Computer Display Output (AREA)
  • Memory System (AREA)

Abstract

PURPOSE: To realize the sharing of the memory to enhance the economical properties, by securing the direct write/read of the data storing memory part used for the I/O device or the like for the CPU.
CONSTITUTION: When the address of sharing RAM9 and the memory write signal are delivered from CPU1, the address detection is carried out at address bus control part 8. Thus address detection signal (a) is delivered to inhibit the output given from memory control part 11. At the same time, the address signal sent from the CPU is supplied to RAM9 from part 8. On the other hand, the inhibition state of data bus control part 10 is released by signal (a), and the data sent from CPU1 is written into RAM9. When the read signal is delivered from CPU1, part 10 is switched to the output state with the data from RAM9 read to CPU1. When no write/read is carried out through the CPU, the output inhibition state of part 11 is released. And the data from RAM9 is displayed at display part 7 through driver 12.
COPYRIGHT: (C)1981,JPO&Japio
JP8244179A 1979-06-29 1979-06-29 Memory sharing device for arithmetic control unit Pending JPS567162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8244179A JPS567162A (en) 1979-06-29 1979-06-29 Memory sharing device for arithmetic control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8244179A JPS567162A (en) 1979-06-29 1979-06-29 Memory sharing device for arithmetic control unit

Publications (1)

Publication Number Publication Date
JPS567162A true JPS567162A (en) 1981-01-24

Family

ID=13774621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8244179A Pending JPS567162A (en) 1979-06-29 1979-06-29 Memory sharing device for arithmetic control unit

Country Status (1)

Country Link
JP (1) JPS567162A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147303A (en) * 1984-12-20 1986-07-05 Mitsubishi Electric Corp Access method of special unit
JPS63192152A (en) * 1987-02-04 1988-08-09 Nec Corp Data transfer system
JPS63271524A (en) * 1988-03-25 1988-11-09 Seiko Epson Corp Microcomputer
US6798711B2 (en) * 2002-03-19 2004-09-28 Micron Technology, Inc. Memory with address management

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5436138A (en) * 1977-08-26 1979-03-16 Nec Corp Direct memory access system
JPS5440040A (en) * 1977-09-06 1979-03-28 Toshiba Corp Common bus control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5436138A (en) * 1977-08-26 1979-03-16 Nec Corp Direct memory access system
JPS5440040A (en) * 1977-09-06 1979-03-28 Toshiba Corp Common bus control system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147303A (en) * 1984-12-20 1986-07-05 Mitsubishi Electric Corp Access method of special unit
JPS63192152A (en) * 1987-02-04 1988-08-09 Nec Corp Data transfer system
JPS63271524A (en) * 1988-03-25 1988-11-09 Seiko Epson Corp Microcomputer
JPH042971B2 (en) * 1988-03-25 1992-01-21
US6798711B2 (en) * 2002-03-19 2004-09-28 Micron Technology, Inc. Memory with address management
US7123541B2 (en) 2002-03-19 2006-10-17 Micron Technology Inc. Memory with address management
US7372768B2 (en) 2002-03-19 2008-05-13 Micron Technology, Inc. Memory with address management

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