JPS63192152A - Data transfer system - Google Patents

Abstract

PURPOSE:To transfer data to a remote memory at the processing speed of a microprocessor kept at a high level by transferring the data to a remote memory at a comparatively low speed under the control of a timing circuit after all transfer data are stored in a buffer memory. CONSTITUTION:A timing signal is transmitted from an interface 2 while data are transferred to a remote memory area from a microprocessor 1. Then a data bus 11 is connected between a buffer memory 6 and the microprocessor 1 while data are transferred by a data bus buffer 3. When this transfer of data is ended, the bus 11 is cut off between the memory 6 and the microprocessor 1. A timing circuit 5 produces an address of a fixed cycle and read/write signals when the transfer of data is ended with the microprocessor 1 and supplies them to the memory 6 via a selector circuit 4. In such a way, data are stored temporarily in the different memory 6 and then transferred to a remote main memory 9 at a comparatively low speed after all data are stored. In such a way, the processing speed of the microprocessor 1 is kept at a high level.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to data transmission, and more particularly to techniques for a microprocessor to write data to a remote memory.

[Conventional technology]

Conventionally, when a microprocessor writes data to a remote memory, the following method has been used.

(1) To use an unbalanced line receiver/driver, reduce the microprocessor clock or provide a wait circuit.

(2) Use a balanced line receiver/driver.

[Problem that the invention seeks to solve]

The conventional method (1) described above has the disadvantage that the memory access time of the CPU increases and the processing time becomes long.

Also, with method (2), theoretically 40 feet away and 1
It is possible to transmit up to 0M baud, but the transmission rate decreases over longer distances (100M baud at 4000 feet).
nibo). In reality, it is necessary to design with a margin of about 2 to 3 times, so even with method (2), the microprocessor clock is considered to have a limit of 5 MHz, and it is difficult to increase the speed beyond this.

[Means for solving problems]

In the data transmission method of the present invention, the data to be written to the memory output by the microprocessor is temporarily stored in another buffer memory, and after all the data is stored in the buffer memory, Memo IJK Data transfer is in danger.

Therefore, the data transmission method of the present invention includes an interface that outputs a signal that identifies the transmission timing of the microprocessor on hardware, a timing circuit that generates address, read, and write signals separately from the microprocessor, and a A buffer that connects the data bus between backup memories to 0N10FF, and a selector circuit that switches address, read, and write signals.
A buffer memory that temporarily stores write data from the microprocessor, a line driver that drives data signals from the buffer memory and address, read, and write signals from the selector circuit, and a line receiver that receives these signals from a remote location. Consists of main memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

1 sends timing signals from the interface of 2 while the microprocessor transfers data to a remote memory area. A data bus buffer 3 connects the buffer memory 6 and the data bus of the microprocessor during data transfer. When the data transfer is completed, the data bus between the two is disconnected. A timing circuit 5 generates fixed-cycle address, read, and write signals when data transfer from the microprocessor is completed. It also generates system timing and sends interrupt signals to the microprocessor. 4 is a selector circuit that switches whether address, read, or write signals are supplied to the buffer memory 6 from either the microprocessor 1 or the timing circuit 5. 6 is a buffer memory 9. This is a memory that stores data from the microprocessor in place of the remote memory. 7 is a buffer and is in a 70-ting state so that each signal is not transmitted to the remote memory 9 while the buffer memory 6 is being accessed. The buffer memory acts as a driver when under the control of the timing circuit 5. 8 is a receiver circuit which receives the signal from the buffer 7. 9 is a remote main memory.

〔Effect of the invention〕

As explained above, the present invention temporarily stores data output from a microprocessor in another buffer memory, and after all transfer data is stored in the buffer memory, controls a newly provided timing circuit. By transferring data to a remote memory at a relatively low speed, it is possible to transfer data to a remote memory while maintaining a high processing speed of the microprocessor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1...Microprocessor, 2...Interface, 3...Buffer, 4...
... Selector circuit, 5 ... Timing circuit, 6
... Buffer memory, 7 ... Buffer, 8 ... Receiver, 9 ... Main memory,
10... Address bus, 11... Data bus, 12... Control bus, 13...
...')-)": Shift signal, 14...Address signal generated by the timing circuit, 15...
9 read/write signals generated by the timing circuit, 16... data transfer timing signal, 1
7...Read signal, 18...Interrupt signal.

Claims (1)

[Claims] A buffer memory that temporarily stores data from the microprocessor, an interface that outputs data transmission timing, and an address and
The timing circuit that generates read and write signals and the data bus between the microprocessor and buffer memory are
A selector circuit that selects the buffer to be turned on/off, an address, read, and write signal, a line driver that drives the data signal from the buffer memory, and an address, read, and write signal from the selector circuit, and a line driver that drives the signal remotely. A data transmission method that includes a line receiver that receives the data, and a main memory.